CN213782012U

CN213782012U - Semiconductor packaging structure

Info

Publication number: CN213782012U
Application number: CN202023107980.5U
Authority: CN
Inventors: 霍炎; 涂旭峰
Original assignee: SIPLP Microelectronics Chongqing Ltd
Current assignee: SIPLP Microelectronics Chongqing Ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2021-07-23
Anticipated expiration: 2030-12-21

Abstract

The application provides a semiconductor packaging structure. The semiconductor packaging structure comprises an encapsulation structure, a rewiring layer, a dielectric layer and a pin layer. The encapsulation structure comprises an encapsulation layer and a chip, wherein the front surface of the chip is provided with a plurality of welding pads, and the encapsulation layer at least covers the side surface of the chip. The rewiring layer is located on one side, close to the front face of the chip, of the encapsulation structure, and the rewiring layer leads out the welding pads of the chip. The dielectric layer covers the rewiring layer, and through holes for exposing partial rewiring layer are formed in the dielectric layer. The pin layer is located on one side, away from the chip, of the dielectric layer, and the pin layer is electrically connected with the rewiring layer through the through hole.

Description

Semiconductor packaging structure

Technical Field

The present disclosure relates to semiconductor technologies, and particularly to a semiconductor package structure.

Background

The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: for the process of carrying out the technical treatment on the front surface of the chip, firstly, the front surface of the chip is attached to a carrier plate, hot-press plastic package is carried out, the carrier plate is stripped, then a rewiring layer and a pin layer positioned on one side, away from the chip, of the rewiring layer are formed on the front surface of the chip, then an insulating layer is formed, the rewiring layer is covered by the insulating layer, and the surface, away from the chip, of the pin layer is exposed out of the insulating layer.

In the existing chip packaging technology, because the pin layer is formed on one side of the rewiring layer, which is far away from the chip, and the area of the rewiring layer is larger than that of the pin layer, the area of the rewiring layer is generally larger, and the contact area of the rewiring layer and an insulating protection layer of the chip is larger. Because the difference between the thermal expansion coefficients of the rewiring layer and the insulating protection layer is large, the stress difference between the rewiring layer and the insulating protection layer is large due to the temperature rise of the rewiring layer in the preparation or chip working process, and the rewiring layer and the plastic packaging layer can be layered or warped possibly to influence the normal work of a product.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a semiconductor packaging structure. The semiconductor package structure includes:

the packaging structure comprises a packaging layer and a chip, wherein the front surface of the chip is provided with a plurality of welding pads, and the packaging layer at least covers the side surface of the chip;

the rewiring layer is positioned on one side of the encapsulation structure close to the front surface of the chip and leads out a welding pad of the chip;

the dielectric layer covers the rewiring layer, and a through hole for exposing part of the rewiring layer is formed in the dielectric layer;

and the pin layer is positioned on one side of the dielectric layer, which is far away from the chip, and is electrically connected with the rewiring layer through the through hole.

In one embodiment, the pin layer includes a plurality of conductive pillars arranged at intervals, and the conductive pillars protrude from the dielectric layer; the semiconductor packaging structure further comprises a solder layer, and the solder layer coats the conductive convex columns and protrudes out of the surface of the dielectric layer.

In one embodiment, the pin layer includes a plurality of conductive pillars arranged at intervals, and the conductive pillars protrude from the dielectric layer; a conductive part is arranged in the through hole, the pin layer is electrically connected with the rewiring layer through the conductive part, and a depression is formed at the position of the conductive part corresponding to the through hole; the semiconductor packaging structure further comprises a solder layer, the solder layer coats the conductive convex columns and protrudes out of the surface of the dielectric layer, and the solder layer fills the depressions.

In one embodiment, the ratio of the width to the depth of the via is greater than or equal to 1/3.

In one embodiment, the depth of the through hole ranges from 60 μm to 100 μm; the thickness range of the part of the conductive part, which is positioned on the bottom wall of the through hole, is 10-50 mu m.

In one embodiment, the thickness of the pin layer is greater than 30 μm.

In one embodiment, the rewiring layer comprises a plurality of rewiring structures arranged at intervals, and the rewiring structures are provided with hollowed-out parts.

In one embodiment, the front surface of the chip is further provided with a protective layer, and the protective layer is provided with an opening for exposing the welding pad;

and a conductive structure is formed in the opening, and the rewiring layer is electrically connected with the welding pad through the conductive structure.

In one embodiment, the semiconductor package structure further comprises a heat dissipation layer located on a side of the dielectric layer facing away from the chip;

the semiconductor packaging structure further comprises a solder layer, and the solder layer coats the surface of the part of the heat dissipation layer protruding out of the dielectric layer.

In one embodiment, a conductive part is arranged in the through hole, the pin layer is electrically connected with the rewiring layer through the conductive part, and the material of the conductive part is the same as that of the pin layer.

The embodiment of the application achieves the main technical effects that:

in the semiconductor packaging structure provided by the embodiment of the application, the dielectric layer covers the rewiring layer, the pin layer is positioned on one side of the dielectric layer, which is far away from the rewiring layer, and the pin layer is electrically connected with the rewiring layer through the through hole on the dielectric layer, namely the pin layer is not directly contacted with the rewiring layer, so that the size of the pin layer is not influenced by the size of the rewiring layer, the size of the rewiring layer can be set to be smaller, the contact area between the rewiring layer and an adjacent insulating layer such as the dielectric layer is reduced, the stress difference between the rewiring layer and the adjacent insulating layer is reduced, the risk that the rewiring layer and the adjacent insulating layer are layered or the rewiring layer is warped is reduced, and the quality of a product is improved; the pin layer is not in direct contact with the rewiring layer, the influence of the rewiring layer on the thickness of the pin layer is small, the thickness of the pin layer is designed more freely, the increase of the thickness of the formed pin layer is facilitated, the breakdown voltage of the semiconductor packaging structure is further increased, the semiconductor packaging structure is facilitated to be applied to a high-voltage environment, and the application range of the semiconductor packaging structure is enlarged.

Drawings

FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

FIG. 2 is a flow chart of forming an encapsulated structure provided by an exemplary embodiment of the present application;

FIG. 3 is a partial cross-sectional view of a first intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

FIG. 4 is a partial cross-sectional view of a second intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

FIG. 5 is a partial cross-sectional view of an encapsulated structure provided by an exemplary embodiment of the present application;

fig. 6 is a partial cross-sectional view of a third intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;

fig. 7 is a partial cross-sectional view of a third intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;

fig. 8 is a partial cross-sectional view of a fourth intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;

fig. 9 is a partial cross-sectional view of a fifth intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;

fig. 10 is a partial cross-sectional view of a sixth intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;

fig. 11 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;

fig. 12 is a partial cross-sectional view of a semiconductor package structure provided in an exemplary embodiment of the present application;

fig. 13 is a partial cross-sectional view of a semiconductor package structure after soldering to a circuit board according to an exemplary embodiment of the present application;

fig. 14 is a partial cross-sectional view of a semiconductor package structure provided in another exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 140.

In step 110, an encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and a chip, the front surface of the chip is provided with a plurality of bonding pads, and the encapsulation layer at least covers the side surface of the chip.

In step 120, a redistribution layer is formed on one side of the encapsulation structure close to the front surface of the chip, and the redistribution layer leads out a bonding pad of the chip.

In step 130, a dielectric layer is formed, the dielectric layer covering the redistribution layer and having a via exposing the redistribution layer.

In step 140, a lead layer is formed on a side of the dielectric layer away from the chip, and the lead layer is electrically connected to the redistribution layer through the through hole.

According to the semiconductor packaging method provided by the embodiment of the application, the dielectric layer covers the rewiring layer, the pin layer is located on one side, away from the rewiring layer, of the dielectric layer, and the pin layer is electrically connected with the rewiring layer through the through hole in the dielectric layer, namely the pin layer is not directly contacted with the rewiring layer, so that the size of the pin layer is not influenced by the size of the rewiring layer, the size of the rewiring layer can be set to be smaller, the contact area between the rewiring layer and an adjacent insulating layer such as the dielectric layer is reduced, the stress difference between the rewiring layer and the adjacent insulating layer is reduced, the risk that the rewiring layer and the adjacent insulating layer are layered or the rewiring layer is warped is reduced, and the quality of a product is improved; the pin layer is not in direct contact with the rewiring layer, the thickness of the pin layer is not affected by the rewiring layer to be small, the thickness of the pin layer is designed more freely, the increase of the thickness of the formed pin layer is facilitated, the breakdown voltage of the semiconductor packaging structure is further increased, the semiconductor packaging structure is facilitated to be applied to a high-voltage environment, and the application range of the semiconductor packaging structure is enlarged.

The steps of the semiconductor packaging method provided by the embodiments of the present application will be described in detail below.

In one embodiment, the encapsulation structure may include one or more chips, the encapsulation layer is provided with recessed cavities corresponding to the chips one to one, and the chips are located in the corresponding recessed cavities.

In one embodiment, referring to fig. 2, the step 110 of forming the encapsulation structure includes the following steps 111 to 113.

In step 111, the chip is mounted on a carrier, and the front surface of the chip faces the surface of the carrier.

A first intermediate structure as shown in fig. 3 is obtained by step 111. In the embodiment shown in fig. 3, a chip 20 is mounted on the carrier 10. In other embodiments, the number of the chips 20 mounted on the carrier board 10 may be plural.

In one embodiment, the carrier board 10 includes a mounting area for mounting the chip 20. The shape of the mounting area is designed according to the layout of the chips 20 on the whole carrier 10, and may include a circle, a rectangle or other shapes. The carrier plate may comprise one or more mounting areas.

In one embodiment, the shape of the carrier plate 10 may be circular, rectangular or other shape. The material of the carrier plate 10 may be iron-nickel alloy, or the material of the carrier plate 10 may also be stainless steel, polymer, etc.

In one embodiment, the chip 20 may be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.

The bonding pad 21 of the chip 20 is formed by a conductive electrode which is led out from the internal circuit of the chip to the surface of the chip. The front surface of the chip 20 may be provided with a plurality of pads 21. The pads 21 are used to lead out the conductive electrodes of the chip 20.

In one embodiment, before the step 111 of mounting the chip on a carrier board, the semiconductor packaging method further includes: a protection layer 22 is formed on the front surface of the chip 20, and an opening 23 for exposing the pad 21 is formed on the protection layer 22.

In some embodiments, opening 23 may be formed in protective layer 22 by a laser process. The size of the opening 23 may be smaller than that of the pad 21, and the opening 23 exposes a portion of the surface of the pad 21 facing away from the carrier 10.

The material of the protective layer 22 may be a plastic film, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite, or other materials with similar properties. In some embodiments, organic or inorganic fillers may also be added to the protective layer 22.

In the subsequent step 112 of forming the encapsulation layer, since the encapsulation layer needs to be formed under high pressure during the forming process, the encapsulation material forming the encapsulation layer easily penetrates between the carrier 10 and the chip 20. By forming a protection layer 22 on the front surface of the chip 20, the protection layer 22 can prevent the encapsulating material from penetrating into the surface of the chip 20, and even if the encapsulating material penetrates into the protection layer 22 when the encapsulating layer is formed, after the carrier 10 is peeled off from the chip 20, the surface of the protection layer 22 can be directly treated by a chemical method or a grinding method without directly contacting the front surface of the chip 20, so that the pad on the front surface of the chip 20 can be prevented from being damaged.

In one embodiment, the die 20 may be attached to the carrier plate 10 by an adhesive layer, and the adhesive layer may be a material that is easily peeled off so as to later peel the die 20 from the carrier plate 10, for example, the adhesive layer may be a thermal release material that can be heated to lose its adhesiveness.

In step 112, an encapsulation layer is formed, and the encapsulation layer covers the carrier and encapsulates the chip.

A second intermediate structure as shown in fig. 4 may be obtained, via step 112.

Referring to fig. 4, an encapsulation layer 30 is formed on the chip 20 and the exposed carrier 10 for encapsulating the chip 20 to reconstruct a flat plate structure, so that after the carrier 10 is peeled off, re-wiring and packaging can be continued on the reconstructed flat plate structure.

In one embodiment, before the formation of the encapsulating layer 30, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the surfaces of the chip 20 and the carrier 10, so that the connection between the encapsulating layer 30 and the chip 20 and the carrier 10 can be more intimate and no delamination or cracking occurs.

In one embodiment, the encapsulating layer 30 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy compound.

In one embodiment, the step 120 of forming the encapsulation layer may include the steps of:

firstly, an encapsulation structure is formed, and the encapsulation structure covers the carrier plate and coats the chip. In this step, the thickness of the encapsulation structure is greater than the thickness of the chip 20, so that the encapsulation structure completely encapsulates the chip 20.

And then, thinning one side of the encapsulating structure, which is far away from the carrier plate, to obtain the encapsulating layer. In this step, the encapsulating structure may be thinned to a specified thickness by performing a thinning process on the encapsulating structure through a grinding process.

In step 113, the carrier is removed to obtain the encapsulation structure.

An encapsulated structure as shown in fig. 5 may be obtained through step 113. The encapsulation layer covers the back and sides of the chip in the embodiment shown in the drawings. In other embodiments, the encapsulation layer may only encapsulate the sides of the chip, etc.

In one embodiment, the carrier plate 10 can be mechanically peeled off from the encapsulating layer 30 and the chip 20 directly. In another embodiment, the chip 20 and the carrier 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity, so as to peel off the carrier 10. After the carrier 10 is stripped, the front surface of each chip 20 is exposed, that is, the pads of the chip 20 are exposed.

A third intermediate structure as shown in fig. 6 is obtained by step 120. The side of the encapsulation structure close to the front side of the chip refers to the side on which the front side of the chip is located. Referring to fig. 6, rewiring layer 40 includes a plurality of rewiring structures 41. Each redistribution structure 41 may be electrically connected to one pad 21, or may be electrically connected to a plurality of pads 21.

In one embodiment, the opening 23 of the protection layer 22 has a conductive structure 24 formed therein, the conductive structure 24 is in direct contact with the redistribution structure 41, and the redistribution structure 41 is electrically connected to the pad 21 through the conductive structure 24. The conductive structure 24 and the re-wiring structure 41 can be formed in the same process step, which helps to simplify the semiconductor packaging process.

In one embodiment, step 120 may be accomplished by:

firstly, a seed layer is formed on one side of the encapsulation structure close to the front surface of the chip. The seed layer may cover the front side of the chip 20 and cover the inner walls of the opening 23.

Subsequently, a photoresist layer is formed on the side of the seed layer facing away from the chip. The photoresist layer is a patterned film layer.

And then, connecting the seed layer to a power supply, and carrying out electroplating to form a conductive layer in a region, which is not shielded by the photoresist layer, of one side of the first seed layer, which is away from the chip.

Subsequently, the photoresist layer is removed.

And then, carrying out patterning treatment on the seed layer, etching the region of the seed layer which is not shielded by the conductive layer, and forming a rewiring layer by the seed layer and the conductive layer which are not etched.

In one embodiment, referring to fig. 7, the re-wiring structure 41 is provided with a hollowed-out portion 411. Thus, the dimension of the rewiring structure 41 can be reduced, the contact area between the rewiring structure 41 and the adjacent insulating layer can be reduced, and the risk of peeling the rewiring structure 41 from the adjacent insulating layer can be further reduced.

In step 130, a dielectric layer is formed, the dielectric layer covers the redistribution layer, and a through hole exposing the redistribution layer is formed on the dielectric layer.

In one embodiment, step 130 may be accomplished by:

first, a dielectric layer is formed on the encapsulation structure, and the dielectric layer covers the rewiring layer 40 and the exposed encapsulation layer.

By this step a fourth intermediate structure as shown in fig. 8 is obtained. Referring to fig. 8, dielectric layer 50 completely encapsulates rewiring layer 40.

Subsequently, a via hole exposing the rewiring layer is formed on the dielectric layer.

By this step a fifth intermediate structure as shown in fig. 9 is obtained. Referring to fig. 9, a plurality of via holes 51 are provided on the dielectric layer 50. A portion of the dielectric layer 50 corresponding to one re-wiring structure 41 in the longitudinal direction may be provided with one through hole 51 or a plurality of through holes 51, that is, one re-wiring structure 41 may correspond to one through hole 51 or a plurality of through holes 51. The size of the via hole 51 is smaller than that of the re-wiring structure 41, and the via hole 51 exposes a part of the surface of the re-wiring structure 41.

In one embodiment, the material of the dielectric layer 50 may be a plastic film, PI, PBO, organic polymer film, organic polymer composite, or other material with similar properties. In some embodiments, organic or inorganic fillers may also be added to the dielectric layer 50.

In one embodiment, a laser process may be used to form via 51 on dielectric layer 50.

A sixth intermediate structure as shown in fig. 10 is obtained through step 140. Referring to fig. 10, the lead layer 60 includes a plurality of conductive pillars 61 arranged at intervals, and the conductive pillars 61 protrude from the dielectric layer 50.

Because the pin layer 60 is positioned on the side of the dielectric layer 50 departing from the chip 20, and the conductive posts 61 protrude from the dielectric layer 50, the dielectric layer 50 does not need to be ground, and compared with a scheme that the dielectric layer is formed after the pin layer is formed, and the pin layer is exposed by grinding the dielectric layer, the time for grinding the dielectric layer can be saved, the packaging efficiency is improved, and the production cost is reduced; meanwhile, the problem that the thickness uniformity of the dielectric layer is poor due to the low precision of the grinding process can be avoided, the phenomenon that the pin layer is ground when the dielectric layer is ground, the stress on the pin layer damages the welding pad of the chip can be avoided, and the quality of a packaging product is improved.

In one embodiment, the through hole 51 of the dielectric layer 50 has a conductive portion 52 formed therein, the conductive portion 52 is in direct contact with the redistribution structure 41 and a conductive pillar 61, and the conductive pillar 61 is electrically connected to the redistribution structure 41 through the conductive portion 52. The conductive posts 61 and the conductive portions 52 can be formed in the same process step, which helps to simplify the semiconductor packaging process.

In one embodiment, an electroplating process may be used to form the lead layer 60 on the side of the dielectric layer 50 facing away from the chip. Because the pin layer 60 is formed on the dielectric layer 50 and does not directly contact the rewiring layer 40, a conductive layer with a larger thickness can be formed on the side of the dielectric layer 50 away from the chip by an electroplating process, so that the pin layer 60 obtained by etching the conductive layer has a larger thickness.

In one embodiment, the thickness d of the lead layer 60 is greater than 30 μm. By the arrangement, the breakdown voltage of the semiconductor packaging structure can be effectively improved. In some embodiments, the conductive portion 52 and the lead layer 60 are formed simultaneously, which can also prevent the conductive portion 52 from being thinner and causing the portion of the conductive portion 52 located at the sidewall of the through hole 51 to be broken. In some embodiments, the thickness d of the lead layer 60 is, for example, 31 μm, 33 μm, 35 μm, 37 μm, 40 μm, or the like.

In one embodiment, the semiconductor packaging method further includes: a heat sink layer is formed on the side of the dielectric layer 50 facing away from the chip.

Referring to fig. 11, the heat dissipation layer 80 has a larger area, so that the semiconductor package structure has a better heat dissipation effect. Each chip 20 may correspond to one heat dissipation layer 80, and the plurality of conductive pillars 61 of the chip 20 may be located around the corresponding heat dissipation layer 80.

In one embodiment, heat spreading layer 80 may be formed in the same process step as pin layer 60. This helps simplify the semiconductor packaging process. At this time, the heat dissipation layer 80 may fully protrude from the dielectric layer 50.

In one embodiment, after the step 150 of forming a lead layer on a side of the dielectric layer facing away from the chip, the semiconductor packaging method further comprises:

and forming a solder layer which coats the conductive convex columns and protrudes out of the surface of the dielectric layer.

Through this step, a semiconductor package structure as shown in fig. 12 can be obtained.

Because the conductive posts 61 of the lead layer 60 are located on the side of the dielectric layer 50 away from the chip, that is, the conductive posts 61 are all exposed out of the dielectric layer 50, the climbing capability of the solder is better when forming the solder layer, the formed solder layer 70 can completely cover the surfaces of the conductive posts 61 protruding out of the dielectric layer, that is, the solder layer 70 completely covers the sidewalls of the conductive posts 61 and the surface away from the chip 20. Thus, as shown in fig. 13, when the semiconductor package structure is soldered to the circuit board 90, the sidewall of the conductive post 61 and the solder layer 70 away from the surface of the chip 20 can be soldered to the circuit board, and compared with the scheme that the conductive post only faces away from the surface of the chip to expose the dielectric layer and the conductive post only faces away from the surface of the chip to form the solder layer, the reliability of the soldering between the conductive post 61 of the semiconductor package structure obtained in the embodiment of the present application and the circuit board is higher, and compared with the scheme that the solder ball is formed by the reflow soldering process, the process of the embodiment of the present application is simpler.

In some embodiments, the material of the solder layer 70 may be metallic tin, gold-tin alloy, or nickel-based alloy, which can perform a soldering function.

In some embodiments, the solder layer 70 can be formed by electroplating, electroless plating, or screen printing. Preferably, a plating process may be used to form the solder layer 70 on the surface of the conductive posts. Therefore, the thickness of the whole semiconductor packaging structure can be more controllable, the thickness uniformity of the semiconductor packaging structure can be ensured, the packaging efficiency can be effectively improved for board-level packaging, and the cost is reduced; meanwhile, the thickness of the formed solder layer 70 can be increased, and the reliability of the semiconductor packaging structure and other post-joint welding can be improved.

In one embodiment, since the heat dissipation layer 80 is located on the side of the dielectric layer 50 away from the chip, that is, the heat dissipation layer 80 is completely exposed from the dielectric layer 50, the solder layer 70 covers the surface of the portion of the heat dissipation layer 80 protruding from the dielectric layer when the solder layer is formed. When the semiconductor package structure is soldered to the circuit board, the solder layers 70 on the surface of the heat dissipation layer 80 can be soldered to the circuit board, and compared with a scheme that the heat dissipation layer is only away from the surface of the chip, the dielectric layer is exposed, and the solder layer is only formed on the surface of the heat dissipation layer away from the chip, the reliability of soldering the heat dissipation layer and the circuit board of the semiconductor package structure obtained by the embodiment of the application is higher.

In one embodiment, referring again to fig. 11, in forming the solder layer, a tin-plated wire 71 is first formed, the tin-plated wire 71 is electrically connected to each of the conductive posts 61 and the heat dissipation layer 80, and then the tin-plated wire 71 is electrically connected to an external power source for electroplating to form a solder layer 70 on the sidewalls of the conductive posts 61 and the surface facing away from the chip, and the sidewalls of the heat dissipation layer 80 and the surface facing away from the chip.

In one embodiment, referring to fig. 14, the size of the through hole 51 is large, so as to avoid the conductive portion 52 from breaking at the sidewall of the through hole 51 of the dielectric layer 50; the solder layer 70 fills the recesses formed by the conductive portions 52. So, solder layer 70 is bigger with the area of contact of the electrically conductive projection 61 of pin layer 60, and the cohesion is better, can provide sufficient filling space for solder layer 70 simultaneously, can make solder layer 70 thicker, helps promoting semiconductor package structure and circuit board welded reliability.

In some embodiments, the ratio of the width to the depth of the via 51 is greater than or equal to 1/3. Thus, the conductive part 52 is more easily recessed in the through hole 51, which is more helpful to increase the contact area between the conductive pillar 61 and the solder layer 70. The ratio of the width D to the depth H of the through-hole 51 is, for example, 1/3, 1/2, 2/3, 3/4, 3/2, and the like.

In one embodiment, the depth H of the through hole 51 ranges from 60 μm to 100 μm, and the thickness S of the conductive portion 52 at the bottom wall of the through hole 51 ranges from 10 μm to 50 μm. By such an arrangement, it is further helpful to provide sufficient filling space for the solder layer 70 in the through hole 51, so as to improve the reliability of the soldering between the semiconductor package structure and other structures. In some embodiments, the depth H (hereinafter referred to as depth H) of the through hole 51 is 100 μm, the thickness S (hereinafter referred to as thickness S) of the conductive portion 52 at the bottom wall of the through hole 51 is 40 μm, and the width D (hereinafter referred to as width D) of the through hole 51 is 50 μm; alternatively, the depth H is 80 μm, the thickness S is 35 μm, and the width D is 40 μm or 80 μm; alternatively, the depth H is 60 μm, the thickness S is 25 μm, and the width D is 30 μm or 80 μm, etc.

The embodiment of the application also provides a semiconductor packaging structure. Referring to fig. 12 and 14, the semiconductor package structure includes an encapsulation structure, a redistribution layer 40, a dielectric layer 50, and a lead layer 60.

The encapsulating structure comprises an encapsulating layer 30 and a chip 20, wherein a plurality of bonding pads 21 are arranged on the front surface of the chip 20, and the encapsulating layer 30 at least covers the side surface of the chip 20. The rewiring layer 40 is located on one side of the encapsulation structure close to the front surface of the chip 20, and the rewiring layer 40 leads out the bonding pad 21 of the chip 20. The side of the encapsulation structure near the front side of the chip 20 refers to the side on which the front side of the chip 20 is located. The dielectric layer 50 covers the redistribution layer 40, and a through hole 51 exposing a portion of the redistribution layer 40 is formed in the dielectric layer 50. The pin layer 60 is located on a side of the dielectric layer 50 away from the chip 20, and the pin layer 60 is electrically connected to the redistribution layer 40 through the through hole 51.

In the semiconductor packaging structure provided by the embodiment of the application, the dielectric layer covers the rewiring layer, the pin layer is positioned on one side of the dielectric layer, which is far away from the rewiring layer, and the pin layer is electrically connected with the rewiring layer through the through hole on the dielectric layer, namely the pin layer is not directly contacted with the rewiring layer, so that the size of the pin layer is not influenced by the rewiring layer, the area of the rewiring layer can be set to be smaller, the contact area between the rewiring layer and an adjacent insulating layer such as the dielectric layer is reduced, the stress difference between the rewiring layer and the adjacent insulating layer is reduced, the risk of layering between the rewiring layer and the insulating layer or warping of the rewiring layer is reduced, and the quality of a product is improved; the pin layer is not in direct contact with the rewiring layer, the thickness of the pin layer is not affected by the rewiring layer, the thickness of the pin layer is designed more freely, the increase of the thickness of the formed pin layer is facilitated, the breakdown voltage of the semiconductor packaging structure is further increased, the semiconductor packaging structure is facilitated to be applied to a high-voltage environment, and the application range of the semiconductor packaging structure is enlarged.

In one embodiment, a protection layer 22 is formed on the front surface of the chip 20, and an opening 23 is formed on the protection layer 22 to expose the pad 21. The size of the opening 23 may be smaller than the size of the pad 21, and the opening 23 exposes a portion of the surface of the pad 21 facing away from the opening.

The material of the protective layer 22 may be plastic film, PI, PBO, organic polymer film, organic polymer composite, or other material with similar properties. In some embodiments, organic or inorganic fillers may also be added to the protective layer 22.

High pressure molding is required in forming the encapsulation layer, and the encapsulation material forming the encapsulation layer easily penetrates between the carrier 10 and the chip 20 in the process. By forming a protection layer 22 on the front surface of the chip 20, the protection layer 22 can prevent the encapsulating material from penetrating into the surface of the chip 20, and even if the encapsulating material penetrates into the protection layer 22 when the encapsulating layer 30 is formed, after the carrier 10 is peeled off from the chip 20, the surface of the protection layer 22 can be directly treated by a chemical method or a grinding method without directly contacting the front surface of the chip 20, so that the pad on the front surface of the chip 20 can be prevented from being damaged.

In one embodiment, the opening 23 of the protection layer 22 has a conductive structure 24 formed therein, the conductive structure 24 is in direct contact with the redistribution structure 41, and the redistribution structure 41 is electrically connected to the pad 21 through the conductive structure 24. The material of the conductive structure 24 and the material of the re-wiring structure 41 may be the same, so that the conductive structure 24 and the re-wiring structure 41 may be formed in the same process step, which helps to simplify the packaging process for forming the semiconductor package structure.

In one embodiment, rerouting layer 40 includes a plurality of rerouting structures 41 arranged at intervals. Each redistribution structure 41 may be electrically connected to one pad 21, or may be electrically connected to a plurality of pads 21.

In one embodiment, a plurality of vias 51 are provided in the dielectric layer 50. A portion of the dielectric layer 50 corresponding to one re-wiring structure 41 in the longitudinal direction may be provided with one through hole 51 or a plurality of through holes 51, that is, one re-wiring structure 41 may correspond to one through hole 51 or a plurality of through holes 51. The size of the via hole 51 is smaller than that of the re-wiring structure 41, and the via hole 51 exposes a part of the surface of the re-wiring structure 41.

In one embodiment, the lead layer 60 includes a plurality of conductive pillars 61 arranged at intervals, and the conductive pillars 61 protrude from the dielectric layer 50.

In one embodiment, the through hole 51 of the dielectric layer 50 has a conductive portion 52 formed therein, the conductive portion 52 is in direct contact with the redistribution structure 41 and a conductive pillar 61, and the conductive pillar 61 is electrically connected to the redistribution structure 41 through the conductive portion 52. The material of the conductive pillar 61 and the material of the conductive portion 52 may be the same, so that the conductive pillar 61 and the conductive portion 52 may be formed in the same process step, which helps to simplify the packaging process of the semiconductor package structure.

In one embodiment, the thickness d of the lead layer 60 is greater than 30 μm. By the arrangement, the breakdown voltage of the semiconductor packaging structure can be effectively improved; in some embodiments, the conductive portion 52 is formed simultaneously with the lead layer 60, which can also prevent the conductive portion 52 from breaking at the sidewall of the through hole 51. In some embodiments, the thickness of the lead layer 60 is, for example, 31 μm, 33 μm, 35 μm, 37 μm, 40 μm, or the like.

In one embodiment, referring to fig. 11, the semiconductor package structure further includes a heat dissipation layer 80. The heat dissipation layer 80 has a larger area, so that the semiconductor package structure has a better heat dissipation effect. Each chip 20 may correspond to one heat dissipation layer 80, and the plurality of conductive pillars 61 of the chip 20 may be located around the corresponding heat dissipation layer 80.

In one embodiment, the material of heat dissipation layer 80 and the material of lead layer 60 may be the same, and thus heat dissipation layer 80 and lead layer 60 may be formed in the same process step, which helps to simplify the packaging process of the semiconductor package structure. At this time, the heat dissipation layer 80 may fully protrude from the dielectric layer 50.

In one embodiment, the semiconductor package structure further includes a solder layer 70, wherein the solder layer 70 covers the conductive posts 61 and protrudes from the surface of the dielectric layer 50.

Because the conductive posts 61 of the lead layer 60 are located on the side of the dielectric layer 50 away from the chip, and the conductive posts 61 protrude from the dielectric layer 50, that is, the conductive posts 61 all expose out of the dielectric layer 50, the climbing capability of the solder is better when forming the solder layer, the formed solder layer 70 can completely cover the surfaces of the conductive posts 61 protruding from the dielectric layer, that is, the side walls of the conductive posts 61 and the surfaces away from the chip 20 are completely covered by the solder layer 70. Thus, as shown in fig. 13, when the semiconductor package structure is soldered to the circuit board 90, the sidewall of the conductive post 61 and the solder layer 70 away from the surface of the chip 20 can be soldered to the circuit board, and compared to the scheme that the conductive post only faces away from the surface of the chip to expose the dielectric layer and the conductive post only faces away from the surface of the chip to form a solder layer, the reliability of soldering the conductive post 61 to the circuit board of the semiconductor package structure provided by the embodiment of the present invention is higher.

In one embodiment, since the heat dissipation layer 80 is located on the side of the dielectric layer 50 away from the chip, that is, the heat dissipation layer 80 is completely exposed from the dielectric layer 50, the solder layer 70 covers the surface of the portion of the heat dissipation layer 80 protruding from the dielectric layer when the solder layer is formed. When the semiconductor package structure is soldered to the circuit board, the sidewall of the heat dissipation layer 80 and the solder layer 70 facing away from the surface of the chip 20 can be soldered to the circuit board, and the solder layer is only formed on the surface of the heat dissipation layer facing away from the chip, compared with the scheme that the heat dissipation layer is only away from the surface of the chip to expose the dielectric layer, the reliability of soldering the heat dissipation layer to the circuit board of the semiconductor package structure provided by the embodiment of the present application is higher.

In one embodiment, referring to fig. 14, the size of the via hole 51 is larger, and a recess is formed at a position of the conductive portion 52 corresponding to the via hole 51 of the dielectric layer 50; the solder layer 70 fills the recess. Therefore, the contact area between the solder layer 70 and the conductive convex column 61 of the pin layer 60 is larger, the bonding force is better, and meanwhile, the solder layer 70 can be made thicker, which is beneficial to improving the reliability of the welding between the semiconductor packaging structure and the circuit board.

In some embodiments, the ratio of the width to the depth of the via 51 is greater than or equal to 1/3. Thus, the conductive part 52 is more easily recessed in the through hole 51, which is more helpful to increase the contact area between the conductive pillar 61 and the solder layer 70. The ratio of the width to the depth of the through-hole 51 is, for example, 1/3, 1/2, 2/3, 3/4, 3/2, and the like.

In one embodiment, the depth H of the through hole 51 ranges from 60 μm to 100 μm, and the dimension S of the portion of the conductive portion 52 located at the bottom wall of the through hole 51 ranges from 10 μm to 50 μm. By such an arrangement, it is further helpful to provide sufficient filling space for the solder layer 70 in the through hole 51, so as to improve the reliability of the soldering between the semiconductor package structure and other structures. In some embodiments, the depth H (hereinafter referred to as depth H) of the through hole 51 is 100 μm, the thickness S (hereinafter referred to as thickness S) of the conductive portion 52 at the bottom wall of the through hole 51 is 40 μm, and the width D (hereinafter referred to as width D) of the through hole 51 is 50 μm; alternatively, the depth H is 80 μm, the thickness S is 35 μm, and the width D is 40 μm or 80 μm; alternatively, the depth H is 60 μm, the thickness S is 25 μm, and the width D is 30 μm or 80 μm, etc. The semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application belong to the same inventive concept, and the description of relevant details and beneficial effects can be mutually referred to and are not repeated.

It should be noted that the drawings provided in the embodiments of the present application are only schematic and may have some differences from the actual structure, for example, the bonding pads on the front surface of the chip are not illustrated in the drawings, and the bonding pads on the front surface of the chip are electrically connected to the redistribution structure in practice.

It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A semiconductor package structure, comprising:

2. The semiconductor package structure of claim 1, wherein the lead layer comprises a plurality of spaced apart conductive posts protruding from the dielectric layer; the semiconductor packaging structure further comprises a solder layer, and the solder layer coats the conductive convex columns and protrudes out of the surface of the dielectric layer.

3. The semiconductor package structure of claim 1, wherein the lead layer comprises a plurality of spaced apart conductive posts protruding from the dielectric layer; a conductive part is arranged in the through hole, the pin layer is electrically connected with the rewiring layer through the conductive part, and a depression is formed at the position of the conductive part corresponding to the through hole; the semiconductor packaging structure further comprises a solder layer, the solder layer coats the conductive convex columns and protrudes out of the surface of the dielectric layer, and the solder layer fills the depressions.

4. The semiconductor package structure of claim 3, wherein a ratio of a width to a depth of the via is greater than or equal to 1/3.

5. The semiconductor package structure of claim 4, wherein the depth of the via is in a range from 60 μm to 100 μm; the thickness range of the part of the conductive part, which is positioned on the bottom wall of the through hole, is 10-50 mu m.

6. The semiconductor package structure of claim 1, wherein the lead layer has a thickness greater than 30 μ ι η.

7. The semiconductor package structure of claim 1, wherein the redistribution layer comprises a plurality of spaced redistribution structures, and the redistribution structures are provided with voids.

8. The semiconductor package structure according to claim 1, wherein a protection layer is further disposed on the front surface of the chip, and an opening for exposing the pad is disposed on the protection layer;

9. The semiconductor package structure of claim 1, further comprising a heat dissipation layer on a side of the dielectric layer facing away from the chip;

10. The semiconductor package structure according to claim 1, wherein a conductive portion is provided in the through hole, the lead layer is electrically connected to the redistribution layer through the conductive portion, and a material of the conductive portion is the same as a material of the lead layer.