CN113611603A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN113611603A CN113611603A CN202110864811.6A CN202110864811A CN113611603A CN 113611603 A CN113611603 A CN 113611603A CN 202110864811 A CN202110864811 A CN 202110864811A CN 113611603 A CN113611603 A CN 113611603A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Abstract
The present application provides a method of fabricating a semiconductor structure. The manufacturing method of the semiconductor structure comprises the following steps: providing a semiconductor intermediate structure, wherein the semiconductor intermediate structure comprises a chip, the chip is provided with a front surface, and the front surface of the chip is provided with a plurality of welding pads; forming an auxiliary layer on the front surface of the chip, wherein the auxiliary layer comprises a plurality of auxiliary structures, and each auxiliary structure covers one welding pad; forming an insulating layer in a region, which is not covered by the auxiliary structure, of the front surface of the chip, wherein the material of the insulating layer is different from that of the auxiliary layer; and etching the auxiliary layer by using etching liquid to expose the welding pad.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure.
Background
The conventional method for manufacturing a semiconductor structure mainly comprises the following processes: firstly, forming an insulating protection layer on the front surface of a chip, and then forming an opening on the insulating protection layer, wherein the opening exposes a welding pad of the chip; and then forming a rewiring layer electrically connected with the bonding pad.
In the prior art, an opening is formed in an insulating layer by laser drilling. However, the energy of laser in the laser drilling process can cause the pad of the chip to be damaged, which affects the yield and reliability of the product.
Disclosure of Invention
The embodiment of the application provides a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure comprises the following steps:
providing a semiconductor intermediate structure, wherein the semiconductor intermediate structure comprises a chip, the chip is provided with a front surface, and the front surface of the chip is provided with a plurality of welding pads;
forming an auxiliary layer on the front surface of the chip, wherein the auxiliary layer comprises a plurality of auxiliary structures, and each auxiliary structure covers one welding pad;
forming an insulating layer in a region, which is not covered by the auxiliary structure, of the front surface of the chip, wherein the material of the insulating layer is different from that of the auxiliary layer;
and etching the auxiliary layer by using etching liquid to expose the welding pad.
In one embodiment, the material of the auxiliary layer is a polymer resin, and the material of the insulating layer includes at least one of an epoxy resin and an inorganic insulating material; the etching liquid comprises an alkaline solution.
In one embodiment, the insulating layer covers sidewalls of the auxiliary structure; the forming an insulating layer in a region of the front surface of the chip not covered by the auxiliary structure includes:
arranging an insulating material layer on the front surface of the chip, wherein the insulating material layer covers the exposed area of the chip and the auxiliary structure;
and thinning the insulating material layer to expose the surface of the auxiliary structure deviating from the chip to obtain the insulating layer.
In one embodiment, the insulating material layer is prefabricated, and the disposing of the insulating material layer on the front surface of the chip includes:
the insulating-material layer, which is prefabricated, is laminated on the front side of the chip, and covers the auxiliary structure.
In one embodiment, the forming of the auxiliary layer on the front surface of the chip includes:
arranging a photosensitive material layer on the front surface of the chip;
and exposing and developing the photosensitive material layer to obtain the plurality of auxiliary structures.
In one embodiment, the providing a semiconductor intermediate structure comprises:
providing a carrier plate and a chip, and mounting the chip on the carrier plate, wherein the front surface of the chip faces the carrier plate;
forming a plastic packaging layer, wherein the plastic packaging layer at least covers the side face of the chip;
and stripping the carrier plate to obtain the semiconductor intermediate structure.
In one embodiment, the semiconductor intermediate structure comprises a plurality of the chips; the providing a semiconductor intermediate structure, comprising:
a wafer structure is provided, the wafer structure including a plurality of the connected chips.
In one embodiment, the insulating layer is provided with a plurality of through holes, and the auxiliary structure is filled in the through holes before the auxiliary layer is etched by using the etching liquid; after the auxiliary layer is etched by adopting etching liquid, the through hole exposes the welding pad;
after the etching liquid is used for etching the auxiliary layer, the manufacturing method of the semiconductor structure further comprises the following steps:
and forming a rewiring structure on the insulating layer, wherein the rewiring structure is electrically connected with the welding pad through the conductive structure in the through hole.
In one embodiment, the rewiring structure includes a trace structure and a conductive post on a side of the trace structure facing away from the chip.
In one embodiment, after the forming of the rewiring structure on the insulating layer, the method for manufacturing the semiconductor structure further includes:
and forming a dielectric layer, wherein the dielectric layer covers the rewiring structure, and the surface of the rewiring structure, which deviates from the chip, exposes the dielectric layer.
The embodiment of the application achieves the main technical effects that:
according to the manufacturing method of the semiconductor structure, the auxiliary layer comprising the auxiliary structures is formed on the front surface of the chip, each auxiliary structure covers one welding pad, the insulating layer is formed in the area, which is not covered by the auxiliary structures, of the front surface of the chip, and after the auxiliary layer is etched by the etching liquid, the through holes in the positions, corresponding to the welding pads, of the insulating layer expose the welding pads. That is, according to the manufacturing method of the semiconductor structure provided by the embodiment of the application, the through hole exposing the bonding pad can be formed on the insulating layer without etching the insulating layer, and compared with a scheme of forming the through hole on the insulating layer by adopting a laser hole forming process, damage of laser to the bonding pad can be avoided, and the yield and the reliability of products are improved. Because the material of the insulating layer is different from that of the auxiliary layer, the insulating layer cannot be etched when the auxiliary layer is etched by adopting etching liquid, the insulating layer between different welding pads of the chip is etched when the auxiliary layer is etched, the problem that short circuits occur to leads corresponding to different welding pads when leads are formed on the front surface of the chip in the follow-up process is solved, and the yield of products is improved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided by an exemplary embodiment of the present application;
FIG. 2 is a flow chart of forming a semiconductor intermediate structure provided by an exemplary embodiment of the present application;
FIG. 3 is a partial cross-sectional view of a first intermediate structure of a semiconductor structure provided in an exemplary embodiment of the present application;
FIG. 4 is a partial cross-sectional view of a wafer provided in accordance with an exemplary embodiment of the present application;
FIG. 5 is a cross-sectional view of a chip provided by an exemplary embodiment of the present application;
FIG. 6 is a partial cross-sectional view of a second intermediate structure of the semiconductor structure provided in an exemplary embodiment of the present application;
FIG. 7 is a partial cross-sectional view of a semiconductor intermediate structure provided in an exemplary embodiment of the present application;
FIG. 8 is a partial cross-sectional view of a third intermediate structure of the semiconductor structure provided in an exemplary embodiment of the present application;
FIG. 9 is a partial cross-sectional view of a fourth intermediate structure of the semiconductor structure provided in an exemplary embodiment of the present application;
FIG. 10 is a partial cross sectional view of a fifth intermediate structure of the semiconductor structure provided in an exemplary embodiment of the present application;
FIG. 11 is a partial cross sectional view of a sixth intermediate structure of the semiconductor structure provided in an exemplary embodiment of the present application;
FIG. 12 is a schematic diagram illustrating a seventh intermediate structure of a semiconductor structure provided in an exemplary embodiment of the present application;
fig. 13 is a partial cross-sectional view of a semiconductor structure provided in an exemplary embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The embodiment of the application provides a manufacturing method of a semiconductor structure. Referring to fig. 1, the method for fabricating the semiconductor structure includes the following steps 110 to 140.
In step 110, a semiconductor intermediate structure is provided, the semiconductor intermediate structure including a chip having a front surface, the front surface of the chip being provided with a plurality of pads.
In step 120, an auxiliary layer is formed on the front surface of the chip, where the auxiliary layer includes a plurality of auxiliary structures, and each auxiliary structure covers one of the pads.
In step 130, an insulating layer is formed on the front surface of the chip in a region not covered by the auxiliary structure, wherein the material of the insulating layer is different from that of the auxiliary layer.
In step 140, the auxiliary layer is etched by using an etching solution to expose the pad.
In the method for manufacturing the semiconductor structure provided by the embodiment of the application, the auxiliary layer including the plurality of auxiliary structures is formed on the front surface of the chip, each auxiliary structure covers one welding pad, then the insulating layer is formed in the area, which is not covered by the auxiliary structures, on the front surface of the chip, the auxiliary layer is etched by using the etching solution, and the welding pads are exposed by the through holes in the positions, corresponding to the welding pads, of the insulating layer. That is, according to the manufacturing method of the semiconductor structure provided by the embodiment of the application, the through hole exposing the bonding pad can be formed on the insulating layer without etching the insulating layer, and compared with a scheme of forming the through hole on the insulating layer by adopting a laser hole forming process, damage of laser to the bonding pad can be avoided, and the yield and the reliability of products are improved. Because the material of the insulating layer is different from that of the auxiliary layer, the insulating layer cannot be etched when the auxiliary layer is etched by adopting etching liquid, the insulating layer between different welding pads of the chip is etched when the auxiliary layer is etched, the problem that short circuits occur to leads corresponding to different welding pads when leads are formed on the front surface of the chip in the follow-up process is solved, and the yield of products is improved.
The steps of the method for fabricating a semiconductor structure provided in the embodiments of the present application will be described in detail below.
In step 110, a semiconductor intermediate structure is provided, the semiconductor intermediate structure including a chip having a front surface, the front surface of the chip being provided with a plurality of pads.
In one embodiment, referring to fig. 2, the step 110 of providing the semiconductor intermediate structure may include the following steps 111 to 113.
In step 111, a carrier board and a chip are provided, and the chip is mounted on the carrier board with the front surface of the chip facing the carrier board.
By this step a first intermediate structure as shown in fig. 3 is obtained. Referring to fig. 3, the chip 10 is attached to the carrier 20 by an adhesive layer 21. The adhesive layer 21 may be made of a material that is easily peelable to allow the carrier sheet to be subsequently peeled off, for example, the adhesive layer 21 may be made of a thermal release material that can be made to lose its adhesiveness by heating.
In one embodiment, the chip may be manufactured by the following process:
first, a wafer is provided. The wafer has a specific function. Referring to fig. 4, the wafer 14 has an active surface, the active surface of the wafer 14 is provided with an insulating film 12 and a bonding pad 11, and the insulating film 12 may cover an edge of the bonding pad 11. The insulating film 12 is provided with an opening exposing the pad 11. The pads 11 are used for electrical connection with external components.
Subsequently, the wafer 14 is diced. The wafer 14 may be diced along the dashed lines shown in fig. 4. The wafer 14 may be diced by mechanical dicing or laser dicing. Optionally, before dicing the wafer 14, a grinding apparatus may be used to grind the back surface of the wafer opposite the active surface so that the thickness of the wafer 14 is a specified thickness. By this step, a chip as shown in fig. 5 can be obtained.
In one embodiment, the carrier plate 20 may be circular, rectangular, or other shape. The carrier 20 may be a small-sized wafer substrate, or may be a larger-sized carrier, such as a stainless steel substrate, a polymer substrate, etc.
In step 112, a molding compound layer is formed, and the molding compound layer covers at least the side surface of the chip.
A second intermediate structure as shown in fig. 6 may be obtained, via step 112. Referring to fig. 6, a molding compound layer 30 is formed on the chip 10 and the exposed carrier 20, completely encapsulating the chip 10 to reconstruct a flat plate structure, so that after the carrier 20 is peeled off, re-wiring and packaging can be continued on the reconstructed flat plate structure. In the embodiment shown in fig. 6, the molding compound layer 30 covers both the side and the back of the chip 10. In other embodiments, the molding layer 30 may cover only the side surfaces of the chip 10. It should be noted that, in the structures shown in fig. 6 to 13, the structure of the chip 10 that is not shown is only schematic, and a specific structure thereof is not shown, and in practice, the chip 10 includes a pad, an insulating film layer, and the like.
In one embodiment, before forming the molding layer 30, some pretreatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the chip 10 and the carrier 20, so that the connection between the molding layer 30 and the chip 10 and the carrier 20 can be more intimate and no delamination or cracking occurs.
In one embodiment, the material of the molding layer 30 may be a polymer resin, a resin composite, a polymer composite, or the like. For example, the molding layer 30 may be a resin with a filler, wherein the filler may be inorganic particles. The molding layer 30 can be formed by injection molding, compression molding, transfer molding, or the like.
In step 113, the carrier is stripped to obtain the semiconductor intermediate structure.
A semiconductor intermediate structure as shown in fig. 7 may be obtained through step 113. Referring to fig. 7, in the semiconductor intermediate structure, the front surface of the chip 10 is not covered by the molding layer 30, and the bonding pads on the front surface of the chip 10 are exposed.
In another embodiment, the semiconductor intermediate structure comprises a plurality of the chips. The providing a semiconductor intermediate structure, comprising: a wafer structure is provided, the wafer structure including a plurality of the connected chips. That is, the semiconductor intermediate structure is a wafer structure.
In the following description of steps 120 to 140, only the semiconductor intermediate structure is illustrated as the structure shown in fig. 7. When the semiconductor intermediate structure is a wafer structure, the details of steps 120 to 140 are the same as those of the semiconductor intermediate structure shown in fig. 7.
In step 120, an auxiliary layer is formed on the front surface of the chip, where the auxiliary layer includes a plurality of auxiliary structures, and each auxiliary structure covers one of the pads.
In one embodiment, the step 120 includes the following process:
first, a layer of photosensitive material is provided on the front side of the chip.
The photosensitive material layer is a film layer on the whole surface and covers the surface of the semiconductor intermediate structure on the front side of the chip.
In one embodiment, the photosensitive material layer may be a pre-fabricated film layer, and the step of disposing the photosensitive material layer on the front surface of the chip includes: and laminating the prefabricated photosensitive material layer on the surface of the front side of the chip of the second intermediate structure, so that the photosensitive material layer is fixed on the surface of the second intermediate structure. Therefore, the time for forming the photosensitive material layer can be saved, and the time required by the process can be shortened. In other embodiments, the front surface of the chip may be coated with a photosensitive material to form a photosensitive material layer.
And then, exposing and developing the photosensitive material layer to obtain a plurality of auxiliary structures.
By exposing the photosensitive material layer, a third intermediate structure as shown in fig. 8 can be obtained. Referring to fig. 8, after the exposure of the photosensitive material layer 40, the regions 42 of the photosensitive material layer 40 irradiated with the light 43 are denatured, and the regions 41 not irradiated with the light 43 are not denatured. The light ray 43 may be an ultraviolet ray. The photosensitive material layer is then developed to remove the areas 41 of the photosensitive material layer not irradiated by light, resulting in a fourth intermediate structure as shown in fig. 9. Referring to fig. 9, the auxiliary layer 44 includes a plurality of auxiliary structures 45, and the auxiliary structures 45 are regions where the photosensitive material layer is denatured. The auxiliary structures 45 may correspond to the pads one to one, and the auxiliary structures 45 cover the corresponding pads.
In some embodiments, the material of the photosensitive material layer is an organic monomer molecule used to synthesize a polymer. The organic monomer molecules undergo a polymerization reaction after being irradiated by light to produce a polymer.
In some embodiments, the material of the secondary structure is a polymeric resin, for example comprising at least one of a polyolefin, a polyamide, a polyacrylamide, polyethyleneoxy ethylcinnamate, a cyclized polyisoprene, and a polyester.
In step 130, an insulating layer is formed on the front surface of the chip in a region not covered by the auxiliary structure, wherein the material of the insulating layer is different from that of the auxiliary layer.
In one embodiment, the insulating layer covers the sidewalls of the auxiliary structure, i.e., there is little gap between the insulating layer and the auxiliary structure. The step 130 of forming an insulating layer on the front surface of the chip in the area not covered by the auxiliary structure includes the following steps:
firstly, an insulating material layer is arranged on the front surface of the chip, and the insulating material layer covers the exposed area of the chip and the auxiliary structure.
In one embodiment, the layer of insulating material is pre-fabricated. The insulating material layer is prefabricated, and the insulating material layer is arranged on the front surface of the chip, and the method comprises the following steps: the insulating-material layer, which is prefabricated, is laminated on the front side of the chip, and covers the auxiliary structure. Therefore, the time for forming the insulating material layer can be saved, and the time required by the process can be shortened. Wherein the region of the insulating-material layer covering the auxiliary structure is lifted by said auxiliary structure so that this part of the insulating-material layer protrudes with respect to the other regions of the insulating-material layer.
In other embodiments, the front surface of the chip may be coated with an insulating material to form an insulating material layer.
And then, thinning the insulating material layer to expose the surface of the auxiliary structure deviating from the chip to obtain the insulating layer.
In one embodiment, the layer of insulating material may be thinned using a grinding process. The thickness of the insulating material layer can be larger than that of the auxiliary structure, and a through hole is formed in the area, opposite to the auxiliary structure, of the thinned insulating material layer, namely the insulating layer is provided with the through hole, and the auxiliary structure is located in the through hole. The thickness of the insulating layer and the thickness of the auxiliary structure may be substantially the same.
A fifth intermediate structure as shown in fig. 10 may be obtained through step 130. Referring to fig. 10, the insulating layer 60 is provided with a plurality of through holes 61, the through holes 61 may correspond to the auxiliary structures 45 one by one, and the auxiliary structures 45 are located in the corresponding through holes 61.
In one embodiment, the material of the insulating layer includes at least one of an epoxy resin and an inorganic insulating material. The inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, or the like.
By setting the material of the insulating layer to be different from that of the auxiliary layer, the etching liquid which does not react with the insulating layer is selected when the auxiliary layer is removed in the subsequent steps, so that the etching of the insulating layer by the etching liquid can be avoided.
In step 140, the auxiliary layer is etched by using an etching solution to expose the pad.
In one embodiment, the material of the auxiliary layer is a polymer resin, the material of the insulating layer includes at least one of an epoxy resin and an inorganic insulating material, and the etching solution includes an alkaline solution. For example, the material of the auxiliary layer may include at least one of polyolefin, polyamide, polyacrylamide, polyethyleneoxy ethyl cinnamate, cyclized polyisoprene, and polyester; the inorganic insulating material comprises at least one of silicon nitride, silicon oxide or silicon oxynitride; the alkaline solution is sodium hydroxide solution.
Since the material of the auxiliary layer is soluble in the alkaline solution, and the epoxy resin and the inorganic insulating material are insoluble in the alkaline solution, the auxiliary structure can be removed by using the etching solution including the alkaline solution, and the insulating layer cannot be removed.
A sixth intermediate structure as shown in fig. 11 may be obtained through step 140. Referring to fig. 11, the auxiliary structure within the via hole 61 of the insulating layer 60 is removed. After the auxiliary structure is removed, the through hole 61 exposes the pad of the chip.
In an embodiment, after the step 140 of etching the auxiliary layer with the etching solution, the method for manufacturing a semiconductor structure further includes: and forming a rewiring structure on the insulating layer, wherein the rewiring structure is electrically connected with the welding pad through the conductive structure in the through hole.
By this step a seventh intermediate structure as shown in fig. 12 is obtained. Referring to fig. 12, the rewiring structure 70 is electrically connected to the pads of the chip 10, and leads the pads of the chip out. The re-routing structure 70 is electrically connected to the pads of the chip 10 through the conductive structures 81 in the through holes 61.
In one embodiment, the redistribution structure 70 includes trace structures 71 and conductive posts 72 located on a side of the trace structures 71 facing away from the chip, and one trace structure 71 may be electrically connected to one pad, or may be electrically connected to two or more pads. One side of each trace structure 71 facing away from the chip may be provided with a conductive pillar 72, the conductive pillar 72 is in direct contact with the trace structure 71, and the conductive pillar 72 may be used to electrically connect with an external component.
In one embodiment, trace structure 71 and conductive structure 81 may be formed simultaneously in the same process step.
In some embodiments, the process of forming the trace structures and the conductive structures may be as follows:
first, a seed layer is formed on the sixth intermediate structure, where the seed layer may be a whole film layer covering the surface of the insulating layer 60 away from the chip and the through hole 61.
Subsequently, a layer of photosensitive material is formed on the side of the seed layer facing away from the chip, the layer of photosensitive material covering the seed layer.
Subsequently, the photosensitive material layer is exposed and developed, so that a plurality of hollow parts are formed on the photosensitive material layer, and each hollow part exposes at least one through hole 61.
And then, connecting the seed layer to a power supply, and electroplating to form a conductive material in the hollow part.
And etching the seed layer, and removing the area of the seed layer which is not covered by the conductive material. The conductive material and the remaining seed layer are in a conductive structure in the through hole 61, and in a trace structure in the hollow portion.
In one embodiment, after the step of forming the rewiring structure on the insulating layer, the method of manufacturing the semiconductor structure further includes:
and forming a dielectric layer, wherein the dielectric layer covers the rewiring structure, and the surface of the rewiring structure, which deviates from the chip, exposes the dielectric layer.
The semiconductor structure shown in fig. 13 can be obtained by this step. Referring to fig. 13, a dielectric layer 90 encapsulates the rewiring structure 70. The dielectric layer 90 may protect the redistribution structure 70, and the surface of the conductive pillar 72 facing away from the chip exposes the dielectric layer 90.
In one embodiment, the dielectric layer 90 is one or more layers of insulating material, and the material of the dielectric layer 90 may be PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite, or other material with similar properties. The dielectric layer 90 may be formed by lamination, spin coating, printing, molding, or other suitable means.
The distance from the side of dielectric layer 90 facing away from insulating layer 60 to insulating layer 60 is substantially the same as the distance from the side of conductive posts 72 facing away from insulating layer 60 to insulating layer 60, such that the surface of conductive posts 72 has just exposed dielectric layer 90. In forming the dielectric layer 90, the initially formed dielectric layer 90 may cover the surface and the side portions of the conductive pillars 72, and then the dielectric layer 90 is thinned to expose the surface of the conductive pillars 72 away from the insulating layer 60.
In an embodiment of the present application, when the semiconductor intermediate structure is a wafer structure, before the step of forming the rewiring structure on the insulating layer, the method for manufacturing the semiconductor structure further includes:
firstly, cutting the structure obtained in the step 140 to obtain a plurality of substructures, wherein each substructure comprises at least one chip;
then, a plurality of substructures are attached to the carrier plate, and the insulating layer faces the carrier plate;
subsequently, an encapsulation layer is formed, the encapsulation layer encapsulating at least the side faces of the substructure;
subsequently, the carrier sheet is peeled off.
In this embodiment, the resulting semiconductor structure is shown in fig. 13.
According to the manufacturing method of the semiconductor structure, the insulating layer is formed firstly, and then the conductive structure is formed in the through hole of the insulating layer, so that the through hole can be filled with the conductive structure, and no gap exists between the conductive structure and the side wall of the through hole; compared with the scheme that the conductive structure is formed firstly and then the insulating layer is formed, the gap between the filling particles in the insulating layer and the side wall of the conductive structure can be avoided, and the subsequent gap between the conductive structure and the insulating layer is increased under the high-temperature condition to cause the water and oxygen in the air to invade the gap to influence the reliability of the product; and the problem that the product fails because the electroplating solution enters the gap in the process of forming the rewiring structure due to the gap between the filling particles in the insulating layer and the side wall of the conductive structure can also be avoided.
In one embodiment, when the semiconductor structure includes a plurality of chips, after obtaining the semiconductor structure, the method for manufacturing the semiconductor structure further includes: and cutting the semiconductor structure to obtain a plurality of semiconductor substructures, wherein each semiconductor substructure comprises one or more chips.
It should be noted that the drawings provided in the embodiments of the present application are only schematic and may have some differences from the actual structure, for example, the bonding pads on the front surface of the chip are not illustrated in the drawings, and the bonding pads on the front surface of the chip are electrically connected to the redistribution structure in practice.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor intermediate structure, wherein the semiconductor intermediate structure comprises a chip, the chip is provided with a front surface, and the front surface of the chip is provided with a plurality of welding pads;
forming an auxiliary layer on the front surface of the chip, wherein the auxiliary layer comprises a plurality of auxiliary structures, and each auxiliary structure covers one welding pad;
forming an insulating layer in a region, which is not covered by the auxiliary structure, of the front surface of the chip, wherein the material of the insulating layer is different from that of the auxiliary layer;
and etching the auxiliary layer by using etching liquid to expose the welding pad.
2. The method of claim 1, wherein the auxiliary layer is made of a polymer resin, and the insulating layer is made of at least one of an epoxy resin and an inorganic insulating material; the etching liquid comprises an alkaline solution.
3. The method of claim 1, wherein the insulating layer covers sidewalls of the auxiliary structure; the forming an insulating layer in a region of the front surface of the chip not covered by the auxiliary structure includes:
arranging an insulating material layer on the front surface of the chip, wherein the insulating material layer covers the exposed area of the chip and the auxiliary structure;
and thinning the insulating material layer to expose the surface of the auxiliary structure deviating from the chip to obtain the insulating layer.
4. A method for fabricating a semiconductor structure according to claim 3, wherein the insulating material layer is pre-fabricated, and the providing of the insulating material layer on the front side of the die comprises:
the insulating-material layer, which is prefabricated, is laminated on the front side of the chip, and covers the auxiliary structure.
5. The method of claim 1, wherein the forming an auxiliary layer on the front side of the chip comprises:
arranging a photosensitive material layer on the front surface of the chip;
and exposing and developing the photosensitive material layer to obtain the plurality of auxiliary structures.
6. The method of claim 1, wherein said providing a semiconductor intermediate structure comprises:
providing a carrier plate and a chip, and mounting the chip on the carrier plate, wherein the front surface of the chip faces the carrier plate;
forming a plastic packaging layer, wherein the plastic packaging layer at least covers the side face of the chip;
and stripping the carrier plate to obtain the semiconductor intermediate structure.
7. The method of claim 1, wherein the semiconductor intermediate structure comprises a plurality of the chips; the providing a semiconductor intermediate structure, comprising:
a wafer structure is provided, the wafer structure including a plurality of the connected chips.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein the insulating layer is provided with a plurality of through holes, and the auxiliary structure is filled in the through holes before the etching of the auxiliary layer by using the etching liquid; after the auxiliary layer is etched by adopting etching liquid, the through hole exposes the welding pad;
after the etching liquid is used for etching the auxiliary layer, the manufacturing method of the semiconductor structure further comprises the following steps:
and forming a rewiring structure on the insulating layer, wherein the rewiring structure is electrically connected with the welding pad through the conductive structure in the through hole.
9. The method of claim 8, wherein the redistribution structure comprises a trace structure and a conductive post on a side of the trace structure facing away from the die.
10. The method of claim 8, wherein after forming a rewiring structure on the insulating layer, the method further comprises:
and forming a dielectric layer, wherein the dielectric layer covers the rewiring structure, and the surface of the rewiring structure, which deviates from the chip, exposes the dielectric layer.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1344018A (en) * | 2000-09-20 | 2002-04-10 | 陈怡铭 | Packaging method of semiconductor chip and its package |
| US20080214008A1 (en) * | 2006-12-22 | 2008-09-04 | Nec Electronics Corporation | Method of manufacturing semiconductor device |
| CN109712953A (en) * | 2017-10-25 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
| CN111540686A (en) * | 2020-03-23 | 2020-08-14 | 江苏长电科技股份有限公司 | Packaging process for laser post-planting balls |
| CN111599702A (en) * | 2019-04-24 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Manufacturing method of fan-out type chip packaging structure |
| CN111755340A (en) * | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
-
2021
- 2021-07-29 CN CN202110864811.6A patent/CN113611603A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1344018A (en) * | 2000-09-20 | 2002-04-10 | 陈怡铭 | Packaging method of semiconductor chip and its package |
| US20080214008A1 (en) * | 2006-12-22 | 2008-09-04 | Nec Electronics Corporation | Method of manufacturing semiconductor device |
| CN109712953A (en) * | 2017-10-25 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
| CN111599702A (en) * | 2019-04-24 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Manufacturing method of fan-out type chip packaging structure |
| CN111540686A (en) * | 2020-03-23 | 2020-08-14 | 江苏长电科技股份有限公司 | Packaging process for laser post-planting balls |
| CN111755340A (en) * | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
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