CN111668114A - Semiconductor packaging method - Google Patents
Semiconductor packaging method Download PDFInfo
- Publication number
- CN111668114A CN111668114A CN201910177325.XA CN201910177325A CN111668114A CN 111668114 A CN111668114 A CN 111668114A CN 201910177325 A CN201910177325 A CN 201910177325A CN 111668114 A CN111668114 A CN 111668114A
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- packaged
- sealing layer
- semiconductor packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
The application provides a semiconductor packaging method, which comprises the following steps: mounting a chip to be packaged on a carrier plate, wherein the back surface of the chip to be packaged is upward, and the front surface of the chip to be packaged faces the carrier plate; forming a sealing layer, wherein the sealing layer covers the carrier plate and wraps the periphery of the chip to be packaged; processing the upper surface of the sealing layer to increase the roughness of the upper surface of the sealing layer; and packaging the chip to be packaged on the upper surface of the sealing layer to form an encapsulating layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method.
Background
The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: the method comprises the steps of firstly, bonding the front surface of a bare chip on a carrier plate through an adhesive tape, carrying out hot-press plastic package, then stripping the carrier plate, then carrying out rewiring process on the front surface of the bare chip to form a rewiring structure, and packaging.
In the hot-press plastic package process, in order to prevent the bare chip from displacing due to overlarge pressure in a hot-press plastic package process, and simultaneously prevent the bare chip from being broken due to overlarge pressure on the back surface of the bare chip during hot-press molding, a sealing layer can be pre-coated on the back surface of the bare chip and the surface of the bonding layer after the bare chip is arranged on the carrier plate, and then hot-press plastic package is carried out.
However, if the interfacial bonding force between the sealing layer and the molding layer is not strong enough, the stability of the whole package structure is affected.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, comprising:
mounting a chip to be packaged on a carrier plate, wherein the back surface of the chip to be packaged is upward, and the front surface of the chip to be packaged faces the carrier plate;
forming a sealing layer, wherein the sealing layer covers the carrier plate and wraps the periphery of the chip to be packaged;
processing the upper surface of the sealing layer to increase the roughness of the upper surface of the sealing layer;
and packaging the chip to be packaged on the upper surface of the sealing layer to form an encapsulating layer.
Optionally, the processing the upper surface of the sealing layer includes performing plasma processing on the upper surface of the sealing layer.
Optionally, when the upper surface of the sealing layer is plasma-treated, at least one of argon and oxygen is supplied to the plasma treatment space.
Optionally, when the upper surface of the sealing layer is subjected to plasma treatment, a mixed gas including argon and oxygen is supplied to the plasma treatment space, wherein the volume percentage of argon is 30-70%, and the volume percentage of oxygen is 30-70%.
Optionally, when the upper surface of the sealing layer is subjected to plasma treatment, the adopted working temperature is 25-50 ℃.
Optionally, when the upper surface of the sealing layer is subjected to plasma treatment, the electric power used is 200W-600W.
Optionally, the duration of the plasma treatment on the upper surface of the sealing layer is 3S to 60S.
Optionally, before the chip to be packaged is mounted on the carrier, the method further includes:
and forming a protective layer on the front surface of the chip to be packaged.
Optionally, after forming the encapsulation layer, the method comprises:
stripping the carrier plate to expose the front surface of the chip to be packaged;
and forming a rewiring structure on the front surface of the chip to be packaged, wherein the rewiring structure is used for leading out the welding pad on the front surface of the chip to be packaged.
Optionally, after the forming of the encapsulating layer and before the peeling of the carrier plate, the method comprises:
and a support layer is pasted on the first surface of the encapsulating layer far away from the carrier plate.
Optionally, after a rewiring structure is formed on the front surface of the chip to be packaged, the method includes:
and stripping the supporting layer.
According to the semiconductor packaging method provided by the embodiment of the application, the upper surface of the sealing layer is processed, so that the roughness of the upper surface of the sealing layer is increased, the contact area between the sealing layer and the encapsulating layer is increased, the bonding force between the sealing layer and the encapsulating layer is increased, the stability of a packaging structure is ensured, and the packaging success rate and the product yield are ensured.
Drawings
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Fig. 2(a) -2 (l) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a front structure of a carrier according to an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a semiconductor package structure obtained by using the semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
According to various embodiments of the present disclosure, a semiconductor packaging method is provided. In the packaging process, a chip to be packaged is attached to a carrier plate, the back surface of the chip to be packaged is upward, and the front surface of the chip to be packaged faces the carrier plate; forming a sealing layer, wherein the sealing layer covers the carrier plate and wraps the periphery of the chip to be packaged; processing the upper surface of the sealing layer to increase the roughness of the upper surface of the sealing layer; and packaging the chip to be packaged on the upper surface of the sealing layer to form an encapsulating layer. According to the above embodiment of the disclosure, the upper surface of the sealing layer is processed, so that the roughness of the upper surface of the sealing layer is increased, the contact area between the sealing layer and the encapsulating layer is increased, the bonding force between the sealing layer and the encapsulating layer is increased, the stability of the packaging structure is ensured, and the packaging success rate and the product yield are ensured.
As shown in fig. 1, 2(a) -2 (l), 3 and 4, the present disclosure provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 101: mounting a chip to be packaged on a carrier plate, wherein the back surface of the chip to be packaged is upward, and the front surface of the chip to be packaged faces the carrier plate;
step 102: forming a sealing layer, wherein the sealing layer covers the carrier plate and wraps the periphery of the chip to be packaged;
step 103: processing the upper surface of the sealing layer to increase the roughness of the upper surface of the sealing layer;
step 104: and packaging the chip to be packaged on the upper surface of the sealing layer to form an encapsulating layer.
In this embodiment, before step 101, that is, before the chip to be packaged is mounted on the carrier, a protection layer may be formed on the front surface of the chip to be packaged. The protective layer may be formed on the front surface of the semiconductor wafer before the semiconductor wafer is cut into a plurality of chips to be packaged, and then the semiconductor wafer is cut to obtain the chips to be packaged with the protective layer formed on the front surface. It is understood that, when the process allows, the protective layer may be formed on the front surface of each chip to be packaged after the semiconductor wafer is cut into the chips to be packaged, which is selected according to the actual situation.
As shown in fig. 2(a), a protection layer 202 is formed on the front surface of the semiconductor wafer 100, i.e. the surface corresponding to the front surface of the to-be-packaged chip 201, and then the semiconductor wafer 100 on which the protection layer 202 is formed is cut along the cutting streets to obtain a plurality of to-be-packaged chips 201 on which the protection layer is formed.
The protection layer 202 is made of an insulating material, such as polyimide, epoxy resin, abf (ajinomoto build film), pbo (polybenzoxazole), and the like. Alternatively, the material of the protective layer is selected to be insulating and capable of accommodating chemical cleaning, polishing, and the like. The protective layer may be formed on the semiconductor wafer by Lamination (Coating), Coating (Coating), Printing (Printing), and the like.
In step 101, a chip 201 to be packaged is attached to a carrier 200 through an adhesive layer 203. As shown in fig. 2(b), an adhesive layer 203 is disposed on the carrier 200 for adhering the chip 201 to be packaged. And the adhesive layer 203 may be made of a material that is easily peeled off so as to peel off the carrier board 200 and the chip 201 to be packaged that is packaged on the back side, for example, a thermal release material that can be heated to lose its adhesiveness.
In other embodiments, the adhesive layer 203 may have a two-layer structure, i.e., a thermal separation material layer and a die attach layer, the thermal separation material layer is attached to the carrier 200 and loses its viscosity when heated, so as to be peeled off from the carrier 200, and the die attach layer has an adhesive material layer and can be used to attach the die 201 to be packaged. After the packaged chip 201 is peeled off from the carrier 200, the chip adhesion layer thereon may be removed by chemical cleaning. In one embodiment, the adhesive layer 203 may be formed on the carrier 200 by lamination, printing, or the like.
As shown in fig. 2(c), a chip 201 to be packaged (a plurality of chips to be packaged are shown in the figure) with a protection layer 202 formed on the front surface is attached to a carrier 200.
In one embodiment, as shown in fig. 3, a bonding position of the chip 201 to be packaged is preset on the carrier 200, and after the adhesive layer 203 is formed, the front surface of the chip 201 to be packaged is bonded at a predetermined position a of the carrier 200 toward the carrier 200. In an embodiment, before the adhesive layer 203 is formed, a bonding position of the chip to be packaged may be identified in advance on the carrier 200 by using laser, mechanical patterning, photolithography, and the like, and the chip 201 to be packaged is also provided with an alignment mark to align with the bonding position on the carrier 200 during bonding. It should be noted that the protective layer may be transparent under certain light so as to be able to see the alignment mark disposed on the chip 201 to be packaged, and to be able to accurately attach the chip 201 to be packaged at the predetermined position a. It can be understood that, in one packaging process, a plurality of chips 201 to be packaged may be provided, that is, a plurality of chips 201 to be packaged are simultaneously mounted on the carrier 200, packaged, and cut into a plurality of packages after the packaging is completed; one package body may include one or more chips to be packaged, and the positions of the chips to be packaged may be freely set according to the needs of an actual product.
In step 102, as shown in fig. 2(d), the sealing layer 300 is covered on the carrier board 200, i.e. the sealing layer 205 is formed on the back surface of the chip 201 to be packaged and the exposed adhesive layer 203, so as to wrap the chip 201 to be packaged. That is, the lower surface 3001 of the sealing layer 300 is connected with the chip 201 to be packaged and the exposed adhesive layer 203.
In an embodiment, the sealing layer 300 may be made of a polymer insulating material liquid or paste, and may be formed by Spraying (Spraying), Printing (Printing), Coating (Coating), and the like, and the thickness of the sealing layer 300 is smaller than that of the chip 201 to be packaged.
In the actual operation process, the polymer insulating material is preferably liquid or paste, so that after the spraying is completed, the polymer insulating material flows to the periphery of the chip 201 to be packaged, covers any gap, achieves uniform thickness, and can enable the sealing layer 300 to wrap the chip 201 to be packaged after the curing in a curing manner, so as to lock the position of the chip 201 to be packaged to be fixed. The sealing layer material is cured by high temperature or ultraviolet ray. The shape of the sealant 300 is largely determined by the adhesive, tensile, etc. properties of the sealant material.
In the above embodiment of the present disclosure, the sealing layer 300 wraps the periphery of the chip 201 to be packaged, so that after the chip 201 to be packaged is displaced in the subsequent process, a situation that the redistribution layer and the pad on the front side of the chip 201 to be packaged cannot be electrically connected due to the fact that the position of the displaced chip 201 to be packaged cannot be estimated can be avoided.
In step 103, the upper surface 3002 of the sealing layer 300 is treated to increase the roughness of the upper surface 3002 of the sealing layer 300. As shown in fig. 2(e), the arrows in the figure indicate the direction of processing.
In some embodiments, treating the upper surface 3002 of the sealing layer 300 includes plasma treating the upper surface 3002 of the sealing layer 300 to increase the roughness of the upper surface 3002 of the sealing layer 300.
The mode of treating the upper surface of the sealing layer by the plasma has the characteristics of convenient and flexible use, simple process and completely controllable process conditions, and has the advantages of low cost, good effect, short time and high efficiency; because the plasma treatment adopts gas treatment, the uniformity of the upper surface of the treated sealing layer is good, and even the surface of a complex carrier plate on which a plurality of chips to be packaged are mounted can be treated with obvious effect in a targeted manner; meanwhile, as the plasma treatment adopts gas treatment, no harmful pollutants are generated, and the method belongs to a green treatment mode which is beneficial to environmental protection.
Specifically, the inventors (or the inventors) have found, through a large number of experiments, that in some embodiments, at least one of argon gas and oxygen gas, that is, only argon gas or only oxygen gas may be supplied as a process gas, or a mixed gas including argon gas and oxygen gas may be supplied as a process gas, is supplied to the plasma processing space when the plasma processing is performed on the upper surface of the sealing layer. Further, when a mixed gas comprising argon and oxygen is supplied to the plasma processing space as a processing gas, the volume percentage of the argon in the mixed gas is 30-70%, and the volume percentage of the oxygen in the mixed gas is 30-70%, the mixed gas can shorten the plasma processing time, thereby improving the production efficiency; meanwhile, the effect of enhancing the interface bonding force of the sealing layer and the encapsulating layer is achieved.
When the upper surface of the sealing layer is subjected to plasma treatment, the adopted working temperature is 25-50 ℃. When the upper surface of the sealing layer is subjected to plasma treatment, the electric power is 200W-600W, such as 280W, 300W, 320W and the like. And when the upper surface of the sealing layer is subjected to plasma treatment, the time length of the plasma treatment on the upper surface of the sealing layer is 3S-60S.
The upper surface of the sealing layer is subjected to plasma treatment by adopting the process conditions, and the roughness of the upper surface of the obtained sealing layer can well ensure the contact area between the upper surface of the sealing layer and other structures, so that the adhesive force between the upper surface of the sealing layer and other structures is increased, the packaging quality is ensured, and the stability of a packaged product in the using process is also favorably ensured. In addition, the upper surface of the sealing layer is subjected to plasma treatment, and impurities on the surface of the sealing layer can be removed, so that the sealing layer and other structures cannot be influenced by the impurities and can be bonded more closely.
In step 104, an encapsulating layer 204 is covered on the upper surface 3001 of the sealing layer 300 and formed on the back surface of the chip 201 to be packaged. As shown in fig. 2(f), the encapsulating layer 204 is used to completely encapsulate the carrier 200 and the chip 201 to be packaged, so as to reconstruct a flat plate structure, so that after the carrier 200 is peeled off, the re-wiring and packaging can be continued on the reconstructed flat plate structure.
As described above, since the upper surface of the sealing layer is subjected to plasma treatment, the roughness of the upper surface of the obtained sealing layer can well ensure the contact area between the upper surface of the sealing layer and the encapsulating layer, so that the adhesive force between the upper surface of the sealing layer and the encapsulating layer is increased, the packaging quality is ensured, and the stability of the packaged product in the using process is also ensured. In addition, the upper surface of the sealing layer is subjected to plasma treatment, and impurities on the surface of the sealing layer can be removed, so that the sealing layer and the encapsulating layer are not influenced by the impurities and can be bonded more closely.
In one embodiment, the encapsulating layer 204 may be formed by laminating an epoxy resin film or abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound.
The encapsulating layer 204 includes a first surface 2041 opposite to the carrier 200, and is substantially flat and parallel to the surface of the carrier 200. The thickness of the encapsulating layer 204 may be reduced by grinding or polishing the first surface 2041, and in an alternative embodiment, the thickness of the encapsulating layer 204 may be reduced to the back side of the chip 201 to be packaged.
When the encapsulating layer 204 is used for encapsulating, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material is easy to penetrate between the carrier 200 and the chip 201 to be encapsulated in the process. Through the embodiment of the disclosure, the protective layer 202 is formed outside the chip 201 to be packaged, the protective layer 202 can prevent the encapsulating material from penetrating into the surface of the chip 201 to be packaged, and even if the encapsulating material penetrates into the surface, the surface of the protective layer 202 can be directly processed through a chemical mode or a grinding mode after being peeled off from the carrier plate, so that the surface can not directly contact with the front surface of the chip 201 to be packaged, and further the circuit structure on the front surface of the chip 201 to be packaged can not be damaged.
Further, optionally, after step 104, the packaging method further includes attaching a support layer 205 on the first surface of the encapsulation layer away from the carrier.
The support layer is attached to at least a portion of the first surface of the envelope layer. As shown in fig. 2(g), in one embodiment, the support layer 205 is attached on the first surface 2041 of the encapsulating layer 204, and the support layer 205 is shown covering the entire area of the first surface 2041 of the encapsulating layer 204.
The material strength of the supporting layer is greater than that of the encapsulating layer, so that the supporting layer can effectively improve and ensure the mechanical strength of the encapsulating structure in the encapsulating process, and effectively inhibit the adverse effect caused by the deformation of each structure, thereby improving the product encapsulating effect. In other embodiments, the supporting layer may also be formed on the first surface 2041 of the encapsulating layer 204 by Spraying (Spraying), Printing (Printing), Coating (Coating), or the like.
Further, in an embodiment, as shown in fig. 2(h), after the supporting layer 205 is attached, the encapsulating method further includes peeling off the carrier 200, and after the carrier 200 is peeled off, the exposed surfaces are the protective layer 202 on the front surface of the chip 201 to be encapsulated and the lower surface 3001 of the sealing layer 300.
In an embodiment, as shown in fig. 2(h), since the adhesive layer 203 is disposed between the carrier 200 and the protective layer 202 and between the carrier 200 and the sealing layer 300, the adhesive layer 203 can be reduced in viscosity after being heated by heating, so as to peel off the carrier 200. By peeling the carrier board 200 by heating the adhesive layer 203, damage to the chip 201 to be packaged during the peeling process can be minimized.
After the carrier 200 is peeled off, the lower surface 3001 of the sealing layer 300 facing the carrier 200 and the protective layer 202 are exposed. After the carrier 200 is peeled off, a flat plate structure including the chip 201 to be packaged, the protection layer 202 covering the front surface of the chip 201 to be packaged, the sealing layer 300 encapsulating the back surface of the chip 201 to be packaged, and the encapsulating layer 204 is obtained. The flat plate structure thus formed may be subjected to rewiring or the like according to the actual situation. In other embodiments, the carrier board 200 can be peeled off directly and mechanically.
In the embodiment of the disclosure, after the carrier 200 is peeled off, the surfaces of the protective layer 202 and the sealing layer 300 are exposed, at this time, the chip adhesion layer in the adhesive layer 202 is also present on the surfaces of the protective layer 202 and the sealing layer 300, and when the chip adhesion layer is removed by a chemical method, the protective layer 202 can also protect the surface of the chip to be packaged from being damaged; after the adhesive layer is completely removed, if the encapsulating material permeates in the adhesive layer, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; if the protective layer is not provided, the surface of the chip to be packaged cannot be processed in a chemical mode or a grinding mode so as to avoid damaging a circuit on the front surface of the chip to be packaged.
It should be noted that, for the embodiment without the supporting layer, after step S104, the carrier may be peeled off to expose the protective layer and the sealing layer. The specific stripping method can be referred to the above description, and is not repeated herein.
Next, as shown in fig. 2(i), a passivation opening 2021 is formed on the passivation layer at a position corresponding to the pads of the to-be-packaged chip, where each passivation opening 2021 is at least correspondingly located on a pad of the to-be-packaged chip 201 or a line led out from the pad, so that the pad on the front surface of the to-be-packaged chip 201 or the line led out from the pad is exposed from the passivation opening 2021. If the material of the protective layer is a laser-reactive material, the protective layer can be opened by forming one protective layer opening 2021 at a time by laser patterning; if the passivation layer is made of a photosensitive material, a plurality of passivation openings 2021 may be formed at a time by photolithography and patterning. The shape of the passivation opening 2021 may be round, but may also be other shapes such as oval, square, linear, etc.
Further, in some embodiments, a rewiring is performed on the protection layer 202 of the chip 201 to be packaged, i.e., a rewiring structure is formed. The front surface of the chip 201 to be packaged is provided with bonding pads of a circuit inside the chip, and the bonding pads can be led out by re-wiring on the front surface of the chip 201 to be packaged. As shown in fig. 2(j), the rewiring structure includes: a first redistribution layer 206 formed on the passivation layer 202 and the exposed encapsulation layer 204 and electrically connected to the pads of the chip 201 through the passivation opening 2021; and a front-side first encapsulation layer 207 formed on the first redistribution layer 206 and the exposed passivation layer 202 and the exposed encapsulation layer 204 and having a first opening, wherein a first conductive pillar 208 electrically connected to the first redistribution layer 206 is disposed in the first opening of the front-side first encapsulation layer 207. The first conductive pillar 208 is preferably circular, but may be rectangular, square, or other shapes, and the conductive pillar 208 is electrically connected to the first redistribution layer 206.
Further, in an alternative embodiment, when forming the rewiring structure, if the surface is completely made of the same material, a passivation layer may be formed on the protection layer 202, and particularly, a passivation layer opening corresponding to the protection layer opening 2021 may be formed on the passivation layer for rewiring.
In an embodiment, since the passivation layer opening is already formed on the passivation layer 202, at least the passivation layer opening can be directly seen when the first redistribution layer 206 is formed, so that the first redistribution layer 206 can be aligned more accurately when formed.
In another embodiment, the sealant material may be selected to match the protection layer, i.e. the expansion coefficient, elastic modulus, etc. of the protection layer material and the sealant material are relatively similar, so that after the first wiring layer 206 is formed on the two materials, the rewiring will not be affected by the difference of the material characteristics. Alternatively, the same material may be used for the protective layer material and the sealing layer material. In addition, in the above-described embodiment, the dependence on the passivation layer can be reduced by forming the sealing layer 300 and the protective layer 202.
Further, after forming the re-wiring structure, the packaging method further includes peeling off the support layer 205. As shown in fig. 2 (k). The supporting layer 205 can be peeled off directly mechanically, or by other methods, which is not limited in this application and can be set according to the specific application environment.
In an embodiment, in the case that a plurality of chips 201 to be packaged are packaged together, after the package of the rewiring structure is completed, the whole package structure is cut into a plurality of packages by laser or mechanical cutting, as shown in fig. 2(l), and the structure diagram of the formed package is shown in fig. 4.
Further, in an embodiment, the re-wiring may be repeated on the front side of the chip 201, for example, a second re-wiring layer or more re-wiring layers may be formed outside the front side encapsulation layer in the same manner to achieve multi-layer re-wiring of the product.
It should be noted that, in another embodiment, the protective layer opening 2021 is formed at a position on the protective layer corresponding to the pads of the to-be-packaged chips, and the pads on the front surface of the to-be-packaged chip 201 or the lines led out from the pads may be exposed from the protective layer opening 2021 before the wafer on which the protective layer is formed is cut into the to-be-packaged chips. The specific scheme for forming the opening of the passivation layer can be referred to the above description, and is not repeated herein.
After the chip to be packaged formed with the protective layer 202 is adhered to the adhesive layer 203 of the carrier 200, the plurality of protective layer openings 2021 are in a hollow state.
In another embodiment, after forming the passivation layer opening 2021 on the passivation layer at a position corresponding to the pads of the plurality of chips to be packaged, the method further includes: and filling a conductive medium in the opening of the protective layer, so that the conductive medium is electrically connected with the welding pad of the chip to be packaged. The conductive medium forms a vertical connecting structure in the opening of the protective layer, so that the welding pad on the surface of the chip is extended to the surface of the protective layer, and the protective layer can surround and form the periphery of the connecting structure.
Fig. 4 is a schematic structural diagram of a chip package structure obtained by using the semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 4, the semiconductor package structure includes:
the encapsulating layer 204 is provided with an inwards concave cavity;
the chip 201 is arranged in the cavity, and the back surface of the chip 201 faces to the bottom of the cavity;
a sealing layer 300 formed on the back surface of the chip 201 and between the encapsulating layer 204 and the rewiring structure;
the passivation layer 202 is formed on the front surface of the chip 201, and a passivation layer opening 2021 is formed on the passivation layer 202, where the passivation layer opening 2021 is located at a position corresponding to the pad on the front surface of the chip 201;
and the rewiring structure is formed on the front surface of the chip 201 and is used for leading out the bonding pad on the front surface of the chip 201.
In some embodiments, the rewiring structure includes: a first redistribution layer 206 formed on the passivation layer 202 and the exposed encapsulation layer 204 and electrically connected to the pads of the chip 201 through the passivation opening 2021; and a front side first encapsulation layer 207 formed on the first redistribution layer 206 and the exposed passivation layer 202 and the exposed encapsulation layer 204 and having a first opening 2071, wherein a first conductive pillar 208 electrically connected to the first redistribution layer 206 is disposed in the first opening 2071 of the front side first encapsulation layer 207.
In another embodiment, the re-routing structure includes more re-routing layers to achieve multi-level re-routing of the product.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (11)
1. A semiconductor packaging method, comprising:
mounting a chip to be packaged on a carrier plate, wherein the back surface of the chip to be packaged is upward, and the front surface of the chip to be packaged faces the carrier plate;
forming a sealing layer, wherein the sealing layer covers the carrier plate and wraps the periphery of the chip to be packaged;
processing the upper surface of the sealing layer to increase the roughness of the upper surface of the sealing layer;
and packaging the chip to be packaged on the upper surface of the sealing layer to form an encapsulating layer.
2. The semiconductor packaging method of claim 1, wherein treating the upper surface of the sealing layer comprises plasma treating the upper surface of the sealing layer.
3. The semiconductor packaging method according to claim 2, wherein at least one of argon gas and oxygen gas is supplied to the plasma processing space when the upper surface of the sealing layer is plasma-processed.
4. The semiconductor packaging method according to claim 3, wherein a mixed gas including argon gas and oxygen gas is supplied to the plasma processing space when the upper surface of the sealing layer is plasma-processed, wherein the argon gas is 30 to 70% by volume, and the oxygen gas is 30 to 70% by volume.
5. The semiconductor packaging method according to claim 2, wherein an operating temperature used when the plasma treatment is performed on the upper surface of the sealing layer is 25 ℃ to 50 ℃.
6. The semiconductor packaging method according to claim 2, wherein an electric power used in the plasma treatment of the upper surface of the sealing layer is 200W to 600W.
7. The semiconductor packaging method according to claim 2, wherein a duration of the plasma treatment on the upper surface of the sealing layer is 3S to 60S.
8. The semiconductor packaging method according to claim 1, further comprising, before the mounting the chip to be packaged on the carrier:
and forming a protective layer on the front surface of the chip to be packaged.
9. The semiconductor packaging method of any one of claims 1-8, wherein after forming the encapsulation layer, the method comprises:
stripping the carrier plate to expose the front surface of the chip to be packaged;
and forming a rewiring structure on the front surface of the chip to be packaged, wherein the rewiring structure is used for leading out the welding pad on the front surface of the chip to be packaged.
10. The method of claim 9, wherein after the forming of the encapsulation layer and before the peeling of the carrier, the method comprises:
and a support layer is pasted on the first surface of the encapsulating layer far away from the carrier plate.
11. The semiconductor packaging method according to claim 10, wherein after forming a re-wiring structure on the front surface of the chip to be packaged, the method comprises:
and stripping the supporting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910177325.XA CN111668114A (en) | 2019-03-08 | 2019-03-08 | Semiconductor packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910177325.XA CN111668114A (en) | 2019-03-08 | 2019-03-08 | Semiconductor packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111668114A true CN111668114A (en) | 2020-09-15 |
Family
ID=72381432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910177325.XA Pending CN111668114A (en) | 2019-03-08 | 2019-03-08 | Semiconductor packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111668114A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020185752A1 (en) * | 2001-06-07 | 2002-12-12 | Takeshi Ishikawa | Potted hybrid integrated circuit and method for manufacturing potted hybrid integrated circuit |
| CN103579134A (en) * | 2012-07-19 | 2014-02-12 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105470209A (en) * | 2014-08-29 | 2016-04-06 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| KR20170020663A (en) * | 2015-08-13 | 2017-02-23 | 삼성전자주식회사 | Semiconductor packages and methods for fabricating the same |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
-
2019
- 2019-03-08 CN CN201910177325.XA patent/CN111668114A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020185752A1 (en) * | 2001-06-07 | 2002-12-12 | Takeshi Ishikawa | Potted hybrid integrated circuit and method for manufacturing potted hybrid integrated circuit |
| CN103579134A (en) * | 2012-07-19 | 2014-02-12 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105470209A (en) * | 2014-08-29 | 2016-04-06 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| KR20170020663A (en) * | 2015-08-13 | 2017-02-23 | 삼성전자주식회사 | Semiconductor packages and methods for fabricating the same |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI756311B (en) | Chip packaging method and packaging structure | |
| CN108172551B (en) | Chip packaging method and packaging structure | |
| US9202753B2 (en) | Semiconductor devices and methods of producing these | |
| KR20160106152A (en) | Glueless light emitting device with phosphor converter | |
| US20150130047A1 (en) | Thermally conductive molding compound structure for heat dissipation in semiconductor packages | |
| CN111916359B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668114A (en) | Semiconductor packaging method | |
| CN111668108B (en) | Semiconductor packaging method | |
| CN112117250B (en) | Chip packaging structure and manufacturing method thereof | |
| CN111952190B (en) | Semiconductor packaging method | |
| CN112397400B (en) | Semiconductor packaging method | |
| CN111668118B (en) | Semiconductor packaging method | |
| CN111668122B (en) | Semiconductor packaging method | |
| CN111668111B (en) | Semiconductor packaging method | |
| CN109300794B (en) | Package structure and method for forming the same | |
| CN112582283A (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111370360A (en) | Substrate film pasting method and packaging method | |
| CN111933534B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668123B (en) | Semiconductor packaging method | |
| JP7459576B2 (en) | Panel and manufacturing method thereof, panel manufacturing member and manufacturing method thereof, and semiconductor chip | |
| CN111599694B (en) | Semiconductor packaging method | |
| CN113725098B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668098A (en) | Semiconductor packaging method | |
| CN111668115A (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668105A (en) | Semiconductor packaging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200915 |
|
| RJ01 | Rejection of invention patent application after publication |