CN113725101A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN113725101A
CN113725101A CN202010231985.4A CN202010231985A CN113725101A CN 113725101 A CN113725101 A CN 113725101A CN 202010231985 A CN202010231985 A CN 202010231985A CN 113725101 A CN113725101 A CN 113725101A
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layer
die
opening
passive element
bare chip
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CN113725101B (en
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周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the steps of forming a first protective layer on the front surface of a first bare chip, laminating and fixing a first passive element on the front surface of the first bare chip through the first protective layer to form a laminated assembly, and forming a first opening and a second opening on the first protective layer; forming a second protective layer on the surface of the second passive element with the second electric connecting key, and forming a third opening on the second protective layer; forming a third protection layer on the front side of the second bare chip, and forming a fourth opening on the third protection layer; mounting the laminated assembly, the second passive element and the second bare chip on a carrier plate; the front surface of the first bare chip faces the carrier plate, the front surface of the second bare chip faces the carrier plate, and the surface of the second passive element with the second electric connecting keys faces the carrier plate; forming an encapsulation layer that encapsulates at least the stacked assembly, the second die, and the second passive component.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
At present, in a semiconductor packaging process, a die and a passive component, such as a capacitor, a resistor, an inductor, etc., are often required to be packaged in a package to perform a certain function. With the miniaturization and weight reduction of electronic devices, chip packages having compact structures and small volumes are increasingly favored by the market, and attention is paid to further reducing the volumes of such chip packages including bare chips and passive components.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, comprising:
forming a first protective layer on the front surface of a first bare chip, laminating and fixing a first passive element on the front surface of the first bare chip through the first protective layer to form a laminated assembly, and forming a first opening and a second opening on the first protective layer; wherein, the surface of the first passive element far away from the side of the first bare chip is covered by the first protective layer, the first opening corresponds to the first electric connection key on the first passive element, and the second opening corresponds to the first welding pad of the first bare chip;
forming a second protective layer on the surface of the second passive element with the second electric connecting key, and forming a third opening on the second protective layer; wherein the third opening corresponds to a second electrical connection key of the second passive component;
forming a third protection layer on the front side of the second bare chip, and forming a fourth opening on the third protection layer; the front surface of the second bare chip is provided with a second welding pad, and the fourth opening corresponds to the second welding pad on the front surface of the second bare chip;
mounting the stacked assembly, the second passive component and the second die on a carrier board; wherein the front surface of the first die faces the carrier board, the front surface of the second die faces the carrier board, and the surface of the second passive component having the second electrical connection keys faces the carrier board;
forming an encapsulation layer that encapsulates at least the stacked assembly, the second die, and the second passive component.
Optionally, the forming a first protection layer on the front surface of the first die, and laminating and fixing a first passive element on the front surface of the first die through the first protection layer to form a laminated assembly includes:
applying the first protective layer on the front side of the first die;
preliminary heating the first protective layer such that the first protective layer viscosity decreases, applying the first passive element through the first protective layer to a predetermined location of the first die front side;
continuing to heat the first protective layer, the first protective layer being cured by heat, the first passive element being cured to the front side of the first die with the first protective layer.
Optionally, before forming the first protective layer on the front side of the first die, the method includes:
the first die is thinned by grinding the back side of the first die.
Optionally, after forming the third protective layer on the front surface of the second die, before mounting the second die on the carrier board, the method includes:
thinning the second die by grinding a back side of the second die.
Optionally, after forming a first opening and a second opening on the first protection layer, forming a third opening on the second protection layer, and forming a fourth opening on the third protection layer, before the stacked assembly, the second passive component, and the second die are mounted on a carrier board, the method includes:
filling a first conductive medium in the first opening to form a first electric connection part capable of being electrically connected with a first electric connection key of the first passive element, filling a second conductive medium in the second opening to form a second electric connection part capable of being electrically connected with a first welding pad on the front surface of the first bare chip, filling a third conductive medium in the third opening to form a third electric connection part capable of being electrically connected with a second electric connection key of the second passive element, and filling a fourth conductive medium in the fourth opening to form a fourth electric connection part capable of being electrically connected with a second welding pad on the front surface of the second bare chip.
Optionally, after forming the encapsulation layer, the semiconductor packaging method includes:
stripping the carrier plate;
and forming wiring layers on the surfaces of the first protection layer, the second protection layer and the third protection layer, which are far away from the first bare chip, the surfaces of the second protection layer, the second protection layer and the third protection layer are far away from the second bare chip, wherein the wiring layers are electrically connected with the first electric connection key of the first passive element, the first welding pad on the front surface of the first bare chip, the second electric connection key of the second passive element and the second welding pad on the front surface of the second bare chip.
Optionally, after forming the encapsulation layer, the method comprises:
and stripping the carrier plate.
Optionally, after peeling off the carrier plate, the method includes:
filling a first conductive medium in the first opening to form a first electric connection part, filling a second conductive medium in the second opening to form a second electric connection part, filling a third conductive medium in the third opening to form a third electric connection part, filling a fourth conductive medium in the fourth opening to form a fourth electric connection part, and forming wiring layers on the surface of the first protection layer, which is far away from the first bare chip, the surface of the second protection layer, which is far away from the second passive element, and the surface of the third protection layer, which is far away from the second bare chip; the wiring layer is electrically connected with the first electric connection key of the first passive element through the first electric connection part, is electrically connected with the first welding pad on the front surface of the first bare chip through the second electric connection part, is electrically connected with the second electric connection key of the second passive element through the third electric connection part, and is electrically connected with the second welding pad on the front surface of the second bare chip through the fourth electric connection part.
Optionally, the wiring layer and the first, second, third and fourth electrical connections are formed in the same conductive layer process; or the like, or, alternatively,
after the first electrical connection portion, the second electrical connection portion, the third electrical connection portion, and the fourth electrical connection portion are formed, the wiring layer is formed in another conductive layer process.
Optionally, after forming the wiring layer, the method further includes:
forming a third electrical connection on a surface of the routing layer on a side remote from the stacked assembly, the second die, and the second passive element.
Optionally, after forming the third electrical connection, the method comprises:
and forming a dielectric layer on the wiring layer, wherein the dielectric layer can cover the exposed wiring layer, part of the third electric connection part and the exposed first, second and third protective layers, and the surface of the third electric connection part, which is far away from the wiring layer, exposes the dielectric layer.
Another aspect of the present application provides a semiconductor package structure, including:
the encapsulating layer is provided with a plurality of inwards concave first cavities, second cavities and third cavities;
the first die and the first passive element are arranged in a stacked mode, the first die and the first passive element are located in the first cavity, the back face of the first die faces the bottom of the first cavity, and the first passive element is arranged on the front face of the first die;
the second passive element is positioned in the second cavity;
a second die located within the third cavity with a back side of the second die facing a bottom of the third cavity;
a first passivation layer covering the exposed portion of the first passive element and the exposed portion of the front surface of the first die, wherein a first opening and a second opening are formed in the first passivation layer, the first opening is located at a first electrical connection key on the first passive element, and the second opening is located at a first bonding pad of the first die;
the second protective layer is formed on the surface of the second passive element, which is provided with a second electric connecting key, and a third opening is formed on the second protective layer and is positioned at the second electric connecting key on the second passive element;
the third protection layer is formed on the front surface of the second bare chip, a fourth opening is formed in the third protection layer, and the fourth opening is located at the second bonding pad of the second bare chip;
and the wiring structure comprises a wiring layer and a third electric connection part positioned on the wiring layer, and is positioned on the surface of the first protective layer far away from the first bare chip, the surface of the second protective layer far away from one side of the second passive element and the surface of the third protective layer far away from one side of the second bare chip, and is used for leading out a first welding pad on the front surface of the first bare chip, a first electric connection key of the first passive element, a second welding pad on the front surface of the second bare chip and a second electric connection key of the second passive element.
According to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the first bare chip and the first passive element are stacked to form a compact stacked assembly structure, so that the overall occupied space of a product is reduced. And protective layers are respectively formed on the surface of the laminated assembly, the surface of the second passive element and the front surface of the second bare chip in advance, and openings corresponding to the electric connecting keys of the passive elements or corresponding to the welding pads on the front surface of the bare chip are respectively formed on the protective layers, so that the electric connecting keys on the passive elements can be accurately positioned through the corresponding openings and the welding pads on the front surface of the bare chip can also be accurately positioned through the corresponding openings before a subsequent panel-level packaging process. And each protective layer can respectively protect the front surfaces of the corresponding passive element and the corresponding bare chip in the plastic packaging process so as to prevent the plastic packaging material from permeating into the front surfaces of the passive element and the bare chip to be damaged.
Drawings
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Fig. 2(a) -2(o) are process flow diagrams of a semiconductor packaging method in an exemplary embodiment according to the present disclosure.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
In a semiconductor packaging process, a die and a passive component, such as a capacitor, a resistor, an inductor, etc., are often packaged in a package to perform a certain function. With the miniaturization and weight reduction of electronic devices, chip packages having compact structures and small volumes are increasingly favored by the market, and attention is paid to further reducing the volumes of such chip packages including bare chips and passive components.
The application provides a semiconductor packaging method. In the packaging process, firstly, a first protective layer is formed on the front surface of a first bare chip, a first passive element is laminated and fixed on the front surface of the first bare chip through the first protective layer to form a laminated assembly, and a first opening and a second opening are formed on the first protective layer; the surface of the first passive element far away from the side of the first bare chip is covered by the first protective layer, the first opening is positioned at the first electric connection key on the first passive element, and the second opening is positioned at the first bonding pad of the first bare chip. Secondly, forming a second protective layer on the surface of the second passive element with the second electric connecting key, and forming a third opening on the second protective layer; wherein the third opening corresponds to a second electrical connection key of the second passive component. Further, a third protection layer is formed on the front surface of the second bare chip, and a fourth opening is formed on the third protection layer; the front surface of the second bare chip is provided with a second welding pad, and the fourth opening corresponds to the second welding pad on the front surface of the second bare chip. Then, the laminated assembly, the second passive element and the second bare chip are mounted on a carrier plate; wherein the front surface of the first bare chip faces the carrier board, the front surface of the second bare chip faces the carrier board, and the surface of the second passive component with the second electric connecting keys faces the carrier board. Finally, an encapsulation layer is formed, the encapsulation layer encapsulating at least the stacked assembly, the second die, and the second passive component. According to the embodiment of the application, a compact stacked assembly structure is formed by stacking the first bare chip and the first passive element, so that the overall occupied space of a product is reduced. And directly fix the first passive component in the front of the first bare chip through the first protective layer, and avoid fixing the first passive component through the adhesive layer, the whole thickness of the thinning product is facilitated, thereby further realizing the beneficial effect of reducing the whole occupied space of the product. And protective layers are respectively formed on the surface of the laminated assembly, the surface of the second passive element and the front surface of the second bare chip in advance, and openings corresponding to the electric connecting keys of the passive elements or corresponding to the welding pads on the front surface of the bare chip are respectively formed on the protective layers, so that the electric connecting keys on the passive elements can be accurately positioned through the corresponding openings and the welding pads on the front surface of the bare chip can also be accurately positioned through the corresponding openings before a subsequent panel-level packaging process. And each protective layer can respectively protect the front surfaces of the corresponding passive element and the corresponding bare chip in the plastic packaging process so as to prevent the plastic packaging material from permeating into the front surfaces of the passive element and the bare chip to be damaged. The semiconductor packaging structure formed by the embodiment of the application has the advantages of small volume and compact structure, and is suitable for small-sized and light-weight electronic equipment.
As shown in fig. 1, 2(a) -2(o) and 3, the present disclosure provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the semiconductor packaging method includes the following steps 101 to 109:
step 101: forming a first protective layer on the front surface of a first bare chip, laminating and fixing a first passive element on the front surface of the first bare chip through the first protective layer to form a laminated assembly, and forming a first opening and a second opening on the first protective layer; wherein, the surface of the first passive component far away from the side of the first bare chip is covered by the first protective layer, the first opening is positioned at the first electric connection key on the first passive component, and the second opening is positioned at the first welding pad of the first bare chip;
step 103: forming a second protective layer on the surface of the second passive element with the second electric connecting key, and forming a third opening on the second protective layer; wherein the third opening corresponds to a second electrical connection key of the second passive component;
step 105: forming a third protection layer on the front side of the second bare chip, and forming a fourth opening on the third protection layer; the front surface of the second bare chip is provided with a second welding pad, and the fourth opening corresponds to the second welding pad on the front surface of the second bare chip;
step 107: mounting the stacked assembly, the second passive component and the second die on a carrier board; wherein the front surface of the first die faces the carrier board, the front surface of the second die faces the carrier board, and the surface of the second passive component having the second electrical connection keys faces the carrier board;
step 109: forming an encapsulation layer that encapsulates at least the stacked assembly, the second die, and the second passive component.
As shown in fig. 2(a), in some embodiments, a first semiconductor wafer 100 is first provided. The front surface of the first semiconductor wafer 100, i.e. the front surface corresponding to the first die 201, has a first insulating layer 2011 and first pads 2012, and the first pads 2012 are used for making electrical connection with the outside world. The front side of the first die 201 is the active side of the first die 201. Next, the first semiconductor wafer 100 is diced along the dicing streets by using a dicing apparatus, so as to obtain a plurality of first dies 201. The cutting process can be mechanical cutting or laser cutting.
Optionally, in some embodiments, before the first semiconductor wafer 100 is diced, the back surface of the first semiconductor wafer 100, that is, the back surface corresponding to the first die 201, may be ground to reduce the thickness of the first die 201, so as to reduce the thickness of the final overall package structure, thereby further achieving the beneficial effect of reducing the overall occupied space.
In step 101, as shown in fig. 2(b) and fig. 2(c), the following steps S1, S2, S3 and S4 may be specifically included:
in step S1, a first protective layer 202 is applied to the front side of the first die 201. The first protective layer 202 is made of an insulating material. The first protective layer material may include BCB benzocyclobutene, PI polyimide, PBO Polybenzoxazole (Polybenzoxazole), epoxy, abf (ajinomoto buildup film), polymer matrix dielectric film, organic polymer film, or other materials having similar insulating and structural properties. It may also be an organic/inorganic composite material such as a resin polymer to which inorganic particles are added. Optionally, the first protective layer is preferably selected from materials that can accommodate chemical cleaning, polishing, and the like. The first protective layer 202 may be formed on the first die 201 by Lamination (Coating), Coating (Coating), Printing (Printing), or the like.
In step S2, after the first protective layer 202 is preliminarily heated, the first passive element 301 is applied to a predetermined position on the front surface of the first die 201 through the first protective layer 202. Since the viscosity of the first protective layer 202 is first reduced after the preliminary heating, the first protective layer 202 has strong fluidity. Therefore, the first passive element 301 is placed at a predetermined position on the front surface of the first die 201, and the preliminarily heated first protective layer 202 originally between the first passive element 301 and the first die 201 can be pushed away by pressing so that the first passive element 301 can be placed at a predetermined position on the front surface of the first die 201 through the first protective layer having reduced viscosity.
In step S3, the first protection layer 202 is continuously heated, and as the heating proceeds, the first protection layer 202 is heated and cured, and the first passive element 301 is cured to the front surface of the first die 201 along with the first protection layer 202.
Since the first passive element is often smaller, and in this embodiment, the first passive element 301 is significantly smaller than the first die 201, after the first passive element 301 is disposed on the front surface of the first die 201, and before the temperature of the first protection layer reaches the curing temperature, the viscosity of the material of the first protection layer 202 is lower, and a portion of the first protection layer 202 can move to cover the surface of the first passive element 301. Therefore, after the first passivation layer 202 is further heated and cured, when the first passive element 301 is cured to the front surface of the first die 201 along with the first passivation layer 202, the surface of the first passive element 301 away from the first die 202 is also covered by the first passivation layer 202, which can be actually understood as the surface of the first passive element 301 other than the surface attached to the front surface of the first die 201 is covered by the first passivation layer 202. In this application, the surface 2002 of the finally formed first protection layer 202, which is away from the side of the first die 201, is entirely planar for subsequent mounting.
It should be noted that the temperature of the material used for the first protective layer is generally selected to be lower than the curing temperature of the material used for the first protective layer. According to the rheological characteristics of the first protective layer material in the curing process, the viscosity of the first protective layer material is reduced along with the increase of the temperature during primary heating, and when the temperature is increased to the curing temperature or above, the first protective layer material can generate cross-linking among molecules, so that the viscosity is increased, and the curing effect is achieved. In the preliminary heating of the first protective layer, the preliminary heating is such that the temperature of the first protective layer should be below and controllable below the curing temperature of the material layer. Optionally, in the preliminary heating of the first protective layer, the preliminary heating allows the temperature of the first protective layer to be controlled at or near the lowest viscosity that allows the curing rheology of the first protective layer material. Thus, the first passive element is convenient to be arranged. While after the first passive element is applied to the predetermined location of the first die, heating may continue to raise the temperature of the first protective layer to or above its curing temperature. The time length of the preliminary heating, the temperature reached by the first protection layer after the preliminary heating, the time length of the continuous heating, and the temperature reached by the first protection layer after the continuous heating can all be determined according to the specific application environment, such as the material of the first protection layer and the corresponding curing temperature thereof.
As can be seen from the above, the step of laminating the first passive element 301 to the first die 201 and the step of forming the first protective layer 202 on the first die 201 are performed simultaneously.
In step S4, a first opening 2021 and a second opening 2022 are formed on the first protective layer, respectively. The first opening 2021 corresponds to the first electrical connection key of the first passive element 301, such that the first electrical connection key of the first passive element 301 is exposed from the first opening 2021. The second opening 2022 corresponds to at least the first pad on the front surface of the first die 201 or the line led out from the first pad, so that the first pad on the front surface of the first die 201 or the line led out from the first pad is exposed from the second opening 2022.
For the material of the first protection layer 202 being a laser-reactive material, the first opening 2021 and the second opening 2022 can be formed by laser patterning. For the material of the first protection layer 202 is a photosensitive material, the first opening 2021 and the second opening 2022 can be formed by photolithography patterning. The shape of the first opening 2021 may be round, but may be other shapes such as oval, square, linear, etc. Of course, the shape of the second opening 2022 may be round, but may also be other shapes such as oval, square, linear, etc.
It should be noted that in fig. 2(b) and other subsequent figures, the front surface of the first die 201 still has the first insulating layer and the first bonding pads, which are not labeled in the figures for convenience of showing the subsequent process flow, and the first die may have more first bonding pads, and the first passivation layer correspondingly has more corresponding second openings.
Optionally, as shown in fig. 2(d), in some embodiments, after completing step 101 and before entering step 103, the semiconductor packaging method may include the following step 102:
in step 102: filling a first conductive medium in the first opening 2021 to form a first electrical connection portion 2031 capable of being electrically connected to the first electrical connection key of the first passive element 301, so that the first electrical connection key of the first passive element 301 is led out to the surface of the first protection layer 202; and filling a second conductive medium in the second opening 2022 to form a second electrical connection portion 2032 capable of electrically connecting with the first pad 2012 on the front surface of the first die 201, so that the first pad 2012 on the front surface of the first die 201 is led out to the surface of the first protection layer 202.
Of course, in some other embodiments, after the first opening and the second opening are formed, the first opening may not be filled with the first conductive medium, and the second opening may not be filled with the second conductive medium, so that the plurality of first openings and the plurality of second openings are still in a hollow state after the stacked assembly formed in step 101 is mounted on the carrier board subsequently.
In step 103, as shown in fig. 2(e), a second passivation layer 302 'is formed on the surface of the second passive element 301' having the second electrical connection keys. The second protective layer 302' may be made of an insulating material. The material of the second passivation layer 302' may also include BCB benzocyclobutene, PI polyimide, PBO Polybenzoxazole (Polybenzoxazole), epoxy, abf (ajinomoto build film), polymer matrix dielectric film, organic polymer film, or other materials with similar insulating and structural properties. It may also be an organic/inorganic composite material such as a resin polymer to which inorganic particles are added. Optionally, the second passivation layer 302' is preferably selected to be compatible with chemical cleaning, polishing, etc. The second protective layer protection layer 302 'may be formed on the second passive element 301' by Lamination (Coating), Coating (Coating), Printing (Printing), or the like.
After the second protective layer 302 ' is formed, a third opening 3021 ' is formed on the second protective layer 302 '. The third opening 3021 'corresponds to a second electrical connection key (not shown) of the second passive element 301' such that the second electrical connection key of the second passive element 301 'is exposed from the third opening 3021'. For the material of the second protective layer 302 'being a laser-reactive material, the third opening 3021' may be formed by laser patterning. For the material of the second protection layer 302 'being a photosensitive material, the third opening 3021' may be formed by using a photolithography patterning method. The shape of the third opening 3021' may be round, but may also be other shapes such as oval, square, linear, etc.
In some embodiments, after step 103 is completed, before step 105 is entered, the semiconductor packaging method may include step 104 of:
a third conductive medium is filled in the third opening 3021 ', and a third electrical connection portion 2031 ' electrically connectable to the second electrical connection key of the second passive element 301 ' is formed such that the second electrical connection key of the second passive element 301 ' is led out to the surface of the second protective layer 302 '.
Of course, in other embodiments, after the third opening is formed, the third opening may not be filled with the third conductive medium, and the plurality of third openings are still in a hollow state after the second passive component formed in step 103 is mounted on the carrier board in the following step.
In step 105, a third protection layer is formed on the front surface of the second die, where the third protection layer may be formed on the front surface of the semiconductor wafer before the semiconductor wafer is cut into a plurality of second dies, and then the semiconductor wafer is cut to obtain the second die with the third protection layer formed on the front surface. It is understood that, when the process allows, the semiconductor wafer may be cut into the second dies, and then the third protective layer is formed on the front surface of each second die, which may be selected according to a specific application, and the present application does not limit this.
As shown in fig. 2(f), the front surface of the second semiconductor wafer 100 ', corresponding to the front surface of the second die 201', has a second insulating layer 2011 'and second pads 2012'. The second pad 2012' is used for electrical connection with the outside. The front side of the second die 201 ', i.e. the active side of the second die 201'. A third protection layer 202 ' is formed on the front side of the second semiconductor wafer 100 ', i.e. the front side corresponding to the second die 201 '.
The third protection layer 202' is made of an insulating material. The material of the third protective layer may include BCB benzocyclobutene, PI polyimide, PBO Polybenzoxazole (Polybenzoxazole), epoxy, abf (ajinomoto build film), polymer matrix dielectric film, organic polymer film, or other materials having similar insulating and structural properties. It may also be an organic/inorganic composite material such as a resin polymer to which inorganic particles are added. Optionally, the third passivation layer 202' is preferably selected to be compatible with chemical cleaning, polishing, etc. The third protective layer 202 'may be formed on the second die 201' by Lamination (Coating), Coating (Coating), Printing (Printing), and the like.
Further, after forming the third protection layer 202 ' on the front side of the second semiconductor wafer 100 ', the back side of the second semiconductor wafer 100 ', i.e. the back side corresponding to the second die 201 ', may be ground to reduce the thickness of the second die 201 '. Of course, in some embodiments, the back side of the second die may not be thinned, which is not limited in this application and may be set according to the specific application environment.
Further, the second semiconductor wafer 100 'is diced along the dicing streets by using a dicing apparatus, so as to obtain a plurality of second dies 201'. The cutting process can be mechanical cutting or laser cutting.
Further, as shown in fig. 2(g), a fourth opening 2021 'is formed on the third protective layer 202'. The fourth opening 2021 'corresponds to at least the second pad on the front surface of the second die 201' or the line led out from the second pad, so that the second pad on the front surface of the second die 201 'or the line led out from the second pad is exposed from the fourth opening 2021'. Similarly, for the material of the third protective layer 202 'being a laser-reactive material, the fourth opening 2021' can be formed by laser patterning. For the material of the third protection layer 202 'being a photosensitive material, the fourth opening 2021' can be formed by using a photolithography patterning method. The shape of the fourth opening 2021' may be round, but may also be other shapes such as oval, square, linear, etc.
It should be noted that the fourth opening 2021 'may also be formed after the third passivation layer 202' is formed on the front surface of the second semiconductor wafer 100 'and before the second semiconductor wafer 100' is diced. The present application is not limited to this, and may be set according to a specific application environment.
To facilitate the demonstration of the subsequent process flow, the subsequent second die 201' may adopt the schematic structure diagram shown in fig. 2 (g). It should be noted that in fig. 2(g) and other subsequent figures, the front surface of the second die still has the second insulating layer and the second pads, and the second die may have more second pads, and the third passivation layer correspondingly has more corresponding fourth openings.
It should be further noted that step 101, step 103 and step 105 are not in the order of their sequence. For example, in some embodiments, step 101, step 103, and step 105 may be performed simultaneously. Step 101, step 103 and step 105 may not be performed simultaneously. The specific sequence of steps 101, 103 and 105 may be set according to a specific application environment, which is not limited in this application.
As shown in fig. 2(h), in some embodiments, after completing step 105 and before entering step 107, the semiconductor packaging method may include the following step 106:
a fourth conductive medium is filled in the fourth opening 2021 ', and a fourth electrical connection portion 2032 ' capable of electrically connecting to the second pad 2012 ' on the front surface of the second die 201 ' is formed, so that the second pad 2012 ' on the front surface of the second die 201 ' is led out to the surface of the third passivation layer 202 '.
Of course, in other embodiments, after the fourth opening is formed, the fourth opening may not be filled with the fourth conductive medium, so that the plurality of fourth openings are still hollow after the second die formed in step 105 is mounted on the carrier board.
In step 107, as shown in fig. 2(i), the stacked assembly with the first passivation layer 202, the second passive element 301 'with the second passivation layer 302', and the second die 201 'with the third passivation layer 202' are mounted on the carrier 200. The front surface of the first die 201 faces the carrier 200, the front surface of the second die 201 'faces the carrier 200, and the surface of the second passive component 301' having the second electrical connection keys also faces the carrier 200.
Alternatively, the carrier plate may be attached by an adhesive layer (not shown). The adhesive layer is used to bond the laminated assembly with the first protective layer 202, and the adhesive layer may be made of a material that is easily peeled off, so that the carrier sheet and the laminated assembly with the first protective layer 202 are peeled off in a subsequent process, for example, a thermal release material that can be heated to lose its adhesiveness.
Alternatively, in other embodiments, the adhesive layer may have a two-layer structure, i.e., a thermal separation material layer and an adhesive layer, the thermal separation material layer is adhered to the carrier 200 and loses its viscosity when heated, so as to be able to be peeled off from the carrier 200, and the adhesive layer has an adhesive material layer and can be used for adhering the stacked assembly with the first protection layer 202. After the laminated assembly with the first protective layer 202 is peeled off from the carrier 200, the adhesion layer thereon can be removed by chemical cleaning. In one embodiment, the adhesive layer may be formed on the carrier 200 by lamination, printing, or the like.
The second passive element 301 'with the second passivation layer 302' and the second die 201 'with the third passivation layer 202' can be mounted on the carrier board in the same manner. Reference is made to the above description, which is not repeated herein.
It should be noted that, as shown in fig. 2(i), the stacked assembly (i.e., the stacked assembly having the first protective layer 202, the first die 201, and the first passive element 301), the second passive element 301 '(i.e., the second passive element 301' having the second protective layer 302 '), and the second die 201' (i.e., the second die 201 'having the third protective layer 202') are disposed on the carrier board 200 according to a predetermined arrangement position, and for convenience of expression, only one stacked assembly, one second passive element 301 ', and one second die 201' are shown in the drawing, and actually, a plurality of stacked assemblies, second dies 201 ', and second passive elements 301' are disposed on the carrier board 200 according to the predetermined arrangement position. Optionally, the stacked assembly, the second passive element 301 'and the second die 201' may be disposed on the carrier 200 at intervals.
It can be understood that, in one packaging process, the stacked assembly, the second bare chip and the second passive component may be multiple, that is, a plurality of stacked assemblies with a first protection layer, a plurality of second passive components with a second protection layer and a plurality of second bare chips with a third protection layer are simultaneously mounted on the carrier, packaged, and cut into a plurality of packages after the packaging is completed; one package may include one or more stacked assemblies, one or more second passive components, and one or more second dies, and the positions and specific numbers of the one or more stacked assemblies, the one or more second passive components, and the one or more second dies may be set according to the needs of an actual product, for example, according to specific functional requirements of the product.
In step 109, an encapsulation layer 204 is formed on the carrier 200, and the encapsulation layer may encapsulate at least a portion of the stacked assembly, at least a portion of the second die, and at least a portion of the second passive component. For example, the encapsulating layer 204 can encapsulate the surface of the stacked assembly away from the carrier 200, the surface of the second passive component 301 'away from the carrier 200, the back surface of the second die 201', and the exposed carrier 200. For the carrier with the adhesive layer, the encapsulating layer can cover the surface of the stacked assembly away from the carrier 200, the surface of the second passive element 301 'away from the carrier, the back surface of the second die 201', and the exposed adhesive layer. Of course, if the surface of the carrier 200 close to the stacked assembly, which is far from the carrier 200, and the surface of the second die 201 'and the second passive component 301' still have an exposed area, the exposed area can also be covered by the encapsulating layer. As shown in fig. 2(j), the encapsulating layer 204 completely encapsulates the carrier 200, the stacked assembly, the second passive component having the second passivation layer 302 ', and the second die 201 ' having the third passivation layer 202 ' to reconstruct a flat plate structure, so that the re-routing and packaging can be continued on the reconstructed flat plate structure after the carrier 200 is peeled off.
In one embodiment, the encapsulating layer 204 may be formed by laminating an epoxy resin film or an abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound.
The upper surface 2041 of the encapsulating layer 204 away from the carrier 200 is substantially flat and parallel or substantially parallel to the surface of the carrier 200. The thickness of encapsulant layer 204 may be thinned by grinding or polishing surface 2041.
When the encapsulating layer 204 is used for encapsulating, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material is easily penetrated between the carrier 200 and the stacked component, between the carrier 200 and the second die 201 ', or between the carrier 200 and the second passive component 301' in the process. The first, second and third protection layers can prevent the encapsulating material from penetrating into the surfaces of the first bare chip, the first passive element, the second bare chip and the second passive element, and the encapsulating material cannot directly contact the front surface of the first bare chip, the front surface of the second bare chip and the surfaces of the first and second passive elements with the first and second electric connection keys, so that the circuit structures of the front surfaces of the first bare chip and the second bare chip, the first passive element and the second passive element cannot be damaged.
Further, in some embodiments, as shown in fig. 2(k), the carrier sheet 200 may be peeled off after the formation of the encapsulation layer 204. For the adhesive layer having the thermal decomposition film between the stacked assembly, the second die 201 ', and the second passive element 301' and the carrier 200, the adhesive layer may be reduced in viscosity after being heated by heating, so as to peel off the carrier 200. By peeling the carrier plate 200 by means of the heated adhesive layer, damage to the stack, the second die 201 'and the second passive component 301' during the peeling process can be minimized. Of course, in other embodiments, the carrier board 200 can be directly and mechanically peeled off.
After the carrier board 200 is peeled off, the lower surface of the encapsulating layer 204, the surface of the first passivation layer 202, the surface of the second passivation layer 302 ', the surface of the third passivation layer 202', the surface of the first electrical connection portion 2031, the surface of the second electrical connection portion 2032, the surface of the third electrical connection portion 2031 ', and the surface of the fourth electrical connection portion 2032', which originally face the carrier board 200, may be exposed. In this way, after the carrier board 200 is peeled off, a flat panel structure including the stacked assembly having the first protection layer 202, the second die 201 ', the second passive element 301', the second protection layer 302 ', the third protection layer 202', and the encapsulating layer 204 can be obtained. On the formed flat plate structure, wiring can be performed according to actual conditions, so that the first die 201, the first passive element 301, the second die 201 'and the second passive element 301' form electrical connection with the outside. Electrical connections between the first die 201, the first passive element 301, the second die 2012 'and the second passive element 301' may also be formed simultaneously.
Accordingly, after the carrier board 200 is peeled off, the surfaces of the first protection layer 202, the second protection layer 302 'and the third protection layer 202' are exposed, and the stacked assembly, the second passive element 301 'and the second die 201' are attached to the carrier board 200 through an adhesive layer having a thermal release material layer and an adhesion layer, which is also present on the surfaces of the first protection layer 202, the second protection layer 302 'and the third protection layer 202', and which can be removed by chemical means. When the adhesion layer is removed by a chemical method, the first protection layer 202, the second protection layer 302 'and the third protection layer 202' can also protect the surfaces of the first die 201, the first passive element 301, the second passive element 301 'and the second die 201' from being damaged. After the adhesive layer is completely removed, if the encapsulating material is infiltrated in the prior art, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated. Without the first, second, and third protective layers 202, 302 ', and 202', the surfaces of the stacked assembly, the second die 201 ', and the second passive element 301' cannot be processed chemically or by grinding, and the protective layers are disposed such that the front surface of the first die 201, the circuits on the front surface of the second die 201 ', the first passive element 301, and the second passive element 301' are protected from being damaged.
Similar plate-like structures can also be formed after peeling the carrier board 200, without forming the first, second, third and fourth electrical connections in the first, second, third and fourth openings before step 107. Furthermore, the wiring on the formed flat plate structure can be performed according to the actual situation, and specific reference may be made to the above description, which is not repeated herein.
After the carrier board 200 is stripped, as shown in fig. 2(l), a wiring layer 206 having conductive traces is formed on the surface of the stacked assembly away from the first die 201, the surface of the second protection layer 302 'away from the second passive element 301', and the surface of the third protection layer 202 'away from the second die 201'. The wiring layer 206 is formed on the surface of the first passivation layer 202, the surface of the second passivation layer 302 ', the surface of the third passivation layer 202', and the surface of the encapsulating layer 204 on the same side. The wiring layer 206 is electrically connected to the first electrical connection portion 2031, the second electrical connection portion 2032, the third electrical connection portion 2031 'and the fourth electrical connection portion 2032', the wiring layer 206 is electrically connected to the first electrical connection key of the first passive element 301 through the first electrical connection portion 2031, electrically connected to the first bonding pad on the front surface of the first die 201 through the second electrical connection portion 2032, electrically connected to the second electrical connection key of the second passive element 301 'through the third electrical connection portion 2031', and electrically connected to the second bonding pad on the front surface of the second die 201 'through the fourth electrical connection portion 2032'.
As can be seen from the above description of the present embodiment, the wiring layer 206 and the first, second, third and fourth electrical connections 2031, 2032, 2031 'and 2032' are not formed in the same conductive layer process. Whether the first, second, third and fourth electric connection parts are arranged on the same conductive layer or not is not limited, and the first, second, third and fourth electric connection parts can be arranged according to specific application environments.
Of course, in other embodiments, for the first, second, third, and fourth electrical connections not formed in the first, second, third, and fourth openings respectively before performing step 107, after the carrier board 200 is peeled off, a first conductive medium may be filled in the first opening to form a first electrical connection, and a second conductive medium may be filled in the second opening to form a second electrical connection, a first conductive medium is filled in the third opening to form a third electrical connection, a second conductive medium is filled in the fourth opening to form a fourth electrical connection, and wiring layers are formed on the surface of the first protection layer away from the first die, the surface of the second protection layer away from the second passive element, and the surface of the third protection layer away from the second die. Accordingly, the wiring layer 206 and the first, second, third, and fourth electrical connections may be formed in the same conductive layer process. Of course, the wiring layer 206 and the first, second, third, and fourth electrical connections may not be formed in the same conductive layer process, and the present application is not limited thereto, and may be set according to a specific application environment.
Further, as shown in fig. 2(m), after the wiring layer 206 is formed, a third electrical connection 207 is formed on a surface of the wiring layer 206 on a side away from the stacked assembly, the second die 201 ', and the second passive element 301'.
Further, as shown in fig. 2(n), a dielectric layer 208 is formed on the surfaces of the wiring layer 206 and the third electrical connection portion 207 to protect the wiring layer 206 and the third electrical connection portion 207. The dielectric layer 208 may be formed to a thickness such that the surface of the third electrical connection portion 207 is just exposed; the dielectric layer 208 may cover all exposed surfaces of the encapsulating layer 204, the first protective layer 202, the second protective layer 302 ', the third protective layer 202', and the wiring layer 206, and then be thinned to the surface of the third electrical connection portion 207. In this embodiment, a combination of the wiring layer 206, the third electrical connection portion 207, and the dielectric layer 208 can be understood as a wiring structure.
The third electrical connection portion 207 is preferably circular, but may be other shapes such as a rectangle and a square, and the third electrical connection portion 207 is electrically connected to the wiring layer 206. Specifically, the third electrical connection portion 207 may be formed in the wiring layer 206 by photolithography and plating.
In another embodiment, after the wiring layer 206 is formed, the dielectric layer 208 is formed on the wiring layer 206 and the exposed first protection layer 202, the second protection layer 302 ', the third protection layer 202' and the encapsulating layer 204, and the dielectric layer 208 has a dielectric layer opening, and then the third electrical connection portion 207 electrically connected to the wiring layer 206 is formed in the dielectric layer opening of the dielectric layer 208. In this embodiment, a combination of the wiring layer 206, the third electrical connection portion 207, and the dielectric layer 208 can be understood as a wiring structure.
In yet another embodiment, the dielectric layer opening of the dielectric layer may not be filled, i.e. the third electrical connection portion 207 electrically connected to the wiring layer 206 is not formed, so that the second pad or connection point of the wiring layer of the completed package is exposed from the dielectric layer opening. In this embodiment, the combination of the wiring layer 206 and the dielectric layer 208 can be understood as a wiring structure.
In one embodiment, the dielectric layer 208 may be formed by Lamination (plating), Molding (Molding) or Printing (Printing), and preferably an epoxy compound is used.
Further, in some embodiments, repeated rewiring may be performed in addition to the wiring structure, such as by forming one or more wiring layers outside the dielectric layer in the same manner to achieve multi-layer wiring of the product.
Further, after the package of the wiring structure is formed, as shown in fig. 2(o), the entire package structure is cut into a plurality of packages, i.e., semiconductor package structures, by laser or mechanical cutting, and the structure of the formed semiconductor package structure is shown in fig. 3.
The semiconductor packaging method provided by the above embodiment forms a compact stacked assembly structure through the stacked arrangement of the first die and the first passive element, thereby reducing the overall occupied space of the product. And directly fix the first passive component in the front of the first bare chip through the first protective layer, and avoid fixing the first passive component through the adhesive layer, the whole thickness of the thinning product is facilitated, thereby further realizing the beneficial effect of reducing the whole occupied space of the product. And protective layers are respectively formed on the surface of the laminated assembly, the surface of the second passive element and the front surface of the second bare chip in advance, and openings corresponding to the electric connecting keys of the passive elements or corresponding to the welding pads on the front surface of the bare chip are respectively formed on the protective layers, so that the electric connecting keys on the passive elements can be accurately positioned through the corresponding openings and the welding pads on the front surface of the bare chip can also be accurately positioned through the corresponding openings before a subsequent panel-level packaging process. According to the arrangement mode, the area of each opening in the protective layer can be smaller, and the distance between the openings of the protective layer can also be smaller, so that the conducting traces can be tighter in the subsequent forming process of the wiring structure, and the problem that the position of the welding pad can have positioning deviation and the like is not worried when the tighter conducting traces are arranged. And each protective layer can respectively protect the front surfaces of the corresponding passive element and the corresponding bare chip in the plastic packaging process so as to prevent the plastic packaging material from permeating into the front surfaces of the passive element and the bare chip to damage the front surfaces. In addition, the protective layer is arranged, in the subsequent wiring process, the wiring process of the conductive trace can be carried out without forming a layer of insulating material on the whole panel, the advantages of material saving (especially for the whole large panel, the saved material is considerable) and smaller process difficulty are achieved, and the problem that the process difficulty of forming the insulating layer on the whole large panel is large is solved.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present application. Referring to fig. 3 and as necessary in conjunction with fig. 2(a) -2(o), the semiconductor package structure includes:
the encapsulating layer 204 is provided with a plurality of concave first cavities, second cavities and third cavities.
The semiconductor device comprises a first die 201 and a first passive element 301 which are arranged in a stacked mode, wherein the first die 201 and the first passive element 301 are located in the first cavity, the back surface of the first die 201 faces the bottom of the first cavity, and the first passive element 301 is arranged on the front surface of the first die.
A second passive element 301' is located within the second cavity.
A second die 201 'is located within the third cavity with the back side of the second die 201' facing the bottom of the third cavity.
The first passivation layer 202 covers the exposed portion of the first passive element 301 and the exposed portion of the front surface of the first die 201, and a first opening 2021 and a second opening 2022 are formed on the first passivation layer 202, wherein the first opening 2021 is located at the first electrical connection key on the first passive element 301, and the second opening 2022 is located at the first pad of the first die 201.
A second passivation layer 302 'is formed on the surface of the second passive device 301' having the second electrical connection key, and a third opening 3021 'is formed in the second passivation layer 302', and the third opening 3021 'is located at the second electrical connection key on the second passive device 301'.
The third passivation layer 202 'is formed on the front surface of the second die 201', and a fourth opening 2021 'is formed on the third passivation layer 202', the fourth opening 2021 'being located at the second bonding pad of the second die 201'.
And the wiring structure comprises a wiring layer 206 and a third electric connection part 207 positioned on the wiring layer 206, wherein the surface of the first protective layer 202 positioned on the side far away from the first bare chip 201, the surface of the second protective layer 302 'positioned on the side far away from the second passive element 301', and the surface of the third protective layer 202 'positioned on the side far away from the second bare chip 201' are used for leading out a first bonding pad on the front surface of the first bare chip 201, a first electric connection key of the first passive element 301, a second bonding pad on the front surface of the second bare chip 201 'and a second electric connection key of the second passive element 301'.
According to the embodiments of the present application, a compact stacked assembly structure is formed by stacking the first die and the first passive element, so that the overall occupied space of the product is reduced. And protective layers are respectively arranged on the surface of the laminated assembly, the surface of the second passive element and the front surface of the second bare chip, and the protective layers can protect the corresponding passive element and the front surface of the corresponding bare chip. The semiconductor packaging structure of the embodiment of the application has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.
In some embodiments, the first passive element 301 may be a capacitor, a resistor, an inductor, or the like. The second passive element 301' may also be a capacitor, a resistor, an inductor, etc. Typically, the first passive element 301 and the second passive element 301 'are smaller than the first die 201 and the second die 201'.
In some embodiments, the first passive element 301 in the semiconductor package structure is smaller than the first die 201, and a projection of the first passive element 301 on the front side of the first die 201 is located within the outer perimeter of the first die 201.
In some embodiments, the wiring layer 206 is electrically connected to the second passive element 301 'through the third electrical connection portion 2031' in the third opening 3021 'and electrically connected to the second die 201' through the fourth electrical connection portion 2032 'in the fourth opening 2021'.
Further, the wiring structure may further include a dielectric layer 208. The dielectric layer 208 is formed on the wiring layer 206 and the exposed first passivation layer 202, the exposed second passivation layer 302, the exposed third passivation layer 202', and the exposed encapsulating layer 204, and has a dielectric layer opening. The dielectric layer opening is provided with a third electrical connection portion 207 electrically connected to the wiring layer 206.
In another embodiment, the wiring structure includes more wiring layers to achieve multi-layer wiring of the product.
In the present embodiment, each structural element of the semiconductor package structure can refer to the related description of the corresponding structural element in the semiconductor package method, which is not repeated herein.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (12)

1. A semiconductor packaging method, comprising:
forming a first protective layer on the front surface of a first bare chip, laminating and fixing a first passive element on the front surface of the first bare chip through the first protective layer to form a laminated assembly, and forming a first opening and a second opening on the first protective layer; wherein, the surface of the first passive element far away from the side of the first bare chip is covered by the first protective layer, the first opening corresponds to the first electric connection key on the first passive element, and the second opening corresponds to the first welding pad of the first bare chip;
forming a second protective layer on the surface of the second passive element with the second electric connecting key, and forming a third opening on the second protective layer; wherein the third opening corresponds to a second electrical connection key of the second passive component;
forming a third protection layer on the front side of the second bare chip, and forming a fourth opening on the third protection layer; the front surface of the second bare chip is provided with a second welding pad, and the fourth opening corresponds to the second welding pad on the front surface of the second bare chip;
mounting the stacked assembly, the second passive component and the second die on a carrier board; wherein the front surface of the first die faces the carrier board, the front surface of the second die faces the carrier board, and the surface of the second passive component having the second electrical connection keys faces the carrier board;
forming an encapsulation layer that encapsulates at least the stacked assembly, the second die, and the second passive component.
2. The semiconductor packaging method of claim 1, wherein forming a first protective layer on the front side of the first die, and laminating and fixing a first passive element to the front side of the first die through the first protective layer to form a laminated assembly comprises:
applying the first protective layer on the front side of the first die;
preliminary heating the first protective layer such that the first protective layer viscosity decreases, applying the first passive element through the first protective layer to a predetermined location of the first die front side;
continuing to heat the first protective layer, the first protective layer being cured by heat, the first passive element being cured to the front side of the first die with the first protective layer.
3. The semiconductor packaging method of claim 1, wherein prior to forming the first protective layer on the front side of the first die, the method comprises:
the first die is thinned by grinding the back side of the first die.
4. The method of packaging a semiconductor of claim 1, wherein after forming a third protective layer on a front side of the second die, and before mounting the second die on a carrier board, the method comprises:
thinning the second die by grinding a back side of the second die.
5. The method of packaging a semiconductor of claim 1, wherein after forming a first opening and a second opening in the first protective layer, a third opening in the second protective layer, and a fourth opening in the third protective layer, the method comprises, prior to mounting the stacked assembly, the second passive component, and the second die on a carrier board:
filling a first conductive medium in the first opening to form a first electric connection part capable of being electrically connected with a first electric connection key of the first passive element, filling a second conductive medium in the second opening to form a second electric connection part capable of being electrically connected with a first welding pad on the front surface of the first bare chip, filling a third conductive medium in the third opening to form a third electric connection part capable of being electrically connected with a second electric connection key of the second passive element, and filling a fourth conductive medium in the fourth opening to form a fourth electric connection part capable of being electrically connected with a second welding pad on the front surface of the second bare chip.
6. The semiconductor packaging method of claim 5, wherein after forming the encapsulation layer, the semiconductor packaging method comprises:
stripping the carrier plate;
and forming wiring layers on the surfaces of the first protection layer, the second protection layer and the third protection layer, which are far away from the first bare chip, the surfaces of the second protection layer, the second protection layer and the third protection layer are far away from the second bare chip, wherein the wiring layers are electrically connected with the first electric connection key of the first passive element, the first welding pad on the front surface of the first bare chip, the second electric connection key of the second passive element and the second welding pad on the front surface of the second bare chip.
7. The semiconductor packaging method of claim 1, wherein after forming the encapsulation layer, the method comprises:
and stripping the carrier plate.
8. The semiconductor packaging method of claim 7, wherein after peeling the carrier plate, the method comprises:
filling a first conductive medium in the first opening to form a first electric connection part, filling a second conductive medium in the second opening to form a second electric connection part, filling a third conductive medium in the third opening to form a third electric connection part, filling a fourth conductive medium in the fourth opening to form a fourth electric connection part, and forming wiring layers on the surface of the first protection layer, which is far away from the first bare chip, the surface of the second protection layer, which is far away from the second passive element, and the surface of the third protection layer, which is far away from the second bare chip; the wiring layer is electrically connected with the first electric connection key of the first passive element through the first electric connection part, is electrically connected with the first welding pad on the front surface of the first bare chip through the second electric connection part, is electrically connected with the second electric connection key of the second passive element through the third electric connection part, and is electrically connected with the second welding pad on the front surface of the second bare chip through the fourth electric connection part.
9. The semiconductor packaging method according to claim 8, wherein the wiring layer and the first, second, third, and fourth electrical connections are formed in the same conductive layer process; or the like, or, alternatively,
after the first electrical connection portion, the second electrical connection portion, the third electrical connection portion, and the fourth electrical connection portion are formed, the wiring layer is formed in another conductive layer process.
10. The semiconductor packaging method according to claim 6, 8 or 9, wherein after forming the wiring layer, the method further comprises:
forming a third electrical connection on a surface of the routing layer on a side remote from the stacked assembly, the second die, and the second passive element.
11. The semiconductor packaging method of claim 10, wherein after forming the third electrical connection, the method comprises:
and forming a dielectric layer on the wiring layer, wherein the dielectric layer can cover the exposed wiring layer, part of the third electric connection part and the exposed first, second and third protective layers, and the surface of the third electric connection part, which is far away from the wiring layer, exposes the dielectric layer.
12. A semiconductor package, comprising:
the encapsulating layer is provided with a plurality of inwards concave first cavities, second cavities and third cavities;
the first die and the first passive element are arranged in a stacked mode, the first die and the first passive element are located in the first cavity, the back face of the first die faces the bottom of the first cavity, and the first passive element is arranged on the front face of the first die;
the second passive element is positioned in the second cavity;
a second die located within the third cavity with a back side of the second die facing a bottom of the third cavity;
a first passivation layer covering the exposed portion of the first passive element and the exposed portion of the front surface of the first die, wherein a first opening and a second opening are formed in the first passivation layer, the first opening is located at a first electrical connection key on the first passive element, and the second opening is located at a first bonding pad of the first die;
the second protective layer is formed on the surface of the second passive element, which is provided with a second electric connecting key, and a third opening is formed on the second protective layer and is positioned at the second electric connecting key on the second passive element;
the third protection layer is formed on the front surface of the second bare chip, a fourth opening is formed in the third protection layer, and the fourth opening is located at the second bonding pad of the second bare chip;
and the wiring structure comprises a wiring layer and a third electric connection part positioned on the wiring layer, and is positioned on the surface of the first protective layer far away from the first bare chip, the surface of the second protective layer far away from one side of the second passive element and the surface of the third protective layer far away from one side of the second bare chip, and is used for leading out a first welding pad on the front surface of the first bare chip, a first electric connection key of the first passive element, a second welding pad on the front surface of the second bare chip and a second electric connection key of the second passive element.
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