WO2022012511A1

WO2022012511A1 - Semiconductor packaging method and semiconductor packaging structure

Info

Publication number: WO2022012511A1
Application number: PCT/CN2021/105965
Authority: WO
Inventors: 周辉星
Original assignee: 矽磐微电子(重庆)有限公司
Priority date: 2020-07-13
Filing date: 2021-07-13
Publication date: 2022-01-20
Also published as: CN113937015A

Abstract

A semiconductor packaging method, comprising: arranging a passive piece on a reverse surface of a first bare chip; fixing conductive pillars, a second bare chip, and the first bare chip fixed with the passive piece onto a carrier board, active faces of the first bare chip and the second bare chip facing the carrier board, and the conductive pillars being arranged on the peripheral sides of the first bare chip and the second bare chip; forming a first wiring redistribution layer above the first bare chip, the second bare chip, and the conductive pillars, the first wiring redistribution layer electrically connecting the passive piece and the conductive pillars; removing the carrier board; and arranging a second wiring redistribution layer on the side of the active faces of the first bare chip and the second bare chip, the second wiring redistribution layer electrically connecting solder pads located on the active face of the first bare chip, solder pads located on the active face of the second bare chip, and the conductive pillars. A semiconductor packaging structure is further provided.

Description

Semiconductor packaging method and semiconductor packaging structure

technical field

Embodiments of the present disclosure relate to a semiconductor packaging method and a semiconductor packaging structure.

Background technique

At present, in the packaging process, bare chips with different functions are often packaged in one package structure to form a chip package with a specific function, that is, a multi-chip module package structure (multi-chip module, MCM).

With the miniaturization and weight reduction of electronic devices, chip packages with compact structure and small volume are favored by more and more markets.

SUMMARY OF THE INVENTION

At least one embodiment of the present disclosure provides a semiconductor packaging method, including: arranging a passive component on the backside of a first die; fixing a conductive column, a second die, and the first die with the passive component fixed on On the carrier board, the active surfaces of the first die and the second die face the carrier board, and the conductive pillars are arranged on the peripheral side of the first die; on the first die, the second die forming a first redistribution layer over the die and the conductive pillar, the first redistribution layer electrically connecting the electrical connection point of the passive component and the conductive pillar; removing the carrier plate; and close to the A second redistribution layer is provided on one side of the active surface of the first bare chip and the second bare chip, and the second redistribution layer is electrically connected to the bonding pad located on the active surface of the first bare chip and the second bare chip. active side pads and the conductive pillars.

At least one embodiment of the present disclosure provides a semiconductor package structure, including: a first die including a first active surface and a first back surface disposed opposite to each other, the first active surface is provided with a first pad; a second The bare chip includes a second active surface and a second back surface arranged opposite to each other, the second active surface is provided with a second pad, and faces the same direction as the first active surface; a passive component is arranged on the first active surface. a back surface; a conductive column disposed on the peripheral side of the first die; a first redistribution layer disposed on the first back surface and electrically connecting the passive component to the conductive column; and a second redistribution layer A redistribution layer, the second redistribution layer electrically connects the conductive post to the first pad and/or the second pad. Wherein, the sum of the thickness of the first die and the thickness of the passive component is less than the height of the conductive pillar.

The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects: by fixing the passive component on the backside of the first die, the first die and the passive component are stacked in a vertical direction, and the At the same time, a functional circuit in which the first bare chip, the second bare chip and the conductive column are electrically connected is formed by using the conductive post, the first redistribution layer and the second redistribution layer; through the above arrangement, the volume reduction of the semiconductor package structure is realized. Small and compact structure; at the same time, at least one first die and a second die are arranged in the semiconductor package structure, which can form different functional circuits. By changing the number of the first die and the second die and their electrical connection relationship , a variety of semiconductor packaging structures with specific functions can be obtained.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

FIG. 1 shows a schematic cross-sectional structure diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 2 shows a simplified schematic flow chart of a semiconductor packaging method according to an embodiment of the present disclosure.

FIG. 3 shows another schematic cross-sectional structure diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 4 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 5 shows another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 6 shows another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 7 shows another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 8 shows a schematic cross-sectional structure diagram of a carrier plate and a metal plate according to an embodiment of the present disclosure.

FIG. 9 shows a schematic cross-sectional structure diagram of a carrier board and conductive pillars according to an embodiment of the present disclosure.

FIG. 10 shows yet another schematic cross-sectional structure diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 11 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 12 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 13 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 14 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 15 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 16 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

FIG. 17 shows yet another cross-sectional structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

Description of reference numerals

Semiconductor packaging structure 1 Semiconductor wafer 2 First bare chip 10 First backside 1001

The first active surface 1002 The first pad 1003 The second die 13 The second backside 1301

The second active surface 1302 The second pad 1303 The conductive column 20 The metal sheet 23

Passive 30 Inductor 31 First redistribution layer 40 First conductive trace 41

first conductive medium 42 second redistribution layer 50 second conductive trace 51 second conductive medium 52

protective layer 60 protective layer opening 61 conductive bump 62 plastic encapsulation layer 70

carrier plate 81 support plate 82 first dielectric layer 91 first opening 71

second dielectric layer 92 third dielectric layer 93

detailed description

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this disclosure. Rather, they are merely examples of means consistent with some aspects of the present disclosure, as recited in the appended claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. As used in this disclosure and in the claims, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Similarly, "a" or "an" and other similar words do not denote a quantitative limitation, but denote that there is at least one, and if only "a" is referred to, it will be specified separately. "Plural" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and/or "upper" are for convenience of description and are not limited to one location or one spatial orientation. Words like "include" or "include" mean that the elements or items appearing before "including" or "including" cover the elements or items listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The features of the embodiments described below may be combined with each other without conflict.

According to various embodiments of the present disclosure, a semiconductor packaging method is provided. The semiconductor packaging method can be used for a semiconductor packaging structure, and the semiconductor packaging structure is a chip packaging body. The conductor package structure can be applied to electronic equipment, such as mobile phones, computers and the like.

As shown in FIG. 1 , the passive component 30 is disposed on the first back surface 1001 of the first die 10 , so that the passive component 30 is fixedly connected to the first back surface 1001 of the first die 10 . The first active surface 1002 of the first die 10 and the second active surface 1302 of the second die 13 are oriented in the same direction, and the conductive pillars 20 are disposed on the peripheral side of the first die 10 . A first redistribution layer 40 is disposed above the first die 10 , the second die 13 and the conductive pillar 20 , and the first redistribution layer 40 is connected to the electrical connection point of the passive component 30 and the conductive pillar 20 . A second redistribution layer 50 is disposed on the side close to the first active surface 1002 of the first die 10 and the second active surface 1302 of the second die 13 , and the second redistribution layer 50 is connected to the first die 10 The first bonding pad 1003 and the conductive pillar 20 of the first active surface 1002 of the second die 13 and/or the second bonding pad 1303 and the conductive pillar 20 of the second active surface 1302 of the second die 13 are connected. In one embodiment of the present disclosure, the first redistribution layer 40 is connected to the first end 21 of the conductive pillar 20 , and the second redistribution layer 50 is connected to the second end 22 of the conductive pillar. In other words, the electrical connection point of the passive element 30 is electrically connected to the first end 21 , the first solder pad 1003 of the first active surface 1002 of the first die 10 and the second solder pad of the second active surface 1302 of the second die 13 The pad 1303 is electrically connected to the second end 22 . The first end 21 and the second end 22 are disposed opposite to each other along the height direction (vertical direction H) of the conductive column 20 .

It should be noted that, the first active surface 1002 of the first die 10 and the second active surface 1302 of the second die 13 may also be referred to as front surfaces. The first active surface 1002 of the first die 10 and the first back surface 1001 of the first die 10 are arranged opposite to each other, and the second active surface 1302 of the second die 13 and the second back surface 1301 of the second die 13 are arranged opposite to each other, The surface of the first die 10 provided with the first bonding pads 1003 is used as the first active surface 1002 , and the surface of the second die 13 with the second bonding pads 1303 is used as the second active surface 1302 . The first pad 1003 and the second pad 1303 are configured to be electrically connected to the outside world.

The semiconductor package structure 1 of the present disclosure fixes the passive component 30 on the back surface 1001 of the first die 10 , so that the first die 10 and the passive component 30 are stacked in the vertical direction H, and the space in the vertical direction is fully and reasonably utilized. Through the above arrangement, the volume of the semiconductor package structure 1 is reduced and the structure is compact. Meanwhile, in the semiconductor package structure 1 of the present disclosure, the conductive pillars 20 are arranged on the peripheral side of the first die 10 , the first redistribution layer 40 electrically connected to the passive component 30 is arranged, and the first redistribution layer 40 is arranged with the first die 10 . An active surface 1002 is electrically connected to the second redistribution layer 50 of the second active surface 1302 of the second die 13 , so as to realize the electrical connection between the first die 10 and the passive component 30 . Furthermore, by arranging the conductive pillars 20 , the first redistribution layer 40 and the second redistribution layer 50 , the electrical connection point of the passive element 30 is drawn out so as to be connected to the outside world. Finally, a functional circuit in which the first die 10 , the second die 13 and the conductive pillars 20 are electrically connected is formed. By arranging at least one first die 10 and a second die 13 in the semiconductor package structure 1 , different functional circuits can be formed, thereby obtaining the semiconductor package structure 1 with specific functions. Through different combinations (setting different numbers of the first die 10 and the second die 13 in the semiconductor packaging structure 1, and changing their electrical connection relationship), various semiconductor packaging structures 1 with specific functions can be obtained, Thus, the functions of the semiconductor packaging structure 1 are enriched.

Hereinafter, a semiconductor packaging method according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 2 to 17 .

FIG. 2 shows a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in FIG. 2, the semiconductor packaging method includes:

Step S100 : disposing the passive element 30 on the back surface 1001 of the first die 10 .

Step S200 : Fix the conductive pillar 20 , the second die 13 and the first die 10 with the passive component 30 fixed on the carrier board 81 , the first active surface 1002 of the first die 10 faces the carrier board 81 , and the second die 10 faces the carrier board 81 . The second active surface 1302 of the die 13 faces the carrier board 81 , and the conductive pillars 20 are disposed on the peripheral side of the first die 10 . The carrier board 81 plays the role of positioning and supporting the conductive pillars 20 , the second die 13 , and the first die 10 on which the passive component 30 is fixed. At the same time, the surface on which the device is fixed on the carrier board 81 can form a flat surface, which is favorable for subsequent wiring, for example, the setting of the second re-wiring layer 50 .

Step S300 : forming a first redistribution layer 40 over the first die 10 , the second die 13 and the conductive pillars 20 , and the first redistribution layer 40 is connected to the passive element 30 and the first end 21 of the conductive pillars 20 . By disposing the first redistribution layer 40 , the electrical connection between the passive element 30 and the conductive pillar 20 is realized.

Step S400 : removing the carrier plate 81 . The carrier plate 81 is removed to expose the second ends 22 of the conductive pillars 20 and the bonding pads 1003 of the first die 10 .

Step S500 : a second redistribution layer 50 is provided on one side of the first active surface 1002 of the first die 10 and the second active surface 1302 of the second die 13 , and the second redistribution layer 50 will be located on the first die The first bonding pad 1003 on the first active surface 1002 of the second die 10 and the second bonding pad 1303 on the second active surface 1302 of the second die 13 are connected to the second end 22 of the conductive pillar 20 . By disposing the second redistribution layer 50 , the electrical connection between the first pad 1003 of the first die 10 and the conductive pillar 20 is realized. Considering that the first end 21 of the conductive pillar 20 is electrically connected to the passive component 30 and the second end 22 is electrically connected to the first pad 1003 of the first die 10 , the passive component 30 and the first pad of the first die 10 are realized. 1003 Electrical connection.

It should be noted that: in other embodiments, the steps of the corresponding methods are not necessarily performed in the order shown and described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. describe.

In an embodiment of the present disclosure, step S100: disposing the passive component 30 on the first back surface 1001 of the first die 10, including the following steps:

Step S110 : coating a thermosetting material on the first back surface 1001 of the first die 10 to form a thermosetting material layer. The thermosetting materials include organic polymers, organic polymer composites, polyimide (PI), epoxy resin, Ajinomoto buildup film (ABF) and polybenzoxazole (PBO) one or more of etc. When the thermosetting material is heated below the curing temperature of the thermosetting material, its fluidity becomes stronger, and when the thermosetting material is heated above the curing temperature of the thermosetting material, the molecules of the thermosetting material will undergo cross-linking reaction, and the thermosetting material will be cured. . The cured thermoset material can adapt to chemical cleaning, grinding, etc. The thermosetting material layer may be formed on the backside of the first die 10 by means of lamination, coating, printing, molding, or the like.

Step S120 : first heating the thermosetting material layer to reduce the viscosity of the thermosetting material layer, and applying the passive component 30 to the first back surface of the first die 10 through the thermosetting material layer 1001's intended location. Since the viscosity of the thermally-curable material layer is first reduced after the first heating is performed on the thermally-curable material layer, the thermally-curable material layer has strong fluidity at this time. Therefore, the passive element 30 is placed at a predetermined position close to the first backside 1001 of the first die 10 , and then pressure is applied to make the original position between the passive element 30 and the first backside 1001 of the first die 10 . The initially heated thermosetting material is squeezed out. In this way, the passive component 30 can be fixed to a predetermined position of the first back surface 1001 of the first die 10 through the thermal curing material layer by performing the first heating on the thermal curing material layer.

Step S130 : performing a second heating on the thermosetting material layer, the thermosetting material layer is cured by heat to form a first dielectric layer, and the passive member 30 is fixed on the first bare metal layer along with the curing of the thermosetting material layer. The first backside 1001 of the sheet 10 . With the second heating of the thermosetting material layer, the thermosetting material layer is thermally cured to form a first dielectric layer, and as the thermosetting material is cured, the passive member 30 is fixed to the first die 10 1001 of the first backside.

At this time, structural diagrams of the formed semiconductor package structure are shown in FIG. 3 and FIG. 4 .

It should be noted that the time and temperature of the first heating for the thermosetting material are determined by the properties of the thermosetting material, and generally, the temperature of the first heating is lower than the curing temperature of the thermosetting material. According to the rheological characteristics of the thermosetting material during curing, the viscosity of the thermosetting material decreases as the temperature increases, but when the temperature rises above the curing temperature, the molecules of the thermosetting material decrease cross-linking, thereby increasing the viscosity. In order to ensure the fluidity of the thermosetting material, the first heating temperature is selected to be lower than the curing temperature.

After the passive member 30 is applied to the predetermined position of the first back surface 1001 of the first die 10, the temperature may be raised to the curing temperature of the thermal curing material or above, and the thermal curing material layer is subjected to a second Heating causes the thermosetting material to be completely cured to form a first dielectric layer. The curing thermodynamic properties of different materials are different. The heating time is determined by the properties of the thermosetting material, the second heating temperature is a certain temperature higher than the curing temperature, and the heating time is the time required for the thermosetting material to be completely cured at this temperature. Generally speaking, heating The higher the temperature, the shorter the time required for the material to fully crosslink, ie the shorter the curing time.

In an embodiment of the present disclosure, the first heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees. The second heating time is 1 hour to 4 hours, and the temperature is 190 to 200 degrees.

In some embodiments of the present disclosure, the height of the first dielectric layer 91 is equal to the height of the passive element 30 , so that the electrical connection points of the passive element 30 are exposed. Alternatively, in some embodiments of the present disclosure, the height of the first dielectric layer 91 is greater than the height of the passive device 30 . Then, the step of disposing the passive component 30 on the back surface 1001 of the first die 10 further includes step 140 : thinning the first dielectric layer 91 to expose the surface of the passive component 30 away from the first die 10 . Through processes such as thinning, the height of the first dielectric layer 91 is reduced, so that the electrical connection points of the passive components 30 are exposed, and the process is simple. At the same time, by reducing the height of the first dielectric layer 91 , the thickness of the final semiconductor package structure 1 can be reduced, thereby further achieving the beneficial effect of reducing the overall occupied space. Alternatively, the height of the first dielectric layer 91 can always be greater than the height of the passive element 30, so that the passive element 30 is wrapped. In the subsequent steps, via holes can be provided in the first dielectric layer 91 to expose the passive element The electrical connection point of 30 is convenient to electrically connect the passive component 30 and the first redistribution layer 40 .

It should be noted that the passive element 30 may be a capacitor, a resistor, or an inductor, or the like. When the passive component 30 is an inductor, the first dielectric layer 91 may not be additionally provided to fix it. The inductance 31 (shown in FIG. 5 and FIG. 6 ) that can be converted into magnetic energy and stored on the back surface 11 of the first die 10 can be formed by the following steps: first, the first die 10 is formed on the first die 10 by sputtering. A seed layer (not shown) is formed on the back side 11 of the surface, and the seed layer can be a Cu thin film, or can be a seed layer including a Ti/Cu thin film; after that, a metal layer is formed on the seed layer by means of electroplating. The material can be copper; finally, by spinning photoresist (spining photo material), exposing (exposing), developing (developing), stripping (srtiping), etching (etching), on the first bare chip 10 The backside 11 forms an inductor 31 .

After performing step S100 and before performing step S200, the semiconductor packaging method further includes:

Step S201 : forming a protective layer 60 on the first active surface 1002 of the first die 10 .

Step S202 : forming a protective layer opening 61 on the protective layer 60 to expose the first pad 1003 of the first die 10 . The number of the protective layer openings 61 may be one or more, and each protective layer opening 61 corresponds to at least the first pad 1003 of the first die 10 or a circuit drawn from the first pad 1003 , so that the first bare The first bonding pads 1003 on the first active surface 1002 of the chip 10 or the lines drawn from the first bonding pads 1003 are exposed from the protective layer opening 61 . Through the above arrangement, it is convenient for the second redistribution layer 50 to be electrically connected to the first pad 1003 through the protective layer opening 61 when the second redistribution layer 50 is formed.

The protective layer 60 may be made of a laser reactive material or a photosensitive material. In the case where the protective layer 60 is formed by using a laser reactive material, the protective layer opening 61 may be formed by laser patterning. In the case of using a photosensitive material to form the protective layer 60, the protective layer opening 61 can be formed by patterning by photolithography. The shape of the protective layer opening 61 can be round, and of course can also be other shapes such as oval, square and so on.

It should be noted that, before dicing the semiconductor wafer 2 into a plurality of first dies 10 , a protective layer 60 may be formed on the active surface 12 of the semiconductor wafer 2 and a protective layer opening 61 may be formed in the protective layer 60 , and/or, the passive element 30 is fixed to the backside 11 of the semiconductor wafer. At this time, the resulting structure is shown in FIGS. 3 and 5 . After that, the semiconductor wafer is cut along the dicing lines to obtain the first bare chip 10 with the protective layer 60 and the protective layer opening 61 formed on the plurality of active surfaces 1002 and the passive element 30 fixed on the back surface 1001. At this time, The resulting structures are shown in Figures 4 and 6. The cutting process can be mechanically cut or laser cut.

Alternatively, if the process allows, after the semiconductor wafer 2 is cut into the first die 10 , the protective layer 60 and the protective layer opening 61 may be formed on the first active surface 1002 of each first die 10 . , and a passive component is fixed on the first back surface 1001 of each first die 10 . Alternatively, the protective layer 60 may be formed on the active surface 12 of the semiconductor wafer 2 before the semiconductor wafer 2 is diced into a plurality of first dies 10, after which the semiconductor wafer 2 is diced, and finally, on the active surface 12 of the semiconductor wafer 2. A protective layer opening 61 is formed on the protective layer 60 of each first die 10 . The specific process steps can be selected according to the actual situation.

In some embodiments of the present disclosure, before disposing the passive device 30 on the first back surface 1001 of the first die 10 , the protective layer 60 may be formed on the first active surface 1002 of the first die 10 and the protective layer may be formed on the first active surface 1002 of the first die 10 A protective layer opening 61 is formed in 60 .

Then, after step S201 and step S202 are performed, when step S200 is performed, the protective layer 60 needs to be fixed on the carrier board 81 . In other words, when the first die 10 is fixed to the carrier board 81 , the protective layer 60 is in contact with the carrier board 81 . Step S200 : Fixing the conductive column 20 and the first die 10 with the passive component 30 fixed on the carrier board 81 , including: disposing the conductive column 20 on the carrier plate 81 , and arranging and fixing the passive component 30 on the carrier plate 81 10 of the first die. At this time, the formed structure is as shown in FIG. 7 .

In one embodiment of the present disclosure, the metal sheet 23 may be fixed on the carrier plate 81 first. At this time, the obtained structure is as shown in FIG. 8 . Then, the metal sheet 23 is processed by processes such as photolithography and etching, so as to obtain the conductive pillars 20 arranged at intervals. At this time, the obtained structure is as shown in FIG. 9 . Of course, in other embodiments, the metal sheet can also be obtained by deposition. Alternatively, the metal conductive pillars 20 with a columnar structure may be formed first, and then the conductive pillars 20 are fixed on the carrier board 81 by means of bonding. After that, the first die 10 is fixed on the carrier board 81 , and the conductive pillars 20 are arranged on the peripheral side of the first die 10 . Of course, in other embodiments, the first die 10 may also be fixed on the carrier board 81 first. After that, the conductive pillars 20 are fixed at the corresponding positions.

The conductive pillars 20 and the protective layer 60 fixed on the first die 10 are mounted on the carrier board 81 through an adhesive layer. The adhesive layer can be made of an easily peelable material, so that the carrier plate 81 and/or the conductive post 20 and the protective layer 60 can be peeled off in the subsequent process. In some embodiments of the present disclosure, the adhesive layer may adopt a two-layer structure, and the adhesive layer includes a thermal separation material layer and a die attach layer. The thermal separation material layer is adhered to the carrier plate 81 , and loses its viscosity when heated, so that it can be peeled off from the carrier plate 81 . The die attach layer adopts an adhesive material layer, which can be pasted on the protective layer 60 and the conductive post 20 . After the protective layer 60 and the conductive pillars 20 are peeled off from the carrier 81 , the die attach layer on the surfaces of the protective layer 60 and the conductive pillars 20 may be removed by chemical cleaning. In some embodiments of the present disclosure, the adhesive layer may be formed on the carrier board 81 by means of lamination, printing, or the like.

After performing step S100 and before performing step S300, the semiconductor packaging method further includes:

Step S301 : forming a plastic encapsulation layer 70 on the carrier board 81 , and the plastic encapsulation layer 70 wraps the conductive pillar 20 , the protective layer 60 , the passive component 30 and the first die 10 . At this time, the formed structure is as shown in FIG. 10 .

By arranging the plastic encapsulation layer 70 , the conductive pillars 20 and the first die 10 on which the passive component 30 and the protective layer 60 are fixed are connected to form a whole. There is a certain distance between the conductive pillars 20 and the first die 10 , so that at least part of the plastic encapsulation layer 70 can enter the gap between the two, so as to limit the position of the conductive pillars 20 and the first die 10 . At the same time, the plastic sealing layer 70 is formed above the carrier board 81 , that is, the plastic sealing layer 70 is covered on the carrier board 81 . At this time, the lower surface of the plastic encapsulation layer 70, the lower surface of the conductive pillar 20 and the lower surface of the protective layer 60 are flush to form a plane structure. After the carrier plate 81 is peeled off, the process can be continued on the reconstructed plane structure. Rewiring and packaging, in particular, facilitate subsequent formation of the second redistribution layer 50 thereon.

The material of the plastic encapsulation layer 70 may be polymer, resin or polymer composite material. In an embodiment of the present disclosure, the plastic sealing layer 70 may be formed by laminating epoxy resin film or Ajinomoto buildup film (ABF), or may be formed by injection molding an epoxy resin compound. molding), compression molding (Compression molding) or transfer molding (Transfer molding).

Step S302 : The plastic sealing layer 70 is thinned to expose the upper surfaces of the conductive pillars 20 . At this time, the formed structure is as shown in FIG. 11 .

In some embodiments of the present disclosure, the plastic encapsulation layer 70 is thinned by means of a mechanical mask, so that the first surfaces 21 of the conductive pillars 20 are exposed. Through the above arrangement, the overall thickness of the protective layer 60 and the first die 10 is reduced, thereby reducing the thickness of the final semiconductor package structure 1 , and further achieving the beneficial effect of reducing the space occupied by the semiconductor package structure 1 .

It should be noted that the sum of the thickness of the protective layer 60, the thickness of the first die 10 and the thickness of the passive component 30 is taken as the first height value H1, the height of the conductive pillar 20 is the second height value H2, the second height The value H2 is greater than the first height value H1 (shown with reference to FIG. 11 ).

Step S303 : forming a first opening 71 on the plastic sealing layer 70 , and the first opening 71 exposes the electrical connection point of the passive element 30 . By controlling the magnitude relationship between the first height value H1 and the second height value H2 , it is beneficial to form the first opening 71 on the plastic sealing layer 70 . At this time, the formed structure is as shown in FIG. 12 .

In some embodiments of the present disclosure, the first openings 71 are formed in the plastic encapsulation layer 70 through a laser processing process, so that the electrical connection points of the passive components 30 are exposed. In the subsequent process of forming the first redistribution layer 40 , the first redistribution layer 40 can enter the first opening 71 to achieve precise connection.

After the first opening 71 is formed, step S300 is performed: forming a first redistribution layer 40 over the first die 10 and the conductive pillar 20 . At this time, the first redistribution layer 40 is electrically connected to the electrical connection point of the passive element 30 through the first opening 71 . At this time, the resulting structure is as shown in FIG. 13 .

The first redistribution layer 40 includes a first conductive trace 41 and a first conductive medium 42 . The first conductive traces 41 and the first conductive medium 42 are electrically connected. The first conductive traces 41 are formed above the plastic encapsulation layer 70 and are electrically connected to one end 21 of the conductive pillars 20 . The first conductive medium 42 is disposed in the first opening 71 and is electrically connected to the passive element 30 . The first redistribution layer 40 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. During the deposition process, part of the metal material may enter the first opening 71 and form the first conductive medium 42 . Another part of the metal material is deposited over the plastic encapsulation layer 70 , and the first conductive traces 41 are finally formed through a patterning process.

Before performing step S400 , the following step S401 is also performed: forming a second dielectric layer 92 on the first redistribution layer 40 and the plastic sealing layer 70 . The second dielectric layer 92 covers at least the first redistribution layer 40 , that is, the second dielectric layer 92 is disposed around and above the first conductive traces 41 to protect the first redistribution layer 40 . At this time, the resulting structure is as shown in FIG. 14 .

The second dielectric layer 92 is made of insulating materials, such as organic polymers, organic polymer composite materials, PI polyimide, epoxy resin, Ajinomoto buildup film (ABF) and polybenzoxazole ( One or more of Polybenzoxazole, PBO) etc. Optionally, the material of the second dielectric layer 92 is selected to be insulating and capable of adapting to chemical cleaning, grinding, and the like. The second dielectric layer 92 may be formed on the first die 10 , the first redistribution layer 40 and the molding layer 70 by means of lamination, coating, printing, molding, or the like.

In an embodiment of the present disclosure, when step S400 is performed, since the adhesive layer between the carrier board 81 and the protective layer 60 , the conductive pillar 20 and the plastic sealing layer 70 on the first die 10 is a thermal separation film, it can be By heating, the viscosity of the adhesive layer is reduced after heating, so that the carrier plate 81 can be peeled off. By heating the adhesive layer to peel off the carrier plate 81 , the damage to the protective layer 60 , the conductive pillars 20 and the plastic sealing layer 70 can be minimized during the peeling process. In some embodiments of the present disclosure, the carrier plate 81 may be peeled off mechanically. At this time, the resulting structure is as shown in FIG. 15 .

In the embodiment of the present disclosure, after the carrier board 81 is peeled off, the lower surface of the plastic encapsulation layer 70 facing the carrier board 81 , the second end surface of the conductive pillar 20 , the lower surface of the protective layer 60 and the lower surface of the protective layer 60 are exposed. solder pads. The lower surface of the plastic encapsulation layer 70 , the second end surface of the conductive post 20 and the lower surface of the protective layer 60 may also be attached with a die attach layer, which can be removed by chemical means. After the adhesive layer is completely removed, if the encapsulation material is infiltrated between the first die, the second die, the conductive pillar and the carrier during the process of forming the plastic encapsulation layer, the lower surface, the lower surface of the plastic encapsulation layer 70, The second end surface of the conductive pillar 20 and the lower surface of the protective layer 60 are chemically cleaned or ground to make the surface flat, which is beneficial for subsequent wiring, especially for the wiring of the second redistribution layer 50 .

Before step S500 is performed, the following step S501 is also performed: disposing the support plate 82 above the second dielectric layer 92 . By arranging the support plate 82 , the whole structure can be supported, which is beneficial to the formation of the second redistribution layer 50 . At this time, the resulting structure is as shown in FIG. 16 .

It should be noted that: in other embodiments, the steps of the corresponding methods are not necessarily performed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. describe. In some embodiments of the present disclosure, step 400 : removing the carrier plate 81 is performed first; then, step 501 : disposing the support plate 82 over the second dielectric layer 92 is performed. In some embodiments of the present disclosure, step 501 : disposing the support plate 82 above the second dielectric layer 92 may also be performed first; then, step 400 : removing the carrier plate 81 is performed. In some embodiments of the present disclosure, the support plate 82 is not disposed over the second dielectric layer 92 .

After the carrier plate 81 is removed, the protective layer openings 61 of the protective layer 60 and the second end surfaces 22 of the conductive pillars 20 are exposed. Then, when step S500 is performed, the second redistribution layer 50 is electrically connected to the bonding pad of the first die 10 through the protective layer opening 61 .

As shown in FIG. 17 , in one embodiment of the present disclosure, the second redistribution layer 50 includes a second conductive trace 51 and a second conductive medium 52 . The second conductive traces 51 and the second conductive medium 52 are electrically connected. The second conductive medium 52 is formed on a side of the protective layer 60 away from the first die 10 and is electrically connected to one end 22 of the conductive pillar 20 . The second conductive medium 52 penetrates through the protective layer opening 61 and is electrically connected to the bonding pad of the first die 10 . The second redistribution layer 50 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. During the deposition process, at least part of the metal material enters the protective layer opening 61 to form the second conductive medium 52 . Another part of the metal material is deposited on the surface of the protective layer 60 , extends to one end 22 of the conductive pillar 20 , and is subjected to a patterning process to finally form the second conductive trace 51 .

In one embodiment of the present disclosure, the semiconductor packaging method further includes:

Step S600 : forming conductive bumps 62 on the surface of the second redistribution layer 50 away from the first die 10 and the second die 13 . The resulting structure is shown in FIG. 17 .

In one embodiment of the present disclosure, the shape of the conductive bumps 62 is circular. In other embodiments of the present disclosure, the conductive bumps 62 may have other shapes such as rectangles, squares, etc., and the conductive bumps 62 are electrically connected to the second redistribution layer 50 . For example, the conductive bumps 62 may be formed on the side of the second redistribution layer 50 away from the first die 10 by photolithography or electroplating.

Step S700 : forming a third dielectric layer 93 on the front surface of the first die, the third dielectric layer 93 covering at least the second redistribution layer 50 and wrapping the peripheral sides of the conductive bumps 62 , so that the conductive bumps 62 The end away from the first die 10 is exposed. At this time, the semiconductor package structure 1 shown in FIG. 1 is formed. It should be noted that the support plate 82 in the semiconductor package structure 1 in Fig. 1 has been removed. The removal of the support plate 82 may be synchronized with the formation of the third dielectric layer 93 . Alternatively, the support plate 82 may be removed before the third dielectric layer 93 is formed. Alternatively, the support plate 82 may also be removed in a subsequent step.

The third dielectric layer 93 is made of an insulating material selected from the group consisting of organic polymers, organic polymer composite materials, PI polyimide, epoxy resin, ABF (Ajinomoto buildup film) and PBO (Polybenzoxazole) group. In one embodiment of the present disclosure, the insulating material for forming the third dielectric layer 93 can be adapted to processes such as chemical cleaning and grinding. The third dielectric layer 93 may be formed on the plastic encapsulation layer 70 , the protective layer 60 , the second redistribution layer 50 and the conductive bumps 62 by means of lamination, coating, printing, molding, etc. superior.

The conductive bumps 62 and the second redistribution layer 50 form a whole, the overall height of the conductive bumps 62 and the second conductive traces 51 is the third height value H3, and the height of the third dielectric layer 93 is the fourth height value H4. In some embodiments of the present disclosure, the fourth height value H4 may be equal to the third height value H3. Then, one end of the conductive bump 62 away from the first die 10 may be exposed from the third dielectric layer 93 and used for communication with the outside world. Alternatively, in some embodiments of the present disclosure, the fourth height value H4 may also be greater than the third height value H3. In other words, the third dielectric layer 93 covers the conductive bumps 62 and the second conductive traces 51 , and the ends of the conductive bumps 62 remote from the first die 10 are not exposed. Subsequently, a thinning process needs to be performed on the third dielectric layer 93 , so that the height of the third dielectric layer 93 is reduced until the ends of the conductive bumps 62 away from the first die 10 are exposed.

In some embodiments of the present disclosure, the semiconductor packaging method further includes the following steps:

Step S800 : forming a surface treatment layer 6201 on the surfaces of the exposed conductive bumps 62 . By disposing the surface treatment layer 6201 on the surface of the conductive bump 62, the conductive bump 62 can be protected from being oxidized.

In some embodiments of the present disclosure, a semiconductor packaging method includes the steps of:

Step S900 : cutting the entire package structure into a plurality of package bodies, ie, a plurality of semiconductor package structures 1 , by means of laser or mechanical cutting. The structure of the semiconductor package structure 1 obtained after step S900 is performed is shown in FIG. 1 .

FIG. 1 is a schematic structural diagram of a semiconductor package structure 1 obtained by using the above-mentioned semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in FIG. 1 , the semiconductor package structure 1 includes a first die 10 , a second die 13 , passive components 30 , conductive pillars 20 , a first redistribution layer 40 , a second redistribution layer 50 and a protection layer 60 .

The first die 10 includes a first active surface 1002 and a first back surface 1001 disposed opposite to each other, and a first bonding pad 1003 is disposed on the first active surface 1002 . The second die 13 includes a second active surface 1302 and a first back surface 1001 disposed opposite to each other, and a second bonding pad 1303 is disposed on the second active surface 1302 . The passive element 30 is disposed on the first back surface 1001 of the first die 10 , and the electrical connection point of the passive element 30 is disposed on a side away from the first die 10 . The conductive pillars 20 are disposed on the peripheral side of the first die 10 . The electrical connection point of the passive element 30 is electrically connected to the conductive pillar 20 through the first redistribution layer 40 , so as to realize the electrical connection between the passive element 30 and the conductive pillar 20 . The first bonding pad 1003 and/or the second bonding pad 1303 are electrically connected to the conductive pillar 20 through the second redistribution layer 50 , so as to realize the electrical connection between the first bonding pad 1003 and/or the second bonding pad 1303 and the conductive pillar 20 . Since the conductive pillar 20 is also electrically connected to the passive element 30 , the passive element 30 and the first pad 1003 of the first die 10 can be electrically connected by disposing the first redistribution layer 40 and the second redistribution layer 50 . At the same time, the electrical connection point of the passive component 30 can be connected to an external circuit through the first redistribution layer 40 and the conductive pillar 20 and the second redistribution layer 50, and the first pad 1003 of the first die 10 can pass through the second redistribution layer. 50 is connected to an external circuit. The protective layer 60 is disposed on the first active surface 1002 of the first die 10 . Surfaces of the protective layer 60 away from the first die 10 and the second die 13 are flush with the lower surfaces of the conductive pillars 20 . A protective layer opening 61 is provided on the protective layer 60 , and the protective layer opening 61 exposes the first pad 1003 of the first die 10 and the second pad 1303 of the second die 13 , so that the first pad 1003 is exposed. and the second pad 1303 may be exposed through the protective layer opening 61 so as to communicate with the outside world. The second wire trace is electrically connected to the first pad 1003 and/or the second pad 1303 through the protective layer opening 61, thereby realizing the second redistribution layer 50 and the first pad 1003 and/or the second pad 1303 electrical connections.

The sum of the thickness of the protective layer 60, the thickness of the first die 10 and the thickness of the passive component 30 is taken as the first height value H1; the height of the conductive pillar 20 is the second height value H2, and the second height value H2 is greater than or equal to the first height value H2. A height value H1.

In the semiconductor package structure 1 according to the embodiment of the present disclosure, the passive component 30 is fixed on the back surface 1001 of the first die 10 , so that the first die 10 and the passive component 30 are stacked in the vertical direction H, and the vertical The space in the straight direction H. Through the above arrangement, the volume of the semiconductor package structure 1 is reduced and the structure is compact. Meanwhile, the semiconductor package structure 1 according to the embodiment of the present disclosure disposes the conductive pillars 20 on the peripheral side of the first die 10 , and provides the first redistribution layer 40 electrically connected to the passive element 30 and the first die. The second redistribution layer 50 is electrically connected to the first active surface 1002 of the 10 , so as to realize the electrical connection between the first die 10 and the passive component 30 . Furthermore, by arranging the conductive pillars 20 , the first redistribution layer 40 and the second redistribution layer 50 , the electrical connection point of the passive element 30 is drawn out so as to be connected to the outside world. Finally, a functional circuit in which the first die 10 and the conductive pillars 20 are electrically connected is formed. By arranging at least one first die 10 and a second die 13 in the semiconductor package structure 1 , different functional circuits can be formed, thereby obtaining the semiconductor package structure 1 with specific functions.

The second redistribution layer 50 includes a second conductive trace 51 and a second conductive medium 52 . The second conductive traces 51 and the second conductive medium 52 are electrically connected. The second conductive trace 51 is formed on the side of the protective layer 60 away from the first die 10 and the second die 13 , and is electrically connected to one end 22 of the conductive pillar 20 , thereby realizing the second redistribution layer 50 and the conductive pillar 20 electrical connection. The second conductive medium 52 penetrates the protective layer opening 61 and is electrically connected to the bonding pads of the first die 10 and the second die 13 , so as to realize the connection between the second redistribution layer 50 and the first die 10 and the second die 13 The bonding pads are electrically connected, thereby realizing the electrical connection between the bonding pads and the conductive pillars 20 .

The semiconductor package structure 1 further includes a first dielectric layer 91 , a second dielectric layer 92 , a plastic sealing layer 70 , conductive bumps 62 and a third dielectric layer 93 .

The first dielectric layer 91 is disposed on the back surface 1001 of the first die 10 and wraps around the peripheral side of the passive element 30 . The passive component 30 is fixedly connected to the first die 10 through the first dielectric layer 91 . The first dielectric layer 91 is configured to secure the passive device 30 on the first back surface 1001 of the first die 10 . No passive component is provided on the second back surface 1301 of the second die 13 , so the first dielectric layer 91 is not provided on the second back surface 1303 of the second die 13 .

The second dielectric layer 92 is disposed above the first redistribution layer 40 and the plastic encapsulation layer 70 and at least partially covers the first redistribution layer 40 . Through the above arrangement, the first redistribution layer 40 can be protected to prevent disconnection, corrosion, oxidation and other phenomena.

At least part of the plastic packaging layer 70 is disposed on the peripheral sides of the first die 10 , the second die 13 and the conductive pillar 20 to fixedly connect the plastic packaging layer 70 , the first die 10 and the second die 13 so as to connect them form a whole. In addition, at least part of the plastic encapsulation layer 70 is also disposed on the first dielectric layer 91 and the passive component 30 to protect the passive component 30 . When the passive component 30 is the inductor 31 , the first dielectric layer 91 is not provided at this time, and the peripheral side of the inductor 31 is wrapped by the plastic encapsulation layer 70 . When the passive element 30 is an element such as a capacitor or a resistor, the peripheral side of the passive element 30 is fixed by the first dielectric layer 91 , thereby realizing a fixed connection with the first die 10 .

A first opening 71 is provided in the portion of the plastic encapsulation layer 70 located above the passive element 30 , and the first opening 71 exposes the electrical connection point of the passive element 30 .

The first redistribution layer 40 is electrically connected to the electrical connection point of the passive component 30 through the first opening 71 . The first redistribution layer 40 includes a first conductive trace 41 and a first conductive medium 42 . The first conductive traces 41 and the first conductive medium 42 are electrically connected. The first conductive traces 41 are disposed on the surface of the plastic encapsulation layer 70 facing the first back surface 1001 of the first die 10 and are connected to the conductive pillars 20 . The first conductive medium 42 is electrically connected to the electrical connection point of the passive element 30 through the first opening 71 .

The conductive bumps 62 are disposed on a side of the second redistribution layer 50 away from the first die 10 . By arranging the conductive bumps 62 , the bonding pads of the first die 10 and the electrical connection points of the passive components 30 are drawn out to facilitate connection with the outside world.

The third dielectric layer 93 is disposed on the side of the first die 10 , the second die 13 , the protective layer 60 and the second redistribution layer 50 away from the passive component 30 , and wraps around the peripheral side of the conductive bump 62 . Through the above arrangement, the upper surfaces of the conductive bumps 62 are exposed to facilitate electrical connection with the outside world.

The surface of the conductive bump 62 is further provided with a surface treatment layer 6201 , and the surface treatment layer 6201 can protect the conductive bump 62 from being oxidized.

In some embodiments of the present disclosure, the number of the first die 10 in the semiconductor package structure 1 is multiple, and a passive element 30 is disposed above each of the first die 10 . The semiconductor package structure 1 also includes one or more second dies 13 . The second die 13 and the first die 10 are disposed in the same layer. The passive member 30 is not disposed on the backside of the second die 13 . In other words, the passive element 30 is only disposed on the backside of the first die 10 . The thickness of the first die 10 and the second die 13 may be the same, and the structures may also be the same. It can be understood that the die with the passive element 30 disposed on the backside is used as the first die 10 , and the die without the passive element 30 disposed on the backside is taken as the second die 13 .

In some embodiments of the present disclosure, the semiconductor package structure 1 includes at least one first die 10 with a first backside 1001 provided with an inductor 31 , and at least one first die 10 with a backside 1001 provided with a resistor or capacitor (ie, the passive element 30 ). A bare chip 10 further includes at least one second bare chip 13 whose backside 1301 is not provided with passive components 30 . Different functional circuits can be formed by arranging different passive components 30 above the first die 10 and changing the number, position and electrical connection relationship between the first die 10 and the second die 13 in the semiconductor package structure 1 . , thereby obtaining a semiconductor package structure 1 with specific functions. In some embodiments of the present disclosure, the semiconductor package structure 1 may include only the first die 10 but not the second die 13; Capacitors are provided only with inductance, only with resistance, or with only any two of capacitance, inductance and resistance.

It should be noted that, the back surface 11 of one first die 10 may be provided with multiple passive elements 30 of the same type, multiple passive elements 30 of different types, or only one passive element 30 . In addition, the passive component 30 located on the first back surface 1001 of the first die 10 can be electrically connected to the second active surface of the first die 10 through the first redistribution layer 40 , the conductive pillars 20 and the second redistribution layer 50 The first pad 1003 on 1002 is alternatively electrically connected to the first pad 1003 on the active surface 1002 of the other first die 10 , or is electrically connected to the second active surface 1302 of the second die 13 the second pad 1303. The above arrangement enriches the electrical connection relationship between the passive element 30 and different first die 10 and second die 13 , so that different functional circuits can be formed, thereby obtaining a semiconductor package structure 1 with specific functions.

The above descriptions are only exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure in any form. Although the present disclosure has been disclosed above with example embodiments, it is not intended to limit the present disclosure. Any person skilled in the art, Within the scope of not departing from the technical solutions of the present disclosure, when some changes or modifications can be made by using the technical content disclosed above to be equivalent embodiments with equivalent changes, but any content that does not depart from the technical solutions of the present disclosure, according to the technical solutions of the present disclosure Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present disclosure.

Claims

A semiconductor packaging method, comprising:

A passive component is arranged on the backside of the first die;

A conductive column, a second die and a first die with the passive component fixed on the carrier are fixed on the carrier, the active surfaces of the first die and the second die face the carrier, and the conductive column arranged on the peripheral side of the first die;

forming a first redistribution layer over the first die, the second die and the conductive pillar, the first redistribution layer electrically connecting the electrical connection point of the passive component and the conductive pillar;

removing the carrier plate; and

A second redistribution layer is provided on the side close to the active surfaces of the first die and the second die, and the second redistribution layer is electrically connected to the pads, the first redistribution The active side of the two die pads and the conductive pillars.
The semiconductor packaging method according to claim 1, wherein disposing the passive element on the backside of the first die comprises:

Coating a thermosetting material on the back of the first die to form a thermosetting material layer;

The thermosetting material layer is first heated to reduce the viscosity of the first dielectric layer, and the passive component is placed on a predetermined position on the backside of the first die through the first dielectric layer ;

performing a second heating on the thermosetting material layer to cure the thermosetting material layer to form a first dielectric layer, and the passive element is fixed on the backside of the first die by the first dielectric layer; and

The first dielectric layer is thinned to expose the surface of the passive element away from the first die.
The semiconductor packaging method of claim 2, wherein the temperature of the first heating is lower than the curing temperature of the thermosetting material layer, and the temperature of the second heating is equal to or higher than the curing temperature of the thermosetting material layer .
The semiconductor packaging method according to claim 2 or 3, wherein the thermosetting material comprises organic polymer, organic polymer composite material, polyimide, epoxy resin, Ajinomoto build-up film and polybenzoxazole at least one of them.
The semiconductor packaging method according to any one of claims 1 to 4, wherein after the passive member is disposed on the backside of the first die, the conductive pillars, the second die and the Before the first die of the passive component is fixed on the carrier, the semiconductor packaging method further includes:

forming a protective layer on the active side of the first die; and

forming a protective layer opening in the protective layer to expose the first bonding pad exposure of the first die;

Wherein, the sum of the thickness of the first die, the thickness of the passive component and the thickness of the protective layer is less than or equal to the height of the conductive pillar.
The semiconductor packaging method of claim 5, wherein the protective layer is made of one of a laser reflective material and a photosensitive material.
The semiconductor packaging method of any one of claims 1 to 6, wherein before forming a first redistribution layer over the first die, the second die, and the conductive pillars, the The semiconductor packaging method also includes:

A plastic encapsulation layer is formed on the carrier board, and the plastic encapsulation layer wraps the conductive pillar and the protective layer, the passive component and the first die;

thinning the plastic encapsulation layer to expose the upper surface of the conductive post; and

A first opening is formed in the molding layer to expose the electrical connection point of the passive component.
The semiconductor packaging method according to any one of claims 1 to 7, further comprising:

A second dielectric layer is formed on a side of the first redistribution layer away from the first die, and the second dielectric layer covers at least the first redistribution layer.
The semiconductor packaging method of any one of claims 1 to 8, further comprising:

forming conductive bumps on a side of the second redistribution layer remote from the first die and the second die; and

A third dielectric layer on the side of the second redistribution layer away from the first die and the second die, wherein the third dielectric layer at least covers the second redistribution layer and wraps The peripheral side of the conductive bump is exposed, and the end of the conductive bump away from the first die is exposed.
The semiconductor packaging method according to claim 9, further comprising: forming a surface treatment layer on the surfaces of the exposed conductive bumps.
The semiconductor packaging method according to any one of claims 1 to 10, wherein the conductive pillar, the second die, and the first die to which the passive member is fixed are fixed on a thermal separation film. on the carrier.
A semiconductor package structure, comprising:

a first bare chip, comprising a first active surface and a first back surface arranged oppositely, and a first solder pad is arranged on the first active surface;

The second bare chip includes a second active surface and a second back surface arranged opposite to each other, the second active surface is provided with a second pad and faces the same direction as the first active surface;

a passive member, arranged on the first back surface;

a conductive column, disposed on the peripheral side of the first die;

a first redistribution layer disposed on the first back surface and electrically connecting the passive element to the conductive post; and

a second redistribution layer electrically connecting the conductive post to the first pad and/or the second pad;

Wherein, the sum of the thickness of the first die and the thickness of the passive component is less than the height of the conductive pillar.
The semiconductor package structure of claim 12, further comprising a protective layer, the protective layer is disposed on the first active surface and the second active surface, the protective layer is provided with a protective layer opening, exposing The first die and the second die, wherein the sum of the thickness of the first die, the thickness of the passive component and the thickness of the protective layer is less than the height of the conductive pillar.
The semiconductor package structure according to claim 12 or 13, further comprising:

a first dielectric layer, disposed on the first back surface, and fixing the passive component on the first back surface;

The plastic sealing layer covers the first dielectric layer, and at least part of the plastic sealing layer is disposed on the peripheral sides of the first die, the second die and the conductive pillar.
The semiconductor packaging structure of claim 14, wherein a first opening is provided in the plastic packaging layer to expose an electrical connection point of the passive component;

The first redistribution layer includes a first conductive trace and a first conductive medium, the first conductive medium being located in the first opening and electrically connected to the electrical connection point of the passive component, the first conductive medium being located in the first opening and electrically connected to the electrical connection point of the passive component. A conductive trace is electrically connected to the first conductive medium; the first conductive trace is disposed on the surface of the plastic encapsulation layer facing the first back surface, and is electrically connected to the conductive post and the first conductive medium.
14. The semiconductor package structure of claim 13, wherein the second redistribution layer includes a second conductive trace and a second conductive medium, the second conductive medium disposed in the protective layer opening and connected to the The first pad is electrically connected, the second conductive trace is disposed on the surface of the protective layer away from the first die and the second die, and is connected with the conductive post and the second conductive trace dielectric electrical connection.
The semiconductor package structure of claim 12, further comprising:

a conductive bump, disposed on a side of the second redistribution layer away from the first die and the second die;

A third dielectric layer is disposed on the side of the second redistribution layer away from the first die, and at least covers the second redistribution layer and wraps around the peripheral side of the conductive bump.
The semiconductor package structure of claim 12 , wherein the passive component includes at least one of a capacitor, a resistor, and an inductor.
13. The semiconductor package structure of claim 12, wherein the semiconductor package structure comprises at least two first dies; wherein a backside of at least one of the at least two first dies is provided with Inductors, capacitors or resistors are provided on the backs of other first dies among the at least two first dies; or, wherein, at least one of the at least two first dies is provided The passive component on the backside is electrically connected to the first of the other first dies of the at least two first dies through the first redistribution layer, the conductive pillar and the second redistribution layer solder pads.
The semiconductor package structure of claim 12 , wherein the first die and the second die are disposed on the same layer.