CN115966565A - Stacked packaging substrate, chip packaging structure of stacked packaging substrate and preparation method - Google Patents

Abstract

The invention discloses a superposition type packaging substrate, which comprises a first packaging substrate and a second packaging substrate which are mutually conductively jointed, wherein the first packaging substrate comprises a first wiring layer, a first jointing dielectric layer positioned on the lower surface of the first wiring layer and a first jointing conductive column surrounded by the first jointing dielectric layer; the second packaging substrate comprises a second wiring layer, a second bonding dielectric layer and a second bonding conductive pillar, wherein the second bonding dielectric layer is located on the upper surface of the second wiring layer, and the second bonding conductive pillar is surrounded by the second bonding dielectric layer; the first bonding conductive pillar and the second bonding conductive pillar correspondingly form conductive bonding; the first bonding dielectric layer and the second bonding dielectric layer are physically bonded to form a bonding dielectric layer. The invention also discloses a stacked packaging substrate, a chip packaging structure of the stacked packaging substrate and a preparation method thereof. The invention realizes the preparation of the superposed packaging substrate in a chip packaging factory, can effectively improve the chip packaging integration level and has shorter processing period.

Description

Stacked packaging substrate, chip packaging structure of stacked packaging substrate and preparation method

Technical Field

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a stacked packaging substrate, a chip packaging structure of the stacked packaging substrate and a preparation method of the chip packaging structure.

Background

In the advanced packaging process of the chip, the chip needs to be transferred to a chip packaging factory for a packaging process with high wiring density and reliability test, and then transferred to a mounting factory for mounting a packaging substrate with medium wiring density and a PCB (printed circuit board) with low wiring density. In the process, the phenomena of technical communication, process chain belonging to different manufacturers and the like exist between a chip packaging factory and a chip mounting factory, so that the problems of long process cycle, high product processing cost, inflexible chip product design and the like exist in a chip product.

In the advanced packaging process, a relatively small-size packaging process such as wafer scribing, chip pin leading-out, plastic package protection of a chip and the like needs to be completed, and used equipment and auxiliary materials are used for the packaging process in the small size range, such as high wiring density fan-out packaging. After the chip completes the fan-out packaging process with high wiring density, substrate packaging with medium and low wiring density is needed to be respectively carried out, and the density of copper wiring is reduced due to the fact that the line width and the line diameter of the copper wiring in the substrate are large, and the mounting integration level of the chip is low. Moreover, the chips are transferred between a packaging factory and a mounting factory, so that the product reliability risk and the transportation cost in the transfer process are increased, and the packaging process processing period of the chip products is longer.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a stacked packaging substrate, a chip packaging structure and a preparation method thereof, which can improve the chip packaging integration level and shorten the processing period.

A superposition type packaging substrate comprises a first packaging substrate and a second packaging substrate which are mutually conductively jointed, wherein the first packaging substrate comprises a first wiring layer, a first jointing dielectric layer positioned on the lower surface of the first wiring layer and a first jointing conductive column surrounded by the first jointing dielectric layer; the second packaging substrate comprises a second wiring layer, a second bonding dielectric layer and a second bonding conductive pillar, wherein the second bonding dielectric layer is located on the upper surface of the second wiring layer, and the second bonding conductive pillar is surrounded by the second bonding dielectric layer; the first bonding conductive pillar and the second bonding conductive pillar correspondingly form conductive bonding;

the first bonding dielectric layer and the second bonding dielectric layer are physically bonded to form a bonding dielectric layer.

Preferably, the first wiring layer has a higher wiring density than the second wiring layer.

Preferably, the photoresist material used for the first bonding dielectric layer and the second bonding dielectric layer comprises a polyimide-based photoresist;

and/or the presence of a gas in the gas,

the first bonding conductive column is made of a copper material, and the second bonding conductive column is made of a copper material.

A package substrate for stacking comprises a first wiring layer, a first bonding dielectric layer on the first wiring layer, and a first bonding conductive pillar on the first wiring layer and surrounded by the first bonding dielectric layer, wherein the first bonding conductive pillar is used for forming a conductive bonding with a conductive pillar of another package substrate, and the first bonding dielectric layer is used for physically bonding with a dielectric layer surrounding the conductive pillar on the other package substrate;

the average longitudinal height of the first bonding dielectric layer is less than the average longitudinal height of the first bonding conductive pillars.

Preferably, an average first longitudinal height difference formed by the first bonding dielectric layer and the first bonding conductive pillar is between 0.1nm and 10nm.

A chip packaging structure of a stacked packaging substrate comprises any one stacked packaging substrate, wherein a chip packaging layer is arranged on the upper surface of a first wiring layer; the chip packaging layer comprises a chip, a bonding pad and an encapsulating layer, and the chip is electrically connected with the first wiring layer through the bonding pad; the encapsulating layer coats the chip;

the chip packaging layer further comprises an underfill layer filled between the chip and the first wiring layer.

A preparation method of a stacked package substrate comprises the following steps:

preparing a first packaging substrate, wherein the first packaging substrate comprises a first wiring layer and a first bonding dielectric layer on the first wiring layer, and a first bonding conductive column electrically connected with the first wiring layer is embedded in the first bonding dielectric layer;

preparing a second packaging substrate, wherein the second packaging substrate comprises a second wiring layer and a second bonding dielectric layer arranged on the second wiring layer, and a second bonding conductive pillar electrically connected with the second wiring layer is embedded in the second bonding dielectric layer;

and corresponding the positions of the first bonding conductive column and the second bonding conductive column, and performing conductive bonding through high temperature and/or high pressure and/or ultrasonic treatment.

As a preferred scheme, the preparing the first packaging substrate comprises the following steps:

preparing a first wiring layer on a first carrier plate with a first temporary release layer;

preparing a first bonding dielectric layer having an array of openings on the first wiring layer;

preparing a first bonding conductive column at the opening array of the first bonding dielectric layer and carrying out planarization treatment on the surface of the first bonding conductive column to obtain a first bonding surface;

performing oxygen etching on the first bonding surface to enable the average longitudinal height of the first bonding dielectric layer to be smaller than that of the first bonding conductive pillar and form a first longitudinal height difference;

the preparation of the second packaging substrate comprises the following steps:

preparing a second wiring layer on a second carrier plate with a second temporary release layer;

preparing a second bonding dielectric layer having an array of openings on the second wiring layer;

preparing a second bonding conductive pillar at the opening array of the second bonding dielectric layer and carrying out planarization treatment on the surface of the second bonding conductive pillar to obtain a second bonding surface;

and performing oxygen etching on the second bonding surface to enable the average longitudinal height of the second bonding dielectric layer to be larger than that of the second bonding conductive pillar and form a second longitudinal height difference.

Preferably, the first bonding surface has an average surface roughness of 0.1nm to 10nm;

and/or the presence of a gas in the gas,

the second bonding surface has an average surface roughness of 0.1nm to 10nm.

Preferably, the electrically conductive bonding is performed by corresponding the positions of the first bonding conductive pillar and the second bonding conductive pillar and by high temperature and/or high pressure and/or ultrasonic processing, and the method includes the following steps:

enabling the first bonding conductive columns and the second bonding conductive columns to correspond one to one;

under the conditions of high temperature and/or high pressure and/or ultrasonic wave, the first bonding dielectric layer and the second bonding dielectric layer are physically bonded to form a bonding dielectric layer, and the metal atoms on the surface of the first bonding conductive column and the metal atoms on the surface of the second bonding conductive column are diffused to form a conductive bonding.

Preferably, before forming the conductive bond between the first bond conductive pillar and the second bond conductive pillar, the method further includes the following steps:

performing oxygen etching on the first bonding dielectric layer to enable the corresponding first longitudinal height difference after oxygen etching to be larger than zero; and/or

And performing oxygen etching on the second bonding dielectric layer to enable the corresponding second longitudinal height difference after oxygen etching to be larger than zero.

Preferably, when the first bonding conductive pillar and/or the second bonding conductive pillar adopt nano-twin crystal copper, the first bonding conductive pillar and the second bonding conductive pillar are aligned, and then heat treatment is performed to achieve conductive bonding between the first bonding conductive pillar and the second bonding conductive pillar.

Preferably, the heat treatment temperature is in the range of 100 ℃ to 300 ℃.

A method for preparing a chip packaging structure of a stacked packaging substrate comprises any one of the above methods, and further comprises the following steps:

electrically connecting a chip to the first wiring layer, and performing underfill and plastic package protection on the chip;

preparing an external connection conductive part by taking the second wiring layer as a reference surface to obtain a chip pre-packaging body;

and cutting the chip pre-packaging body by taking a plurality of chips as units to prepare the chip packaging structure with the superposed packaging substrate.

A method for preparing a chip packaging structure of a stacked packaging substrate comprises the following steps:

preparing a first packaging substrate, wherein the first packaging substrate comprises a first wiring layer and a first bonding dielectric layer on the first wiring layer, and a first bonding conductive column electrically connected with the first wiring layer is embedded in the first bonding dielectric layer;

preparing a chip packaging layer on the opposite side of the first wiring layer with respect to the first bonding dielectric layer;

preparing a second packaging substrate, wherein the second packaging substrate comprises a second wiring layer and a second bonding dielectric layer arranged on the second wiring layer, and a second bonding conductive pillar electrically connected with the second wiring layer is embedded in the second bonding dielectric layer;

fabricating an external conductive feature on an opposite side of the second wiring layer with respect to the second bonding dielectric layer;

the positions of the first bonding conductive column and the second bonding conductive column correspond, and conductive bonding is carried out through high temperature and/or high pressure and/or ultrasonic treatment;

and cutting the chips as units to obtain the chip packaging structure with the stacked packaging substrate.

Compared with the prior art, the invention has the following beneficial effects:

firstly, by adopting a superposition type packaging substrate formed by combining a first packaging substrate and a second packaging substrate with different wiring densities, the packaging substrates with two different copper wire sizes can be physically connected, wherein the first packaging substrate is used for interconnecting chips with smaller packaging sizes, and the second packaging substrate is used for interconnecting with a PCB (printed circuit board) or a packaging substrate with low wiring density, so that transition interconnection between a fan-out rewiring packaging structure with high wiring density and the PCB or the packaging substrate with low wiring density is realized; secondly, the copper circuit layer in the second packaging substrate adopts a process procedure of a chip packaging factory (instead of a traditional chip mounting factory), so that the size of a copper wire in a traditional packaging substrate can be further reduced, the packaging integration level of a chip is improved, and the size of a chip packaging product is further reduced; and thirdly, as the chip packaging factory integrates a part of the traditional packaging substrate process, the processing process of the chip packaging product can be simplified, and the processing period of the chip packaging product can be reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a chip package structure of a stacked package substrate according to the present invention;

fig. 2-4 are schematic structural diagrams corresponding to step S1 of a first method for manufacturing a chip package substrate with an overlay type package substrate according to the present invention;

fig. 5-7 are schematic structural diagrams corresponding to step S2 of a first method for manufacturing a chip package with an overlay type package substrate according to the present invention;

fig. 8-10 are schematic structural views corresponding to step S3 of a method for manufacturing a chip package with an overlay type package substrate according to the first embodiment of the present invention;

fig. 11-13 are schematic structural diagrams corresponding to step S4 of a method for manufacturing a chip package with an overlay type package substrate according to a first embodiment of the present invention;

fig. 14 is a schematic structural diagram corresponding to step S5 of a second method for manufacturing a chip package with an overlying package substrate according to the present invention.

Fig. 15 is a schematic structural diagram corresponding to step S3' of a second method for manufacturing a chip package with an overlying package substrate according to the present invention.

Fig. 16 is a schematic structural diagram corresponding to step S5' of a second method for manufacturing a chip package with an overlying package substrate according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "height," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated in a particular orientation, and thus are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.

In a first aspect, a chip package structure of an overlay type package substrate includes, as shown in fig. 1 and 10, a first package substrate P1 and a second package substrate P2 that are bonded to each other, where the first package substrate P1 includes a first wiring layer 10, a first bonding dielectric layer 11 located on a lower surface of the first wiring layer 10, and a first bonding conductive pillar 12 surrounded by the first bonding dielectric layer 11; the second package substrate P2 includes a second wiring layer 20, a second bonding dielectric layer 21 on the upper surface of the second wiring layer 20, and a second bonding conductive pillar 22 surrounded by the second bonding dielectric layer 21; the first bonding conductive pillar 12 is correspondingly bonded with the second bonding conductive pillar 22; the first wiring layer 10 has a higher wiring density than the second wiring layer 20. The upper surface of the first wiring layer 10 is provided with a chip packaging layer.

In the present embodiment, as shown in fig. 1, the first wiring layer 10 includes a first metal layer 10a and a first dielectric layer 10b, and may adopt a multilayer wiring structure; the second wiring layer 20 includes a second metal layer 20a and a second dielectric layer 20b, and a multilayer wiring structure may be used. The first wiring layer 10 has a higher wiring density, and the first package substrate P1 may be used for direct interconnection with a chip pin having a smaller package size, corresponding to a smaller size of the copper wire in the first metal layer 10 a; the wiring density of the second wiring layer 20 is lower, and the size of the copper wire in the corresponding second metal layer 20a is larger, that is, the line width and the line distance of the second metal layer 20a are both larger than the line width and the line distance of the first metal layer 10 a; the second package substrate P2 may be used for transition interconnection with a PCB board having a low wiring density.

The superposed package substrate obtained by bonding the first package substrate P1 and the second package substrate P2 can physically connect two package units with different copper wire sizes. The copper circuit layer in the second packaging substrate adopts the process of a chip packaging factory, so that the size of a copper wire of a traditional packaging substrate can be further reduced, the packaging integration level of a chip is improved, and the size of a chip packaging product is further reduced. In addition, because the chip packaging factory integrates the traditional packaging substrate process, the processing process of the chip packaging product can be simplified, and the processing period of the chip packaging product is further reduced.

In a preferred embodiment, the first bonding dielectric layer 11 and the second bonding dielectric layer 21 are correspondingly bonded, and the first bonding conductive pillar 12 and the second bonding conductive pillar 22 are correspondingly physically bonded, so as to form a conductive bond.

In some embodiments, when the first and second bonding conductive pillars 12 and 22 are prepared by conventional electroplating or electroless plating with copper material as the conductive medium (other metal materials common in the art, such as Al, ag, ni, W, au, etc., can also be used), the copper atoms on the surface layer of the first bonding conductive pillar 12 and the copper atoms on the surface layer of the second bonding conductive pillar 22 can diffuse into each other under high temperature and/or high pressure and/or ultrasonic conditions, and a bonding copper layer based on covalent bonds of copper atoms is formed under high temperature and/or high pressure and/or ultrasonic conditions. Specifically, the high temperature and/or ultrasonic conditions accelerate the lattice vibration of the copper atoms in the copper pillar, and the high pressure conditions facilitate interdiffusion and intercalation between the copper atoms at the interface of the first bonding conductive pillar 12 and the interface of the second bonding conductive pillar 22, so as to form a homogeneous fused copper layer with covalently bonded copper atoms between the interface of the first bonding conductive pillar 12 and the interface of the second bonding conductive pillar 22. Also, the first bonding dielectric layer 11 and the second bonding dielectric layer 21 may be physically bonded under high temperature and/or high pressure and/or ultrasonic conditions to form a bonding dielectric layer.

In some embodiments, when the high temperature process is used to promote the interdiffusion and fusion between the copper atoms on the surface layer of the first bonding conductive pillar 12 and the copper atoms on the surface layer of the second bonding conductive pillar 22, since the high temperature process may cause the expansion of the lattice of the copper atoms and the expansion of the bonding dielectric layer, and generally, the thermal expansion coefficient of the bonding dielectric layer is greater than that of copper, a certain gap needs to be reserved between the first bonding dielectric layer and the second bonding dielectric layer in a one-to-one correspondence, and the average longitudinal height of the first bonding dielectric layer and/or the second bonding dielectric layer is smaller than that of the first bonding conductive pillar and/or the second bonding conductive pillar, so that the copper pillars after the expansion of the high temperature process are just physically bonded, and the first bonding dielectric layer and the second bonding dielectric layer after the expansion of the high temperature process are just physically bonded, and the height of the gap is preferably 1nm to 100nm. Wherein the average longitudinal height of the first bonding dielectric layer 11 can be smaller than the average longitudinal height of the first bonding conductive pillar 12 and form a first longitudinal height difference, wherein the average first longitudinal height difference is controlled to be 0.1nm-10nm; the second dielectric layer 21 may have a vertical height smaller than the average vertical height of the second bonding conductive pillars 22 and form an average second vertical height difference, wherein the average second vertical height difference is controlled to be 0.1nm to 10nm.

In some embodiments, when the first bonding conductive pillar 12 and the second bonding conductive pillar 22 use nano-twin crystal copper, first, the first package substrate needs to be polished with the first bonding dielectric layer 11 as a reference surface, and then a certain amount of the first bonding dielectric layer 11 is removed in an oxygen etching atmosphere, so that the average longitudinal height of the first bonding dielectric layer 11 is smaller than the average longitudinal height of the first bonding copper pillar and a first longitudinal height difference is formed; the second dielectric layer 21 is used as a reference surface to perform a planarization grinding treatment on the second package substrate, and then a certain amount of the second bonding dielectric layer 21 is removed in an oxygen etching atmosphere, so that the average longitudinal height of the second bonding dielectric layer 21 is smaller than the average longitudinal height of the second bonding copper pillar and a second longitudinal height difference is formed, wherein the average surface roughness (Ra) of planarization grinding can be 0.1nm-10nm; then, the first bonding conductive pillar 12 and the second bonding conductive pillar 22 are subjected to heat treatment within a certain temperature range, so that the conductive bonding of the nano-twin crystal copper can be realized, and the physical bonding between the first bonding dielectric layer 11 and the second bonding dielectric layer 21 is realized, wherein the heat treatment temperature is 100 ℃ to 300 ℃.

As a preferred embodiment, the chip packaging layer includes a chip, an interconnection E, an underfill layer 1 and an encapsulation layer 2, the chip is electrically connected to the first wiring layer 10 through the interconnection E; the encapsulating layer 2 encapsulates the chip.

In this embodiment, as shown in fig. 1, the chip may include a first chip 100 and a second chip 200. The pin columns 101 on the chip can be correspondingly welded with the bonding pads 13 through solder blocks 102 to form the electrical connection of the chip to the first wiring layer. In this embodiment, the chip may be encapsulated by a material such as epoxy resin to form the encapsulating layer 2, so as to encapsulate and protect the chip and reduce the reliability risk.

In addition, the chip packaging layer may further include an underfill layer 1 filled between the chip and the first wiring layer. The material of the underfill layer 1 can be epoxy resin-based high polymer material; the chip redistributes the mechanical stresses caused by the CTE mismatch between the encapsulating materials through the underfill layer 1.

The stacked package substrate according to the present aspect can be obtained by bonding two package substrates for stacking. For example, the two package substrates for stacking may be the first package substrate P1 and the second package substrate P2. Before the two are bonded, the first package substrate P1 may include a first wiring layer, a first bonding dielectric layer on the first wiring layer, and a first bonding conductive pillar on the first wiring layer and surrounded by the first bonding dielectric layer. The second package substrate P2 may include a second wiring layer, a second bonding dielectric layer on the second wiring layer, and a second bonding conductive pillar on the second wiring layer and surrounded by the second bonding dielectric layer.

The first bonding conductive pillar is for forming an electrically conductive bond with the second conductive pillar, and the first bonding dielectric layer is for physically bonding with the second bonding dielectric layer.

The dielectric layer and the conductive pillar of at least one of the first package substrate P1 and the second package substrate P2 have a vertical height difference. In other words, the average longitudinal height of the first bonding dielectric layer is less than the average longitudinal height of the first bonding conductive pillars, and/or the average longitudinal height of the second bonding dielectric layer is less than the average longitudinal height of the second bonding conductive pillars. The average longitudinal height difference is between 0.1nm and 10nm.

In a second aspect, a first method for manufacturing a chip package structure of a stacked package substrate includes the following steps:

s1: preparing a first package substrate P1, where the first package substrate P1 includes a first wiring layer 10 and a first bonding dielectric layer 11 thereon, and a first bonding conductive pillar 12 electrically connected to the first wiring layer 10 is embedded in the first bonding dielectric layer 11.

Wherein, the step S1 may specifically include the following steps:

s101: a first wiring layer 10 is prepared on a first carrier C1 having a first temporary release layer F1.

As shown in fig. 2, a first carrier C1 is prepared, a first temporary release layer F1 is prepared on the first carrier C1, and then a first wiring layer 10 is prepared on the first temporary release layer F1; the first wiring layer 10 includes a first dielectric layer 10b and a first metal layer 10a, and the first dielectric layer 10b provides an insulating and isolating function for routing arrangement of conductive metal. The metal wiring layer 10a may be made of copper material. The first wiring layer 10 may be composed of a plurality of wiring layers.

The first dielectric layer 10b may be prepared by coating polyimide photoresist and performing processes such as low temperature baking, exposure, development, and high temperature curing.

S102: a first bonding dielectric layer 11 having an array of openings is prepared on the first wiring layer 10.

As shown in fig. 3, the first wiring layer 10 is subjected to a planarization polishing process to obtain a first wiring layer 10 surface with a high surface flatness; a first bonding dielectric layer 11 is then prepared on the first wiring layer. The first bonding dielectric layer 11 has an array of openings for exposing the first metal layer 10a.

The first bonding dielectric layer 11 can be prepared by coating polyimide photoresist or directly pasting a dry film with a photosensitizer and performing processes such as low-temperature drying, exposure, development and the like. That is, the first dielectric layer 11 may be a polyimide photoresist that is subjected to a low temperature baking process to evaporate the organic solvent and moisture in the first dielectric layer 11, and does not undergo a complete cross-linking curing reaction at a high temperature.

The temperature range of the low-temperature baking heat treatment is determined according to the material composition of the photoresist, specifically, the lower limit temperature range T1 of the low-temperature baking heat treatment is to remove the solvent in the photoresist, the upper limit temperature range T2 of the low-temperature baking heat treatment is to sufficiently crosslink and cure the photoresist, and thus, the temperature range of the low-temperature baking heat treatment for the first bonding dielectric layer 11 is [ T1, T2].

S103: a first bonding conductive pillar 12 is prepared at the opening array of the first bonding dielectric layer 11 and is planarized to obtain a first bonding surface. The first bonding conductive pillar 12 may be made of copper material.

As shown in fig. 4, an electroplating copper process, an electroless copper process, or a copper deposition process may be performed at the opening array to obtain the first bonding conductive pillar 12; and performing planarization grinding treatment on the surfaces of the first bonding dielectric layer 11 and the first bonding conductive column 12 to obtain a first bonding surface, wherein the average surface roughness (Ra) of the first bonding surface is less than or equal to 10nm. The first bonding conductive pillar 12 is electrically connected to the first metal layer 10a.

S104: the first bonding surface is etched with oxygen, so that the average longitudinal height of the first bonding dielectric layer 11 is smaller than the average longitudinal height of the first bonding conductive pillar 12, and a first longitudinal height difference is formed.

The surfaces of the first bonding dielectric layer 11 and the first bonding conductive pillar 12 after the planarization and grinding treatment are placed in an oxygen etching atmosphere, and the first bonding dielectric layer with a certain longitudinal height is removed through oxygen etching, so that the average longitudinal height of the first bonding dielectric layer 11 is smaller than the average longitudinal height of the first bonding conductive pillar 12, and a first longitudinal height difference is formed, wherein the range of the average first longitudinal height difference is 0.1nm-10nm.

S2: preparing a second package substrate P2, where the second package substrate P2 includes a second wiring layer 20 and a second bonding dielectric layer 21 thereon, and a second bonding conductive pillar 22 electrically connected to the second wiring layer 20 is embedded in the second bonding dielectric layer 21.

Wherein, the step S2 may specifically include the following steps:

s201: a second wiring layer 20 is prepared on a third carrier C3 with a third temporary release layer F3.

As shown in fig. 5, a second carrier C2 is prepared, a second temporary release layer F3 is prepared on the second carrier C2, and then a second wiring layer 20 is prepared on the second temporary release layer F2. The second wiring layer 20 includes a second metal layer 20a and a second dielectric layer 20b, and the second dielectric layer 20b provides an insulating and isolating function for routing arrangement of metal. The second metal layer 20a may be made of copper material. The second wiring layer 20 may be composed of a plurality of wiring layers.

S202: a second bonding dielectric layer 21 having an array of openings is prepared on the second wiring layer 20.

As shown in fig. 6, second wiring layer 20 is polished to obtain a surface of second wiring layer 20 with high surface flatness, and second bonding dielectric layer 21 is prepared on second wiring layer. The second bonding dielectric layer 21 has an array of openings for exposing the second metal layer 20a.

The second dielectric layer 20b may be prepared by coating a polyimide photoresist or attaching a dry film with a photosensitizer, and performing processes such as low-temperature drying, exposure, development, and the like. The low-temperature baking treatment is to evaporate the organic solvent and moisture in the second bonding dielectric layer 21, the temperature range of the low-temperature baking heat treatment is determined according to the material composition of the photoresist, specifically, the lower limit temperature range T3 of the low-temperature baking heat treatment is to remove the solvent in the photoresist, the upper limit temperature range T4 of the low-temperature baking heat treatment is to sufficiently crosslink and cure the photoresist, and thus, the temperature range of the low-temperature baking heat treatment for the second bonding dielectric layer 21 is [ T3, T4].

S203: a second bonding conductive pillar 22 is prepared at the opening array of the second bonding dielectric layer 21 and planarized to obtain a second bonding surface. The second bonding conductive pillar 22 may be made of copper material.

As shown in fig. 7, an electro-coppering or electroless copper plating process may be performed at the opening array to obtain the second bonding conductive pillar 22; and performing planarization grinding treatment on the surfaces of the second bonding dielectric layer 21 and the second bonding conductive column 22 to obtain a second bonding surface, wherein the average surface roughness (Ra) of the second bonding surface is less than or equal to 10nm. The second bonding conductive pillar 22 is electrically connected to the second metal layer 20a.

S204: the second bonding surface is subjected to oxygen etching, so that the average longitudinal height of the second bonding dielectric layer 21 is smaller than the average longitudinal height of the second bonding conductive pillar 22, and a second longitudinal height difference is formed.

The surfaces of the second bonding dielectric layer 21 and the second bonding conductive pillar 22 after the planarization and grinding process are placed in an oxygen etching atmosphere, and the second bonding dielectric layer with a certain longitudinal height is removed through oxygen etching, so that the average longitudinal height of the second bonding dielectric layer 21 is smaller than the average longitudinal height of the second bonding conductive pillar 22, and a second longitudinal height difference is formed, wherein the range of the average second longitudinal height difference is 0.1nm-10nm.

In some embodiments, when the high temperature process is used to promote the interdiffusion and fusion between the copper atoms on the surface layer of the first bonding conductive pillar 12 and the copper atoms on the surface layer of the second bonding conductive pillar 22, since the high temperature process may cause the expansion of the lattice of the copper atoms and the expansion of the bonding dielectric layer, and generally, the thermal expansion coefficient of the bonding dielectric layer is greater than that of copper, a certain gap needs to be reserved between the first bonding conductive pillar and the second bonding conductive pillar that correspond to each other, and the average longitudinal height of the first bonding dielectric layer and/or the second bonding dielectric layer is smaller than that of the first bonding conductive pillar and/or the second bonding conductive pillar, so that the copper pillars after the expansion of the high temperature process are just physically bonded, and the first bonding dielectric layer and the second bonding dielectric layer that are expanded by the high temperature process are just physically bonded. Therefore, the first bonding dielectric layer with a certain longitudinal height can be removed by performing oxygen etching on the ground first bonding dielectric layer, so that the first bonding dielectric layer after the oxygen etching is lower than the first bonding conductive pillar in the longitudinal height and forms a certain first longitudinal height difference, and the average first longitudinal height difference is controlled to be 0.1nm-10nm; similarly, the first bonding dielectric layer with a certain longitudinal height can be removed by etching with oxygen in the second bonding dielectric layer after grinding treatment, so that the second bonding dielectric layer after etching with oxygen is lower than the second bonding conductive pillar in the longitudinal height and forms a certain second longitudinal height difference, and the average second longitudinal height difference is controlled to be 0.1nm-10nm.

In some embodiments, when the bonding copper pillar is made of nano twinned copper, the conductive bonding of the bonding copper pillar may be achieved only by aligning the first bonding conductive pillar having the first vertical height difference and/or the second bonding conductive pillar having the second vertical height difference, and performing a heat treatment within a certain temperature range, wherein the heat treatment temperature is 100 ℃ to 300 ℃.

In some embodiments, the wiring density of the second metal layer 20a in the second wiring layer 20 is different from the wiring density of the first metal layer 10a in the first wiring layer 10. Specifically, as shown in fig. 8, in this embodiment, a scheme that the wiring density of the second metal layer 20a is less than the wiring density of the first metal layer 10a may be adopted, wherein the line width and the line distance of the second metal layer 20a are both greater than the line width and the line distance of the first metal layer 10a. The larger diameter metal lines in the second metal layer 20a may be used to serve as a transitional interconnect between the fan-out rewiring package with high wiring density and the PCB board with low wiring density; the metal lines of the first metal layer 10a with smaller diameter can be used for interconnection with the chip pins.

S3: the positions of the first bonding conductive pillars 12 of the first package substrate P1 and the second bonding conductive pillars 22 of the second package substrate P2 are corresponded, and bonding is performed by high temperature and/or high pressure and/or ultrasonic processing.

Wherein, the step S3 may specifically include the following steps:

s301: the first bonding conductive pillars 12 and the second bonding conductive pillars 22 are in one-to-one correspondence, as shown in fig. 8.

S302: under the conditions of high temperature and/or high pressure and/or ultrasonic wave, the first bonding dielectric layer 11 and the second bonding dielectric layer 21 are subjected to cross-linking bonding, and copper atoms at the surface of the first bonding conductive pillar 12 and copper atoms at the surface of the second bonding conductive pillar 22 are diffused and form conductive bonding.

As shown in fig. 9 and 10, the polyimide of the first and second dielectric bonding layers 11 and 21 are subjected to high temperature and/or high pressure and/or ultrasonic treatment to form the dielectric bonding layers. The high temperature and/or high pressure and/or ultrasonic treatment herein may achieve physical bonding between the first bonding dielectric layer 11 and the second bonding dielectric layer 21, forming a bonding dielectric layer therebetween, and tightly connecting the first bonding dielectric layer 11 and the second bonding dielectric layer 21.

In some embodiments, when the first bonding conductive pillar and/or the second bonding conductive pillar are plated or electroless plated or deposited with copper, under high temperature and/or high pressure and/or ultrasonic conditions, the copper atoms in the first bonding conductive pillar and the second bonding conductive pillar accelerate the diffusion rate, and break through the first copper pillar interface and the second copper pillar interface under the action of high pressure and/or ultrasonic waves, so that the copper atoms in the first bonding conductive pillar 12 are diffused and embedded into the copper crystal structure in the second bonding conductive pillar 22, and at the same time, the copper atoms in the second bonding conductive pillar 22 are also diffused and embedded into the copper crystal structure in the first bonding conductive pillar 12, thereby forming a bonding copper layer with good conductive connection.

In some embodiments, when the first bonding conductive pillars and/or the second bonding conductive pillars adopt nano-twin copper, only the first bonding conductive pillars having the first longitudinal height difference and/or the second bonding conductive pillars having the second longitudinal height difference need to be aligned,

and then carrying out heat treatment within a certain temperature range to realize the conductive bonding of the bonded copper cylinder, wherein the heat treatment temperature is 100-300 ℃.

Thus, a stacked package substrate is prepared.

S4: and electrically connecting the chip with the superposition type packaging substrate, and carrying out bottom filling and plastic packaging protection on the chip to obtain the chip prepackaged body with the superposition type packaging substrate and the externally-connected conductive parts.

The step S4 may specifically include the following steps:

s401: as shown in fig. 11, the pads 13 are prepared with the first wiring layer 10 as a reference plane, and the pin pillars 101 and the solder bumps 102 on the chip 100 and the chip 200 are in one-to-one correspondence with the pads 13;

s402: as shown in fig. 12, the pin pillars 101 and the pads 13 are electrically connected through solder balls 102' formed by a high-temperature reflow soldering process, that is, the chip 100 and the chip 200 are electrically connected with the stacked package substrate through a conductive member E;

filling the conductive piece E at the bottom to obtain an underfill layer 1;

and (3) carrying out plastic packaging filling on the chip 100 and the chip 200 to prepare a plastic packaging layer 2, and grinding along the passive surface of the chip until silicon materials in the chip are exposed, so that the adverse effect of the plastic packaging filler on the heat dissipation of the chip is reduced.

S403: as shown in fig. 13, a third carrier C3 with a third temporary release layer F3 is prepared, the chip pre-package structure prepared in S402 is flipped and attached to the third temporary release layer F3, and the second carrier C2 of the second temporary release layer F2 is removed;

external conductive members including external conductive posts 23 and external solder balls 24 are prepared with the second wiring layer 20 as a reference surface.

S5: and (3) dividing the chip pre-packaging body by taking a plurality of chips as units to prepare the chip packaging structure with the superposed packaging substrate and the externally-connected conductive parts.

The method comprises the following specific steps:

as shown in fig. 14, a first protective adhesive film M1 is applied on the external connection conductive component, and the chip packaging structure is turned over;

preparing a fourth carrier plate C4 with a fourth temporary release layer F4, and attaching a first protective adhesive film on the chip packaging structure to the fourth temporary release layer F4;

and cutting the whole packaging body by taking a plurality of chips as units along the cutting path 3a, and then removing the fourth carrier plate C4 and the fourth temporary release layer F4 by bonding so as to obtain the chip packaging structure shown in FIG. 1.

In a second method for manufacturing a chip package structure of a stacked package substrate, the method includes the steps of:

s1': preparing a first package substrate P1, with reference to step S1;

s2': preparing a chip packaging layer on the opposite side of the first wiring layer 10 with respect to the first bonding dielectric layer 11, with reference to steps S401 to S402;

s3': a second package substrate P2 with an external conductive member is prepared, with reference to step S2.

As shown in fig. 15, on the basis of the step S2, a fifth carrier plate C5 is prepared, a fifth temporary release layer F5 is prepared on the fifth carrier plate C5, and then the second bonding dielectric layer 21 and the second bonding conductive pillars 22 are applied onto the fifth temporary release layer F5; and an external conductive member is prepared with the second wiring layer 20 as a reference plane.

The external conductive component includes an external conductive column 23 and an external solder ball 24.

And S4': referring to step S3, the first bonding conductive pillars 12 in the first package substrate P1 and the second bonding conductive pillars 22 in the second package substrate P2 are bonded.

And S5': as shown in fig. 16, the stacked package substrate is divided by using a plurality of chips as a unit, so as to obtain the chip package structure with the stacked package substrate as shown in fig. 1.

The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Claims (15)

1. The stacked package substrate is characterized by comprising a first package substrate and a second package substrate which are mutually conductively jointed, wherein the first package substrate comprises a first wiring layer, a first jointing dielectric layer positioned on the lower surface of the first wiring layer and a first jointing conductive column surrounded by the first jointing dielectric layer; the second packaging substrate comprises a second wiring layer, a second bonding dielectric layer and a second bonding conductive pillar, wherein the second bonding dielectric layer is located on the upper surface of the second wiring layer, and the second bonding conductive pillar is surrounded by the second bonding dielectric layer; the first bonding conductive pillar and the second bonding conductive pillar correspondingly form conductive bonding;

the first bonding dielectric layer and the second bonding dielectric layer are physically bonded to form a bonding dielectric layer.

2. A stacked package substrate of claim 1, wherein: the first wiring layer has a higher wiring density than the second wiring layer.

3. A stacked package substrate of claim 1 or 2, wherein: the materials adopted by the first bonding dielectric layer and the second bonding dielectric layer comprise polyimide-based photoresist;

and/or the presence of a gas in the gas,

the first bonding conductive column is made of a copper material, and the second bonding conductive column is made of a copper material.

4. A package substrate for stacking, characterized by:

the packaging structure comprises a first wiring layer, a first bonding dielectric layer and a first bonding conductive pillar, wherein the first bonding dielectric layer is located on the first wiring layer, the first bonding conductive pillar is located on the first wiring layer and is surrounded by the first bonding dielectric layer, the first bonding conductive pillar is used for forming conductive bonding with a conductive pillar of another packaging substrate, and the first bonding dielectric layer is used for physically bonding with a dielectric layer surrounding the conductive pillar on the other packaging substrate;

the average longitudinal height of the first bonding dielectric layer is smaller than the average longitudinal height of the first bonding conductive pillar.

5. A package substrate for stacking according to claim 4, wherein:

the average value of the first longitudinal height difference formed by the first bonding dielectric layer and the first bonding conductive column is between 0.1nm and 10nm.

6. A chip package structure of a stacked package substrate, comprising the stacked package substrate of any one of claims 1 to 3, wherein:

a chip packaging layer is arranged on the upper surface of the first wiring layer; the chip packaging layer comprises a chip, a bonding pad and an encapsulating layer, and the chip is electrically connected with the first wiring layer through the bonding pad; the encapsulating layer coats the chip;

the chip packaging layer further comprises an underfill layer filled between the chip and the first wiring layer.

7. A preparation method of a stacked package substrate is characterized by comprising the following steps:

preparing a first packaging substrate, wherein the first packaging substrate comprises a first wiring layer and a first bonding dielectric layer on the first wiring layer, and a first bonding conductive pillar electrically connected with the first wiring layer is embedded in the first bonding dielectric layer;

preparing a second packaging substrate, wherein the second packaging substrate comprises a second wiring layer and a second bonding dielectric layer arranged on the second wiring layer, and a second bonding conductive pillar electrically connected with the second wiring layer is embedded in the second bonding dielectric layer;

and corresponding the positions of the first bonding conductive column and the second bonding conductive column, and performing conductive bonding through high temperature and/or high pressure and/or ultrasonic treatment.

8. A method of making an overlay package substrate of claim 7, wherein:

the preparation of the first package substrate comprises the following steps:

preparing a first wiring layer on a first carrier plate with a first temporary release layer;

preparing a first bonding dielectric layer having an array of openings on the first wiring layer;

preparing a first bonding conductive column at the opening array of the first bonding dielectric layer and carrying out planarization treatment on the surface of the first bonding conductive column to obtain a first bonding surface;

making the average longitudinal height of the first bonding dielectric layer smaller than the average longitudinal height of the first bonding conductive pillar and forming a first longitudinal height difference;

the preparation of the second package substrate comprises the following steps:

preparing a second wiring layer on a second carrier plate with a second temporary release layer;

preparing a second bonding dielectric layer having an array of openings on the second wiring layer;

preparing a second bonding conductive column at the opening array of the second bonding dielectric layer and carrying out planarization treatment on the surface of the second bonding conductive column to obtain a second bonding surface;

the average longitudinal height of the second bonding dielectric layer is larger than that of the second bonding conductive pillar, and a second longitudinal height difference is formed.

9. A method of making an overlay package substrate of claim 8, wherein:

the average surface roughness of the first bonding surface is less than or equal to 10nm;

and/or the presence of a gas in the atmosphere,

the average surface roughness of the second bonding surface is less than or equal to 10nm.

10. A method for fabricating a stacked package substrate as recited in claim 7, wherein:

the corresponding positions of the first bonding conductive column and the second bonding conductive column are carried out, and the conductive bonding is carried out through high temperature and/or high pressure and/or ultrasonic treatment, and the method comprises the following steps:

enabling the first bonding conductive columns and the second bonding conductive columns to correspond one to one;

under the conditions of high temperature and/or high pressure and/or ultrasonic wave, the first bonding dielectric layer and the second bonding dielectric layer are physically bonded to form a bonding dielectric layer, and the metal atoms on the surface of the first bonding conductive column and the metal atoms on the surface of the second bonding conductive column are diffused to form a conductive bonding.

11. A method for preparing a stacked package substrate according to any one of claims 7-10, wherein:

before forming the conductive joint between the first joint conductive column and the second joint conductive column, the method further comprises the following steps:

performing oxygen etching on the first bonding dielectric layer to enable the corresponding first longitudinal height difference after oxygen etching to be larger than zero; and/or

And performing oxygen etching on the second bonding dielectric layer to enable the corresponding second longitudinal height difference after oxygen etching to be larger than zero.

12. A method for fabricating a stacked package substrate as recited in claim 7, wherein: when the first bonding conductive pillar and/or the second bonding conductive pillar adopt nano twin crystal copper, the first bonding conductive pillar and the second bonding conductive pillar are aligned, and then heat treatment is carried out to realize conductive bonding between the first bonding conductive pillar and the second bonding conductive pillar.

13. A method for fabricating a stacked package substrate as recited in claim 12, wherein: wherein the heat treatment temperature range is 100-300 ℃.

14. A method for manufacturing a chip package structure of a stacked package substrate, comprising the method for manufacturing a stacked package substrate according to any one of claims 7 to 13, further comprising the steps of:

electrically connecting a chip to the first wiring layer, and performing bottom filling and plastic package protection on the chip;

preparing an external connection conductive part by taking the second wiring layer as a reference surface to obtain a chip prepackage body;

and cutting the chip pre-packaging body by taking a plurality of chips as units to prepare the chip packaging structure with the superposed packaging substrate.

15. A method for preparing a chip packaging structure of a superposition type packaging substrate is characterized by comprising the following steps:

preparing a first packaging substrate, wherein the first packaging substrate comprises a first wiring layer and a first bonding dielectric layer on the first wiring layer, and a first bonding conductive pillar electrically connected with the first wiring layer is embedded in the first bonding dielectric layer;

preparing a chip packaging layer on the opposite side of the first wiring layer with respect to the first bonding dielectric layer;

preparing a second packaging substrate, wherein the second packaging substrate comprises a second wiring layer and a second bonding dielectric layer arranged on the second wiring layer, and a second bonding conductive pillar electrically connected with the second wiring layer is embedded in the second bonding dielectric layer;

fabricating an external conductive feature on an opposite side of the second wiring layer with respect to the second bonding dielectric layer;

the positions of the first bonding conductive column and the second bonding conductive column correspond, and conductive bonding is carried out through high temperature and/or high pressure and/or ultrasonic treatment;

and cutting the chips as units to obtain the chip packaging structure with the stacked packaging substrate.

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