CN107579011A

CN107579011A - Method for the semiconductor devices of interconnection stack

Info

Publication number: CN107579011A
Application number: CN201710678886.9A
Authority: CN
Inventors: 赵俊峰
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2013-09-27
Filing date: 2014-09-26
Publication date: 2018-01-12
Also published as: CN104517934B; CN104517934A

Abstract

The present invention describes the method being used for producing the semiconductor devices.Methods described, which is included on the first and second tube cores, forms edge.The edge is extended the first and second tube cores in the horizontal.By the second die-stack in first die, in heap poststack, one or more vias are drilled out through edge.The semiconductor devices includes the redistributing layer extended respectively at least one in the first and second tube cores and corresponding edge.One or more of vias extend through corresponding edge, and one or more of vias are communicated via edge with the first and second tube cores.

Description

Method for the semiconductor devices of interconnection stack

The application is the applying date for September in 2014 26 days, Application No. 201410504407.8, entitled " is used for The divisional application of the application of the method for the semiconductor devices of interconnection stack ".

Technical field

Embodiment described herein relates generally to the multilayer manufacture in microelectronic component and is electrically interconnected.

Background technology

Multilayer semiconductor device includes multiple tube cores, and the multiple tube core is to stack, and utilizes the electricity extended therebetween Connection is bonded.In one example, the device of stacking is formed by two or more wafers (including multiple tube cores), the crystalline substance Circle is coupled at the interface between two or more wafers.The wafer of coupling is cut into small pieces and connects its lead Close to form multiple devices.

In some instances, some tube cores (for example, chip in tube core) of wafer are defective and can not use.Due to crystalline substance Coupling between circle, these defective tube cores are still included in multilayer semiconductor device, and even if in device it is many its Its tube core can use completely, but caused device is also defective and can not use.Therefore, the manufacture based on wafer reduces The total output of available multilayer device.

In other examples, provided by the wire bonding between each layer between the tube core in multilayer semiconductor device Interconnection.For example, two or more semiconductor elements stack (for example, bonding) on substrate, and electric wire is along semiconductor element Wire bond pads extend to substrate.On substrate, the ball grid array being further routed on the opposite side of substrate is electrically interconnected. The semiconductor element stacked has been moulded to protect tube core and electric wire.Electric wire is provided between two layers of multilayer device or more layer INDIRECT COUPLING.Data and power transmission are limited (for example, number using the INDIRECT COUPLING between two layers or more layer of combined leads Speed and corresponding performance according to transmission).In addition, the introducing of the substrate and die cap on the tube core stacked increases multilayer device Height (z-height).

Desirably the improved multilayer manufacturing technology of these and other technical barrier and faster interlayer interconnection skill are solved Art.

Brief description of the drawings

Fig. 1 is the cross-sectional view of multilayer semiconductor device, and the multilayer semiconductor device includes extending through from tube core horizontal stroke To the via at the edge of extension.

Fig. 2 is the detailed cross sectional view of Fig. 1 multilayer semiconductor device.

Fig. 3 is the process chart for an example for showing the method for manufacturing multilayer semiconductor device.

Fig. 4 is the form for the difference in height for showing semiconductor devices.

Fig. 5 is the flow chart for an example for showing the method for manufacturing multilayer semiconductor device.

Fig. 6 is the Z to the semiconductor devices including wire bonding and the semiconductor devices including the via in transverse edge The form being highly compared.

Fig. 7 is the block diagram for another example for showing the method for manufacturing multilayer semiconductor device.

Fig. 8 is the block diagram for another example for showing the method for manufacturing multilayer semiconductor device.

Fig. 9 is another example for including extending through the multilayer semiconductor device of the via of one or more transverse edges Cross-sectional view.

Figure 10 is the flow chart for another example for showing the method for manufacturing multilayer semiconductor device.

Figure 11 is the schematic diagram according to the electronic system of some embodiments of present disclosure.

Embodiment

Explanation and accompanying drawing show well that specific embodiment below, so that those skilled in the art can put into practice these implementations Example.Other embodiments can include in structure, in logic, electrically, technique and other changes.The part of some embodiments and spy Sign can be included in the part and feature of other embodiments, or can replace part and the feature of other embodiments.Right The embodiment illustrated in claim includes whole available equivalents of these claims.

Fig. 1 shows an example of the semiconductor devices 100 including multiple tube cores 102.For example, as shown in fig. 1, half Conductor device 100 comprises at least the tube core 106 of first die 104 and second.As indicated, the edge of 104 and second tube core of first die 106 The upper and lower surface coupling of respective tube core.As in Fig. 1 further shown in, semiconductor devices 100 include one or more Individual edge 108, one or more of edges 108 for example extend laterally 110 size from each in tube core 102 according to edge Individual tube core extends laterally.In one example, as shown on the tube core 106 of first die 104 and second, corresponding edge 108 are extended the respective edges of the tube core 106 of first die 104 and second in the horizontal.

In one example, edge 108 is made up of polymeric material, but not limited to this, and the polymeric material is for example electric Medium mold compound, it is configured as moulding around the tube core 106 of first die 104 and second and therefore protected therein Tube core.In another example, the tube core 106 of first die 104 and second is by the mold compound than being used in edge 108 hard Material is formed, but not limited to this.For example, the tube core 106 of first die 104 and second is made up of silicon.In another example, edge 108 by the tube core 106 of first die 104 and second that is configured as protecting semiconductor devices 100 softer polymer (for example, Compared with low elastic modulus) form.The relatively flexible polymer at edge 108 is easier to be pierced like that (for example, laser as described herein Drilling, machine drilling, FIB removals, etching etc.).

Referring again to Fig. 1, as illustrated, multiple vias 112 extend through one or more tube cores 102.As herein will Description, conductive via 112 allows the communication and data transmission between each tube core and external circuit in tube core 102, The external circuit include but is not limited to along semiconductor devices 100 surface set ball grid array 114, land grid array, Pin grid array etc..As shown in Fig. 1 cross-sectional view, through the edge 108 relative with the tube core 106 of first die 104 and second Form multiple vias 112.As will be described herein, in one example, in the knot being stacked to tube core 102 shown in Fig. 1 Via 112 is formed after in structure.For example, using the one or more in machinery, chemical (photoetching) and method for drilling holes incited somebody to action Hole 112 is got into edge 108.

As being described further herein, in one example, each tube core in tube core 102 includes redistribution Layer, for example, a series of patterned conductive traces that each tube core in adjacent die 102 is provided.Redistributing layer is in pipe Extend on the area occupied of core 102 and enter in edge 108.The conductive trace formed along redistributing layer is arranged to and mistake Hole 112 couples.Therefore, each tube core in the tube core 102 of semiconductor devices 100 can pass through via 112 and one or more Individual other tube cores 102 are communicated, and are optionally communicated with ball grid array 114.By for each in tube core 102 Tube core provides edge 108 and corresponding via 112 therein, and (freedom of encapsulation is adjusted to being covered in die cap by utilization The size of lead) and one or more of underlying substrate tube core with ball grid array wire bonding provided it is other INDIRECT COUPLING is compared, and realizes the direct-coupling between one or more tube cores 102 and ball grid array 114.That is, one In individual example, provide and be used for from the edge 108 (for example, 110 size is extended laterally according to edge) of multiple tube cores 102 extension The mechanism of multiple vias 112 is closely received wherein, and it allow for directly logical between the tube core 102 of semiconductor devices 100 Letter, die cap and substrate without additionally needing the wire bonding for covering multiple tube cores 102 etc. provide this communication.Therefore, half The height (Z height) of conductor device 100 is substantially less than using wirebond interconnections and is then encapsulated in die cap Multiple tube cores and the height with the semiconductor devices of underlying substrate.For example, in some instances, relative to comparable Wire bonding device, the Z height to be saved with the semiconductor devices 100 of the via 112 provided in edge 108 can reach 0.2mm。

Referring again to Fig. 1, as further shown in, in one example, semiconductor devices 100 includes ball grid array 114, the ball grid array 114 includes the multiple soldered balls 116 set along one or more tube cores 102.In the example shown in Fig. 1 In, first die 104 (for example, redistributing layer of first die described herein 104) and the direct-coupling of soldered ball 116.Cause This, the data via via 112 of each tube core in tube core 102 transmit correspondingly is sent to the first pipe via via 112 Core 104 and any other tube core 102.The soldered ball 116 provided in ball grid array 114 is provided and arrived and from semiconductor devices 100 Input and output, and avoid simultaneously and additionally need the underlying substrates of multiple tube cores 102 and come from semiconductor devices receive information simultaneously And transmission information.That is, the redistributing layer by the way that ball grid array 114 to be directly coupled to first die 104, institute in Fig. 1 The semiconductor devices 100 shown need not be additionally useful for the substrate of some semiconductor devices, it is achieved thereby that additional space is saved And provide greater compactness of device.It is through multiple vias 112 at edge 108 and direct along first die 104 by providing The ball grid array 114 of coupling, contributes in semiconductor devices 100 high-speed transfer of (and arrive and from), and makes partly to lead simultaneously The overall height of body device 100 minimizes.

Referring now to Figure 2, provide the more detailed cross-sectional view of the semiconductor devices 100 shown in prior figures 1.Scheming In 2 detailed view, multiple tube cores 102 are again illustrated in stacked structure, and each tube core in tube core 102 includes Such as extend laterally 110 respective edges 108 extended laterally from tube core 102 according to edge.In one example, in tube core 102 Each tube core be die assemblies 201 a part, the die assemblies 201 include corresponding pipe as described in this article Core 102, edge 108 and redistributing layer 202 (and optional mold compound 200).

As shown in Figure 2, via 112 or multiple vias, and via 112 or multiple mistakes are provided through edge 108 Hole continuously extends between tube core 102.In another example, one or more vias 112 extend through one or more sides Edge 108, with provide between two or more tube cores 102 of semiconductor devices 100 or tube core 102 with ball grid array (by again Distribution layer 202) between communication.That is, the via 112 provided in edge 108 is extended partially or entirely through tube core group The stacked body of part 201.The other vias 112 provided through edge 108 extend through two or more edges 108, to stack Semiconductor devices 100 two or more tube cores 102 between communication is correspondingly provided.In one example, from edge 108 Both sides drill out via 112, such as are drilled from the upper surface 203 of semiconductor devices 100 and basal surface 205.In another example, Multiple vias 112 are drilled out from the one or both sides of semiconductor devices 203,205.In another example, drilled out after stacking Via 112.Therefore, via 112 is easier to be alignd by the tube core 102 previously stacked.With forming multiple individually vias, simultaneously And then stack and the via that aligns (for example, tube core) on the contrary, it is single effectively operation in drilled, this is closed in a single step And the formation of via.

As described above, each die assemblies in die assemblies 201 include tube core 102 and adjacent die 102 is formed Redistributing layer 202.As illustrated, redistributing layer 202 extends beyond area occupied (for example, the horizontal occupancy face of tube core 102 Product), and extend in edge 108.For example, in one example, tube core 102 is encapsulated in mold compound 200, such as In panel frame described herein.After being received into panel frame, mold compound 200 is incorporated into panel frame In and make to harden around its each tube core in tube core 102.Recompose-technique is used for along each pipe in tube core 102 Core provides the conductive trace of redistributing layer 202.For example, as shown in Figure 2, redistributing layer 202 in die assemblies 201 each Die assemblies multiple edges 108 on correspondingly extended laterally from multiple tube cores 102 and pass through the multiple edge 108.Thus redistributing layer 202 provides " being fanned out to " structure, it allows each tube core and semiconductor devices 100 in tube core 102 The distributed interconnection (for example, by via 112) of interior other tube cores and ball grid array 114.Therefore, the redistributing layer being fanned out to 202 cooperate with the multiple vias 112 provided through edge 108, correspondingly to make the overall height of semiconductor devices 100 minimum Change, and provide and be directly connected between each tube core in tube core 102 simultaneously, and below offer and first die 104 Ball grid array 114 is directly connected to.Redistributing layer provides the conductive trace extended laterally from tube core, then will by via 112 The tube core interconnection.In other words, via 108 and redistributing layer 202 provide the interconnection being contained in edge 108, without Larger die cap (for example, for encapsulating free lead wire in addition).

As further shown in fig. 2, before stack chip, laterally and at the top of multiple tube cores 102 above carry For mold compound 200 (for example, forming the dielectric resin of corresponding polymer).In another example, with along pipe Mold compound 200 is provided on the side of the opposite multiple tube cores 102 in the upper surface of each tube core in core 102.Moldingization Compound 200, which extends laterally to form, has the edge 108 that 110 are extended laterally relative to the edge of tube core 102.As it was previously stated, Mould after multiple tube cores 102 (as described in this article in the flat panel with wafer or panel construction), from face Plate cuts out multiple tube cores 102, and its operability is tested, and is then stacked to such as semiconductor devices 100 Stacked structure Fig. 2 shown in structure in.In another example, weight is being separated and formed from original Silicon Wafer Before the die panel (described herein) of structure, multiple tube cores are tested.

Each tube core in tube core 102 utilizes the bonding provided between each die assemblies in die assemblies 201 The layer of agent 204 or other mating substances is coupled to each other.As shown in Figure 2, bonding agent 204 and each pipe in tube core 102 Core is alignd, and tube core 102 is maintained in alignment structures.In one example, after stack chip 102, through partly leading Body device 100 drills out multiple vias 112, with from there through the redistributing layer 202 of each die assemblies in die assemblies 201 Interconnection between each tube core in tube core 102 is provided.

In another example, in fig. 2 in shown structure, before stack chip component, respectively in die assemblies Via 112 is formed in each die assemblies in 201.Therefore, via 112 is made to align in stacking process, with correspondingly true The communication between each die assemblies (and ball grid array 114) in keeping core assembly 201.In one example, via 112 conductive materials filled with copper etc., sputter or provide the conductive material by vapour deposition, with interconnecting semiconductor device Each tube core 102 of part 100 and tube core 102 is connected with ball grid array 114.

Referring again to Fig. 2, as previously described herein, each via in via 112 is shown in edge 108, and It is spaced relative to each tube core in tube core 102.That is, tube core 102 passes through the edge 108 by extending laterally The conductive via 112 of offer interconnects.Tube core is provided in lateral part by each die assemblies in die assemblies 201 Interconnection between 102, by the connection between each tube core and ball grid array 114 in tube core 102 be merged into via 112 with And the redistributing layer 202 (for example, transverse edge 108) being fanned out to from each tube core in tube core 102.Therefore, correspondingly avoid The parts of other semiconductor devices, for example, stacking the conductive substrates that are provided below of tube core and provide for encapsulating and protecting The wire bonding between each tube core and underlying substrate in the die cap and tube core of pillar core.Alternatively, by partly leading Body device 100, each tube core in tube core 102 is moulded using mold compound, is laterally prolonged so as to be provided for redistributing layer 202 Stretch edge 108 and the via 112 laterally to set provides space.Accordingly, with respect to using wire bonding and underlying substrate (with And wire bonding at the top of on corresponding die cap) semiconductor devices other structures Z height, make semiconductor devices 100 hang down Straight height or Z height minimize.

Further, since via 112 is provided through edge 108, thus via 112 is easier to be formed in semiconductor devices In 100.For example, at least some examples, via is provided through the silicon of tube core 102.Silicon is more difficult to be drilled through because it is frangible and Harder (such as with higher modulus of elasticity).However, for the polymer in the mold compound 200 of semiconductor devices 100 Softer material is provided for the convenient drilling of each tube core in tube core 112 (relative to silicon).The softer material at edge 108 It correspondingly ensure that and be easily formed via in semiconductor device 100, and therefore, conductive material is easy to be deposited on via 112 It is interior, to interconnect each redistributing layer in the redistributing layer 202 of the respective dies 102 of die assemblies 201.Similarly, due to Via 112 facilitates penetration of the mold compound at edge 108 and formed, so that for example forming the stacked structure of tube core 102 Before or after damage to semiconductor devices 100 it is minimum.By contrast, bored through the silicon of one or more silicon dies There is problem in hole, because the chip of the semiconductor in tube core or damage are risky.One example of mold compound 200 include but Epoxy resin is not limited to, it includes one or more additives, and the additive is configured as adjusting the property (example at edge 108 Such as, the encapsulation of semiconductor devices 100) required with meeting to encapsulate.For example, epoxy resin includes additive, with adjust modulus of elasticity, One or more of thermal coefficient of expansion, solidification temperature, hardening time, glass transition temperature, thermal conductivity etc. property.

The technique that Fig. 3 shows the manufacture of the semiconductor devices for all semiconductor devices 100 as shown in figs. 1 and 2 An example a series of schematic diagrames process chart.In the first stage in 301, shown in monolithic semiconductor wafer 300 Multiple tube cores 302.For example, multiple tube cores 302 are formed in Silicon Wafer, it is such as previously known (by the mask of wafer and The mode of etching).The tube core 302 in Silicon Wafer 300 is detected to determine which tube core is exercisable (no manufacture or performance deficiency Operable tube core).Cutting semiconductor wafer 300 is correspondingly to separate each tube core in tube core 302.Optionally, cutting After cutting and then separating, tube core 302 is detected.

Exercisable tube core 306 is separated from remaining tube core 302, and in the stage 303, by exercisable tube core 306 are arranged in panel frame 304.As shown in Figure 3, in one example, shown in panel frame 304 and stage 301 Semiconductor crystal wafer 300 has essentially similar structure.In another example as described herein, panel frame 304 has another A kind of shape, such as square or rectangle.Multiple exercisable tube cores 306 are assembled in panel frame 304, and form weight The die panel 308 of structure.For example, the mold compound of the resin for hardening into dielectrical polymer etc. is supplied to panel frame Frame 304.Mold compound hardens around each operable tube core in operable tube core 306, to correspondingly form in Fig. 2 The die assemblies 201 (including tube core 102 and corresponding edge 108) of shown separation.Structure shown in the stage 303 In, the die panel 308 of reconstruct is easy to stack, such as to form one or more semiconductor devices previously described herein 100。

In another example, (for example, after operable tube core 306 has been moulded) after the die panel of reconstruct is formed, Form the redistributing layer 202 of each tube core in tube core 306.For example, manufacture and photoetching are used in the He of mold compound 200 The conductive trace of redistributing layer 202 is etched on tube core 306.It is fanned out to as it was previously stated, redistributing layer 202 has, it is configured as Extend (for example, seeing Fig. 2) on the area occupied of operable tube core 306 and edge 108.

With reference now to the stage 305, in the decomposition texture for each die panel being stacked in multiple die panels 310 Show reconstruct die panel 308.As illustrated, the operable tube core of each panel in multiple reconstruct die panels 310 306 are shown in essentially similar structure, and are correspondingly alignd between each in reconstructing die panel 310. That is by for example including first and second reconstruct die panels 312,314 die panel 310 in each die panel Operable tube core 306 align, with the later step of technique, when the tube core of stacking separates (cutting), correspondingly provide The semiconductor devices of stacking.As it was previously stated, in one example, applied between each of multiple reconstruct die panels 310 viscous Agent 204 is connect, to ensure the coupling between multiple reconstruct die panels 310, including keeps the alignment of tube core therein.

In the stage 307, multiple vias 112 are formed in multiple reconstruct die panels 310 of stacking.For example, such as the stage 307 Shown in, multiple reconstruct die panels 310 in the structure that stack of panels component 316 includes stacking and is bonded.Therefore, right Multiple tube cores 102 of align panel 310 (it should correspond to operable in the structure of the arrangement of the device 100 shown in Fig. 1 and 2 Tube core 306).Each tube core (306 shown in Fig. 3) being extended in the horizontal in tube core 102 edge 108 (including Redistributing layer 202 shown in Fig. 2) in formed via 112.

In one example, via 112 is formed in batch process, such as including through every in corresponding tube core 102 The edge 108 of one tube core is drilled.That is, through stack of panels. in stack of panels component 316 (before cutting) Component 316 drills out multiple vias 112, each semiconductor in semiconductor devices to accordingly contribute to the single fabrication stage The quick formation of via 112 in device.In another example, stack of panels component 316 is cut into multiple semiconductor devices Part 100.Hereafter, the semiconductor devices 100 of multiple separation is drilled respectively and extends through the via 112 at edge 108 to be formed. After via 112 is formed, the conductive material sputtering or vapour deposition of such as copper are in the passage of via 112, to be electrically coupled tube core 306 (for example, redistributing layer 202 by edge 108).

As shown in the stage 309, ball grid array 114 (also showing in fig 1 and 2) is additionally provided.In one example, with Similar to the mode in stage 307, while in the stack of panels component 316 shown in the stage that remains at 307, along semiconductor The ball grid array 114 for each semiconductor devices that device is formed in semiconductor devices 100.Optionally, after dicing, such as cut After being segmented into the semiconductor devices 100 shown in the stage 309, ball grid array 114 is formed along semiconductor devices 100.

Referring again to the stage 309, the semiconductor devices 100 of completion is shown as with the tube core 102 stacked and extended through Cross the via 112 at edge 108.Also show ball grid array 114 on the bottom of semiconductor devices 100, for example, with redistributing layer Coupling, the redistributing layer are associated with first die 104 (as shown in Figure 2).

Technique shown in Fig. 3 has illustratively provided multiple semiconductor devices 100, such as the device shown in Fig. 1 and 2 Part.Because each in panel frame 304 and corresponding reconstruct die panel 310 only include operable tube core 306, therefore base The semiconductor devices 100 of tube core 102 be damaged including one or more or defective is avoided in sheet.That is, again With reference to the stage 305, previously tested in the operable tube core 306 included in each of multiple reconstruct die panels 310 Each, and know that it is exercisable.Therefore, semiconductor devices 100 is correspondingly as caused by the panel assembly 316 stacked It is exercisable.Relative to for example using the monolithic semiconductor wherein with operable, defective and impaired semiconductor The existing manufacturing technology of wafer, the technique shown in figure make defective or impaired semiconductor minimum or avoid bag Containing defective or impaired semiconductor.In previous manufacturing technology, defective or impaired semiconductor is included in In the device of completion, available device overall in other cases is caused to go out of use.In other words, work as described herein is utilized Skill, the defective or impaired pipe of the one or more (for example, multiple) that is provided in one or more semiconductor crystal wafers 300 Core 302 will not enter in the semiconductor devices 100 fully operational in other cases manufactured as described above.

Therefore, the yield of semiconductor devices 100 is substantially higher than exercisable and defective or impaired using including Other techniques of the whole semiconductor crystal wafer 300 of tube core.In addition to higher yield, such as the via 112 through edge 108 Configuration provides tube core 102 in each tube core between direct interconnection, without larger die cap and substrate, and in lead Larger die cap and substrate are then needed in the case of the semiconductor devices of engagement.Accordingly, with respect to by wirebond interconnections with And other semiconductor devices that the mode of substrate is formed, as caused by the technique shown in Fig. 3 semiconductor devices 100 have compared with Reliable operable characteristic and the vertical height (Z height) minimized.

Referring now to Figure 4, provide two replacing as the stage 303 and 305 shown in Fig. 3 of other stage 403,405 Generation.For example, relative to the crystal circle structure of the panel frame 304 shown in the stage 303, the panel frame 400 shown in Fig. 4 has Square or rectangle (for example, non-circular) structure.Therefore, operable tube core 306 is arranged in such as with just by panel frame 400 In the grid of the pattern of square rectangular configuration.Then the reconstruct die panel 402 shown in the stage 403 is stacked to as in Fig. 4 Stage 405 shown in multiple reconstruct die panels 404 in.As in Fig. 4 further shown in, multiple reconstruct die panels 404 comprise at least the first and second reconstruct die panels 406,408.

Then, in a manner of multiple reconstruct die panels 404 with being provided in stacked structure are essentially similar in implementing Fig. 3 Previously described technique.That is, in one example, through each pipe being extended in the horizontal in tube core 102 Multiple edges 108 of core form via 112.In one example, (example while tube core 102 is maintained in stacked structure Such as, before being cut), via 112 is formed in edge 108.In a similar way, in the stage 307, by semiconductor devices While 100 the first reconstruct die panel 406 is maintained in the stack of panels component shown in Fig. 3, by ball grid array 114 It is applied to the first reconstruct die panel 406.In another example, as previously described herein, via 112 and ball grid array 114 form on single semiconductor devices 100, such as multiple reconstruct die panels 404 in semiconductor devices 100 from stacking After cutting out.

Fig. 5 shows the semiconductor devices for including the wire bonding between underlying substrate 506 and the tube core 502 of device 500 500 cross-sectional view.As in Fig. 5 further shown in, by one or more lead 504 with it is every in tube core 502 One tube core engages and extends through semiconductor devices 500 (for example, passing through die cap 510), each tube core in tube core 502 It is connected with substrate 506.It is as illustrated, at least some by extending to lining from corresponding tube core 502 first in a plurality of leads 504 Bottom 506 (substrate includes multiple conductive traces) and then extend to one or more from substrate 506 by additional lead 504 Individual other tube cores 502, and the interconnection between each tube core in tube core 502 is provided.As in Fig. 5 further shown in, edge The opposed surface for substrate 506 provides ball grid array 508, and the lead 504 by extending to tube core 502 from substrate 506 will Ball grid array 508 interconnects with tube core.

Compared with the component shown in Fig. 5, semiconductor devices 100 (Fig. 1 and 2) described herein includes stacked structure In multiple tube cores 102, the stacked structure includes from each tube core 102 extending laterally and (extending laterally 110 for example, seeing) Multiple edges 108 extended laterally.Edge 108 provides the molding of the drilling and the formation that are arranged to via 112 therein Compound, resin etc..As previously described herein, each in die assemblies 201 formed with redistributing layer 202, such as To provide the fan-out structure of the conductive trace of the horizontal area occupied of each tube core extended beyond in tube core 102.Therefore, it is sharp With the via 112 for extending through redistributing layer 202, in the compact lateral attitude relative to tube core 102 (for example, at edge 108 In) provide electrical interconnection between each tube core in tube core 102.In the horizontal stroke adjacent with each tube core in tube core 102 Interconnection between tube core is provided into space, the semiconductor devices shown in Fig. 5 is accommodated without additionally needing big die cap 510 500 a plurality of leads 504.In addition, extend between each of via 112 in tube core 102.For example, via 112 at two or Extend between more die 102, be directly connected to providing between tube core 102, and therefore avoid centre as shown in Figure 5 Substrate 506.

In addition, the semiconductor devices 100 shown in Fig. 1 and 2 need not be used to input from device 100 or defeated to device 100 The substrate 506 gone out.Alternatively, it is configured as including the tube core 102 interconnected with via 112 and the device 100 of redistributing layer 202 The ball grid array 114 coupled by the redistributing layer 202 along first die 104 provides input and output.In other words, Fig. 1 and 2 Shown in semiconductor devices 100 in no longer need substrate 506 and die cap 510 shown in Fig. 5.Alternatively, from tube core 102 The edge 108 extended laterally is that the via 112 for including the redistributing layer 202 of its conductive trace and being drilled out through edge 108 carries Space is supplied.Therefore, by using semiconductor devices 100, (needed larger relative to the semiconductor devices 500 shown in Fig. 5 Die cap 510 and substrate 506), (Z height) realizes space saving in vertical direction.In addition, the semiconductor shown in Fig. 1 Device 100 includes passing through the relatively straightforward connection of the via 112 between each tube core in tube core 102 (without middle lining Bottom 506).This is arranged between tube core 102 and the ball grid array 114 associated with the redistributing layer 202 of first die 104 (see Fig. 2) provide direct and therefore very fast and relatively reliable data transfer.

Referring now to Figure 6, for structure presented herein (such as using shown in Fig. 1 and 2 device 100 Structure) a variety of semiconductor devices provide Z height and compare form.As described herein, semiconductor devices 100 include one or Multiple die assemblies 201, each die assemblies have tube core 102, edge 108 and extend to redistributing layer 202 through edge 108 One or more vias.Each tube core group is shown in the row of " semiconductor devices with the via in edge " of form The Z height 602 of corresponding mold compound used in the edge 108 of part and each die assemblies.Total Z height 602 is right Ying Yu be used for the die assemblies 201 of the stacking of specific type of encapsulation quantity (each there is about 25 microns of height, and Mold compound has 10 microns of height).Semiconductor devices 100 in ascending order, that is, include the first of singulated dies component Device (single die encapsulate or SDP), second device (dual-die encapsulates, DDP) with two die assemblies, etc. (for example, QDP includes four components, and ODP includes eight components, and HDP includes 16 components).

The semiconductor devices including wire bonding and substrate is provided in the first row of form (see partly leading shown in Fig. 5 Body device 500) corresponding Z height 604.As illustrated, the die assemblies Z height of wire bonding device is 25 microns, and The die cap and spacing Z height of each die assemblies change according to the quantity of the die assemblies of device.Beneath a line is shown often Total Z height of one device, it is multiplied by the number of the die assemblies of device based on die assemblies Z height and die cap and spacing Z height Amount.

As shown in Figure 6, (such as wrapped relative to the corresponding total Z height of the corresponding device with the arrangement shown in Fig. 5 Include wire bonding, die cap and substrate), there is being fanned out in the device of redistributing layer 202 comprising the via 112 in edge 108 The total Z height 602 of each is smaller.The saving of the Z height of each in corresponding die assemblies 201 is delivered to two Or more the stacking of die assemblies semiconductor devices 100.That is, relative to use wire bonding, die cap and substrate The respective dies component used in encapsulation, there is the device comprising more than two tube core of structure described herein (for example, tube core group Part 201) Z height of each that adds in the die assemblies 201 of stacking saves.

Fig. 7 shows the Stacket semiconductor device for manufacturing all semiconductor devices 100 as previously described herein One example of method 700.In the method 700 of description, one or more parts as described herein, feature, function etc. with reference to. In the case of convenient, part and the feature with reference with reference to.Reference is exemplary, and non-dedicated. For example, the element, as described herein other that part, feature, function described in method 700 etc. includes but is not limited to accordingly to number Individual features (numbering or unnumbered) and their equivalent.

At 702, method 700 is included in formation edge 108 on the tube core 106 of first die 104 and second.Edge 108 exists It is horizontal to extend upwardly away from the first and second tube cores 104,106.For example, as shown in fig. 1, multiple edges 108 are horizontal according to edge Extension 110 extends from each in corresponding tube core.

At 704, the second tube core 106 is stacked in first die 104.For example, as shown in Figure 2, for example, being tied stacking In structure, including the die assemblies 201 of corresponding tube core 102 and corresponding redistributing layer 202 are coupled.In an example In, the die-stack of such as the second tube core 106 is included at least in the first and second tube cores 104,106 in first die 104 Between surface coating adhesive, so that tube core correspondingly to be bonded together in laminated construction.

At 706, stack Fig. 2 shown in structure in die assemblies 201 after, through edge 108 drill out one or Multiple vias 112.One or more vias 112 at least extend between the first and second tube cores 104,106.In another example In, method 700 is included before stacking, for example, shown in the stage 303 that multiple tube cores 102 are maintained in such as Fig. 3 When in the panel frame of panel frame 304, one or more vias 112 through edge 108 are drilled out.Then, by multiple tube cores 102 are arranged in laminated construction, and corresponding via 112 according to multiple tube cores 102 (for example, die assemblies 201) relative to The mode being in alignment with each other is alignd.After being drilled to one or more vias 112, such as by being vapor-deposited, sputtering Or plating, conductive material is applied via via 112, correspondingly to interconnect tube core 102.For example, multiple vias 112 by with pipe Each associated redistributing layer 202 in core 102 provides interconnection.

In addition, in another example, one or more vias 112 provide tube cores 102 and along with first die 104 Interconnection between the ball grid array 114 of associated redistributing layer 202.

Referring now to Figure 8, provide another example of the method 800 for manufacturing the semiconductor devices 100 stacked. During description method 800, one or more parts as described herein, feature, function etc. with reference to.In the case of convenient, reference There is the part and feature of reference.Reference is exemplary, and non-dedicated.For example, described in method 800 Element that part, feature, function etc. include but is not limited to accordingly to number, other individual features as described herein (numbering or It is unnumbered) and their equivalent.

Referring again to Fig. 8, at 802, method 800 includes selection tube core 302 to obtain multiple operable tube cores, such as schemes The operable tube core 306 shown in stage 303 in 3.Multiple operable tube cores 306 are detected or tested to determine its operability. At 804, the first reconstruct die panel 308 is at least formed.

In one example, at 806, forming the first reconstruct die panel (and additional dies panel) includes choosing Multiple operable tube cores 306 be arranged in panel frame 304.In another example, by the cloth of operable tube core 306 of selection Put in non-circular geometric face plate framework, such as the panel frame 400 shown in Fig. 4.At 808, in (or the face of panel frame 304 Plate framework 400) in multiple operable surrounding moulded resins of tube core 306, with formed first reconstruct die panel 308.As herein Previously described, edge 108 is formed in resin, and each from multiple operable tube cores 306 extends laterally.

In one example, at 804, the technique that die panel is reconstructed for being formed is recycled and reused for additional dies face Plate, distinguish multiple reconstruct die panels 312 or 404 shown in figures 3 and 4 therefore to produce.As described earlier in this article, then Multiple reconstruct die panels are stacked into the corresponding square or non-circular structure shown in stack of panels component 316 and Fig. 4, A series of pipes stacked are provided with each (in Fig. 3 shown in the stage 309) in the semiconductor devices 100 for caused by before cutting Core 102.

When in stack of panels component 316, such as shown in Fig. 3 stage 307, through including in semiconductor device 100 Die assemblies 201 in the associated edge 108 of each tube core form multiple vias 112.For example, shown in 307 When in stack of panels component 316, multiple vias 112 are formed in batch process, correspondingly to reduce in other discrete semiconductor The time needed for via 112 is produced during device 100.After via 112 is formed, semiconductor is cut out from stack of panels component 316 Device 100, to form semiconductor devices that is shown in the stage 309 in Fig. 3 and being further shown specifically in fig 1 and 2 100。

In addition, in another example, while semiconductor devices 100 is still a part for stack of panels component 316, Ball grid array 114 is supplied to (shown in Fig. 1 and 2) associated with each semiconductor devices in semiconductor devices 100 First die 104.In another example, after semiconductor devices is cut out from stack of panels component 316, via is formed 112 and the ball grid array 114 associated with each semiconductor devices in semiconductor devices 100.

Fig. 9 shows another example of the semiconductor devices 900 including multiple tube cores 102 with respective edges 904. As shown in Figure 9, (for example, displacement or hierarchic structure) provides tube core 102 in cross structure.For example, in die assemblies 902 Each be displaced relative to each other, to form a series of tube cores staggeredly in semiconductor devices 900.As shown in Figure 9, manage Each in core 102 is displaced relative to each other, and the one or more of each tube core in tube core 102 are included with exposure and are engaged At least one side of pad 905.In one example, such as according to tube core displacement 906 each tube core 102, tube core displacement are shifted 906, which correspondingly make tube core be respectively relative to adjacent tube core, interlocks.In another example, the progress of tube core 102 different brackets (and Optionally different directions) displacement, correspondingly to expose one or more bond pads 905 according to displacement.That is, one Individual or multiple tube cores 102 according to the position of respective bond pad 905 and with one or more larger or smaller grades or Shifted in different directions.

As shown in Figure 9, each on the equidirectional that cross structure (staged) is provided in staggered pipe core, with phase Answer the corresponding engagement of each (in addition to the tube core 102 of the bottommost of semiconductor devices 900) in ground exposure tube core 102 Pad 905.As described earlier in this article, each tube core in tube core 102 is included in corresponding die assemblies 902.As schemed Show, each die assemblies in die assemblies 902 include one of tube core 102 and each tube core in tube core 102 or Multiple corresponding edges 904.

As in Fig. 9 further shown in, for example, using towards the bonding agent provided on the surface of adjacent tube core 102 908, each tube core in multiple tube cores 102 is engaged with each other.Bonding agent 908 keeps each tube core in tube core 102 In cross structure, and tube core displacement 906 as shown in Figure 9 (example of tube core displacement) is correspondingly kept, so that will Bond pad 905 is maintained in exposed structure, for final interconnection.In one example, in such as Fig. 2 is coated previously Before the mold compound of shown mold compound 200 etc, multiple tube cores 102 are bonded together using bonding agent 908.Such as Preceding described, mold compound 202 is solidified into dielectrical polymer, and is correspondingly each tube core in die assemblies 902 Component provides edge 904.After each being bonded in tube core 102, by mold compound 202 coated in the tube core 102 stacked Around, to correspondingly form the intergrade of semiconductor devices 900.

Drill out one or more vias 912 through one or more edges 904, with correspondingly provide tube core 102 with it is corresponding Redistributing layer 910 between interconnection, one or more tube cores 102 of the redistributing layer 910 and neighbouring ball grid array 114 (for example, tube core of the bottommost shown in Fig. 9) is associated.As shown in Figure 9, each via in via 912 is with being used for The corresponding bond pad 905 for being covered each by tube core 102 couples.The multiple mistakes associated with each tube core in tube core 102 Hole 912 correspondingly extends through the one or more edges 904 being associated with corresponding die assemblies 902 from bond pad 905. That is, the uppermost tube core 102 of semiconductor devices 900 includes the corresponding edge for extending through lower die 102 One or more vias 912.

(for example, by machine drilling, photoetching, laser drill etc.) after via 912 is formed, there is provided similar in Fig. 2 The redistributing layer 910 of shown redistributing layer 202, at least one tube core 102, such as corresponding to the phase of ball grid array 114 The tube core 102 of the bottom of adjacent semiconductor devices 900.In one example, redistributing layer 910 provides accounting in tube core 102 With the fan-out structure of the conductive trace extended on corresponding total area occupied of area and the tube core of stacking 102.Namely Say, as shown in Figure 9, the lower section extension of each tube core of the redistributing layer 910 in tube core 102, and conductive trace is provided For being interconnected with via 912, via 912 extends through edge from the respective bond pad 905 of each tube core in tube core 102 904.In another example, after redistributing layer 910 is formed, ball grid array 114 is applied to along redistributing layer 910 and partly led Body device 900, connected with providing the input of semiconductor devices 900 and output.

Referring now to Figure 10, provide the side for forming semiconductor (for example, semiconductor devices 900 shown in Fig. 9) Another example of method.As described above with the method shown in Fig. 5, it is a series of signal the sexual stages 1001,1003, 1005th, method is shown in 1007.At 1001, to the multiple pipes cut out from one or more monolithic semiconductor wafers The operability of core 102 is tested.Then exercisable tube core 102 (zero defect or damage) is assembled into die stack stack In 1002.For example, it is bonded the tube core 102 of one or more die stack stacks 1002.As shown in the stage 1001, die stack stack 1002 have cross structure (ladder, displacement etc.), and it correspondingly exposes each in the tube core 102 of die stack stack 1002 Bond pad 905 at least one surface of tube core.As described above, in another example, according to respective bond pad 905 position and quantity, tube core 102 is shifted with one or more different brackets or direction.

With reference now to the stage 1003 in Figure 10, each die stack stack in die stack stack 1002 is arranged at face In plate framework 1004, panel frame 1004 can accommodate the system of each in die stack stack 1002 including size and shape Row cavity.It is multiple in panel frame 1004 after die stack stack 1002 is arranged in the cavity of panel frame 1004 The surrounding of die stack stack 1002 applies mold compound, to form the edge 904 of the die assemblies 902 of previously illustrated in Fig. 9.Such as this Described in text, in one example, mold compound 202 is resin, and its formation has compared with the material (for example, silicon) of tube core Compared with the dielectrical polymer of low elastic modulus.Reconstruct die panel 1006 is formd with reference to panel frame 1004, including more The die stack stack of individual molding.Stage 3 shows circular (wafer shape) panel frame 1004.In another example, face Plate framework has all different shapes of rectangle or square as shown in Figure 4.

As shown in the stage 1003, the die assemblies 902 formed by die stack stack 1002 are included from every in tube core 102 The edge 904 that one tube core extends laterally.As shown in the structure, die stack stack 1002 is interlocked in mold compound 202. Each edge in the edge 904 of corresponding tube core 102 is according to each pipe in the tube core 102 in die stack stack 1002 The deviation post of core and correspondingly changed on lateral dimension.By the displacement of tube core and the face of bond pad 905 of exposure To the bottom (as shown in Figure 10) of the die stack stack 1002 towards the edge 904 of lower die 1002.

At the stage 1005, multiple vias 912 are got into the edge 904 below bond pad 905, by tube core 102 Each interconnected with the redistributing layer 910 provided along one of tube core 102.For example, shown example in Fig. 10 In, the tube core (uppermost tube core is shown as in the inverted structure) of bottommost is provided with redistributing layer 910.Optionally, exist Formed before the conductive trace of redistributing layer 910, multiple vias 912 are got into edge 904, led receiving with correspondingly forming The passage of electric material, to be interconnected with the redistributing layer 910 subsequently formed.Conductive material is coated onto the passage of via 912 with final The redistributing layer of multiple tube cores 102 of die stack stack 1002 and semiconductor devices 900 is interconnected.In another example, Redistributing layer 910 is formed before the drilling of via 912.

At the stage 1007, by ball grid array 114 is applied to the redistributing layer 910 previously formed in the stage 1005 come Complete semiconductor devices 900.As shown in the stage 1007, then semiconductor devices is cut out from reconstruct die panel 1006 900.Multiple semiconductor devices 900 are cut out from same reconstruct die panel 1006.

Such as foregoing semiconductor devices 100, the semiconductor devices 900 shown in Fig. 9 and 10 provides and redistributing layer 910 (for example, redistributing layers 910 associated with the tube core 102 and die stack stack 1002 of bottommost) are directly connected to.It is multiple The offer of via 912 is directly connected to redistributing layer 910, is correspondingly included and is encapsulated from tube core without other larger die cap In multiple wire bondings of substrate (being more than redistributing layer 910) for extending to below die stack stack of each tube core.Tube core The cross structure of stacked body 1002 exposes the bond pad 905 of one or more tube cores 102, and so as to allow from seam welding The via 912 that disk 905 extends through edge 904 interconnects each tube core in corresponding tube core 102 with redistributing layer 910. Compared to the die cap of other relatively deep (thicker) needed for reliably package lead, such as 504 shown in Fig. 5, bond pad The mold compound for being directly connected to allow shallow-layer provided by via 912 between 905 and redistributing layer.

In addition, as previously described, because compared with the relatively hard materials of the silicon of tube core 102, via the softer of mold compound 202 Material (compared with low elastic modulus) carries out the drilling through semiconductor devices 900, thus by through mold compound 202 (electricity Dielectric polymers) via 912 is provided so that and the damage to semiconductor devices 900 is minimum.In addition, utilize the side shown in Figure 10 Method, form one of technique and tube core 102 of die stack stack 1002 of redistributing layer 901 and isolate.For example, as herein It is described, redistributing layer 910 is supplied to the tube core 102 of the bottommost of die stack stack 1002.Therefore, via 912 passes through tube core The transverse edge 904 of the tube core 102 of stacked body 1002 extends to the redistributing layer 910 associated with bottommost tube core 102.So as to Redistributing layer 910 is by the interconnection of each redistributing layer in multiple redistributing layers associated with each tube core 102 in addition The single redistributing layer also provided with the interconnection of ball grid array 114 is provided.In another example, the tube core of bottommost 102 include being confined to multiple redistributing layers (for example, multiple adjacent layers 910) of tube core, and cover the pipe of bottommost tube core 102 The remainder of dice of core 102 interconnects with via 912.In another example, each tube core in tube core 102 include it is respective again Distribution layer 910, and tube core 102 is interconnected by redistributing layer 910 and via 912.

Include the example of the electronic equipment using the semiconductor devices 100,900 as described in present disclosure, to show Go out the example of the equipment application of the higher level of present disclosure.Figure 11 is the block diagram of electronic equipment 1100, and it, which is included, utilizes At least one semiconductor devices constructed according to the manufacture method of at least one embodiment of present disclosure and structure.Electronics Equipment 1100 is only an example of the electronic system for the embodiment for having used present disclosure.The example bag of electronic equipment 1100 Include but be not limited to, personal computer, tablet personal computer, mobile phone, game station, MP3 or other digital music players etc.. In this example, electronic equipment 1100 includes data handling system, and it includes system bus 1102, with the various portions of coupled system Part.System bus 1102 provides communication link in the various parts of electronic equipment 1100, and may be implemented as single total Line, the combination of bus are implemented in any other suitable manner.

Electronic building brick 1110 is coupled to system bus 1102.Electronic building brick 1110 can include the group of any circuit or circuit Close.In one embodiment, electronic building brick 1110 includes can having any kind of processor 1112.As used herein , " processor " represents any kind of computing circuit, such as, but not limited to microprocessor, microcontroller, sophisticated vocabulary meter Calculate (CISC) microprocessor, Jing Ke Cao Neng (RISC) microprocessor, very long instruction word (VLIW) microprocessor, at figure Manage device, digital signal processor (DSP), the processor or process circuit of polycaryon processor either any other type.

It is custom circuit, application specific integrated circuit (ASIC) that the other types of circuit in electronic building brick 1110, which can be included in, Deng for example, for example being moved for one or more of wireless device circuit (such as telecommunication circuit 1114), the wireless device Phone, personal digital assistant, portable computer, two-way radio and similar electronic system.IC can perform any other The function of type.

Electronic equipment 1100 (for example, driver or flash memories of such as solid-state drive) can also include outside Memory 1120, it can correspondingly include the one or more memory components for being suitable for special applications, such as arbitrary access The main storage 1122, one or more hard disk drives 1124 or management such as CD (CD) of memory (RAM) form, One or more drivers of the removable medium 1126 of flash-storing card, Digital video disc (DVD) etc..

Electronic equipment 1100 can also include one or more display devices 1116, one or more loudspeakers 1118, key Disk or controller 1130, the keyboard or controller 1130 can optionally include mouse, tracking ball, touch-screen, voice Identification equipment allows system user to enter information into electronic equipment 1100 and from the receive information of electronic equipment 1100 Any other equipment.

In order to preferably show method and apparatus disclosed herein, the non-limiting row of embodiment are there is provided herein Table：

Example 1 is to be directed to the device for the method for being used to manufacture the semiconductor devices stacked, and it includes：In first die and Edge is formed on two tube cores, the edge is extended the first and second tube cores in the horizontal；By the second die-stack first On tube core；And in heap poststack, one or more vias are drilled out through edge, one or more of vias are first and second Extend between tube core.

In example 2, the subject content of example 1 optionally can fill one or more mistakes using conductive material Hole, so that the first and second tube cores are electrically interconnected.

In example 3, the subject content of any one in example 1-2 can optionally include：Wherein, edge is formed It is included on first die and the second tube core and forms dielectric portion, the edge is formed using dielectric portion.

In example 4, the subject content of any one in example 1-3 can optionally include：Wherein, electricity is formed to be situated between Matter is partly comprised in moulded resin around first die and the second tube core, and edge is formed using resin.

In example 5, the subject content of any one in example 1-4 can optionally include：Form the first reconstruct pipe Core panel, the first reconstruct die panel are included in individual tube core more than first moulded in panel frame, more than described first pipe Core includes first die；And the second reconstruct die panel is formed, the second reconstruct die panel is included in another panel Individual tube core more than second moulded in framework, individual tube core more than described second include the second tube core；And edge is formed using electricity The periphery for the tube core that dielectric material is surrounded in the first and second reconstruct die panels.

In example 6, the subject content of any one in example 1-5 can optionally include：Choose more than described first Tube core in individual tube core and more than second individual tube cores, to ensure only to be used to exercisable tube core form the first and second reconstruct tube cores Panel.

In example 7, the subject content of any one in example 1-6 can optionally include：From the first and second weights The single stacked body of the tube core of the bonding of structure die panel separation first and second.

In example 8, the subject content of any one in example 1-7 can optionally include：Wherein, one is drilled out Or multiple vias are made up of one or more of laser drill, machine drilling or chemical etching.

In example 9, the subject content of any one in example 1-8 can optionally include：Wherein, through first The one or more vias drilled out with the second tube core are continuous.

In example 10, the subject content of any one in example 1-9 can optionally include：First or second One or more redistributing layers of conductive trace, one or more mistakes are formed on one or more of tube core or the edge Hole communicates at edge with conductive trace.

In example 11, the subject content of any one in example 1-10 can optionally include：Wherein, by first Die-stack includes interlocking the second tube core relative to first die on the second tube core, and with exposure, at least one of the second tube core connects Close pad.

In example 12, the subject content of any one in example 1-11 can optionally include：Wherein, one is drilled out Individual or multiple vias include drilling out at least one via through the edge of first die, and at least one via extends to second At least one bond pad of tube core.

In example 13, the subject content of any one in example 1-12 can optionally include：Stacked for manufacturing Semiconductor devices method, it includes：Multiple operable tube cores in sort out tube core, to grasping for multiple operable tube cores Tested as property；And the reconstruct die panel of formation at least first includes：By multiple operable die arrangements of selection in face In plate framework, and moulded resin around multiple operable tube cores in panel frame, to form the first reconstruct tube core Panel, the edge formed using resin are extended laterally from each in multiple operable tube cores.

In example 14, the subject content of any one in example 1-13 can optionally include：Repeat to arrange And molding, to form the second reconstruct die panel, edge is extended the second the multiple of reconstruct die panel and grasped in the horizontal Make each tube core of tube core.

In example 15, the subject content of any one in example 1-14 can optionally include：First reconstruct is managed Core panel is coupled to the second reconstruct die panel；And drill out one or more in first and second reconstruct die panel of coupling Individual via, one or more vias are in the edge of multiple operable tube cores, and one or more vias are first and second Extend between reconstruct die panel.

In example 16, the subject content of any one in example 1-15 can optionally include：Wherein, by first Reconstruct die panel is coupled to the second reconstruct die panel and included the more of each in the first and second reconstruct die panels Individual operable tube core alignment.

In example 17, the subject content of any one in example 1-16 can optionally include：By first and second Reconstruct die panel is divided into multiple multilayer encapsulations, and each in multilayer encapsulation includes：First and second reconstruct die panels At least two tube cores in multiple operable tube cores, and at least one via in one or more vias.

In example 18, the subject content of any one in example 1-17 can optionally include：Wherein, coupling First and second reconstruct die panels in drill out one or more vias include drilled out through the edge of multiple operable tube cores One or more vias.

In example 19, the subject content of any one in example 1-18 can optionally include：Utilize conductive material One or more vias are filled, the first and second reconstruct die panels are electrically coupled.

In example 20, the subject content of any one in example 1-19 can optionally include：Wherein, formed extremely Few first reconstruct die panel is included in one or more of formation conductive trace on multiple operable tube cores and corresponding edge Individual redistributing layer, one or more vias are communicated at edge with conductive trace.

In example 21, the subject content of any one in example 1-20 can optionally include：Wherein, will choose Multiple operable die arrangements in panel frame include by multiple operable die arrangements of selection in panel frame In the die stack stack of one or more staggeredly, each die stack stack bag in the die stack stack of one or more staggeredly Two or more tube cores are included, and at least one of two or more tube cores is interlocked with adjacent tube core.

In example 22, the subject content of any one in example 1-21 can optionally include：Wherein, multiple Moulded resin is included in moulded resin around each in one or more die stack stacks staggeredly around operable tube core.

In example 23, the subject content of any one in example 1-22 can optionally include：Semiconductor devices, It includes：First die；The second tube core being stacked in first die；The every of the first and second tube cores is extended in the horizontal The edge of one；The first redistributing layer extended on the edge of first die and first die；And extend through corresponding Edge at least one of one or more vias, one or more vias are entered by edge and the first and second tube cores Row communication.

In example 24, the subject content of any one in example 1-23 can optionally include：Wherein, accordingly Edge is the resin edge of the molding moulded around corresponding first and second tube core, and one or more vias extend through mould At least one of the resin edge of system.

In example 25, the subject content of any one in example 1-24 can be optionally included in first and second The dielectric portion formed on each in tube core, dielectric portion include one or more edges, and one or more Individual via extends through dielectric portion.

In example 26, the subject content of any one in example 1-25 can optionally include：Wherein, one or Multiple vias and the first and second tube cores are spaced.

In example 27, the subject content of any one in example 1-26 can optionally include the second redistributing layer, It extends on the edge of the second tube core and the second tube core.

In example 28, the subject content of any one in example 1-27 can optionally include：First and second again Distribution layer provides the fan-out structure of conductive trace, and the conductive trace extends on the corresponding area occupied of the first and second tube cores And exceed, and one or more vias are communicated with the first and second redistributing layers.

In example 29, the subject content of any one in example 1-27 can optionally include：Wherein, via is After by the second die-stack in first die, the mistake drilled out that is formed at least one of corresponding edge Hole.

In example 30, the subject content of any one in example 1-29 can optionally be included comprising first and the Multiple tube cores of two tube cores, edge extend laterally from each tube core in multiple tube cores, multiple tube cores in stacked structure, and And one or more vias extend through at least two edges in the corresponding edge of multiple tube cores.

In example 31, the subject content of any one in example 1-30 can optionally include：Wherein, the second pipe Core interlocks with first die, and the second tube core includes the bond pad for depending at least one exposure staggeredly.

In example 32, the subject content of any one in example 1-31 can optionally include：Wherein, one or Multiple vias extend to the bond pad of at least one exposure of the second tube core through the edge of first die.

Each in these non-limiting examples is independent, or can be in any combination or permutation form with One or more of the other example is combined.

Above embodiment includes the reference to accompanying drawing, and which form a part for embodiment.Pass through act Example explanation, accompanying drawing are shown in which that the specific embodiment of present disclosure can be put into practice.These embodiments are also claimed herein For " example ".This example can include the key element in addition to those shown or described key elements.However, the present inventor The example of those shown in wherein only providing or described key elements is be provided.In addition, relative to particular example (or one Or many aspects), either relative to other examples (or in terms of one or more) shown or described herein, the present inventor Also contemplate shown in or the described any combination of those key elements (or for the use of one or more) or the example of arrangement.

In this document, as common in patent document, term " one " is used to include one or more than one, independent In " at least one " or any other example of " one or more " or use.In this document, term "or" is used to refer to Generation without exclusive or, make it that " A or B " include " A but be not B ", " B but be not A " and " A and B ", unless finger in addition It is bright.In this document, term " comprising " and " wherein " are used as being equal for the popular language of corresponding term "comprising" and " wherein " Thing.Equally, in following claims, term " comprising " and "comprising" are open, i.e. including except in the claims Listed key element after this term, system, equipment, product, composition, formula or the technique of key element in addition are regarded as Fall in the range of the claim.In addition, in following claims, term " first ", " second " and " the 3rd " etc. is only With marking, and not numerical requirements are applied to its object.

It is described above to be intended to rather than limited.For example, above-mentioned example (or one or more side Face) it can be used in combination with each other.For example, those of ordinary skill in the art can use other implementations after reading is described above Example.Summary is provided to follow 37C.F.R. § 1.72 (b), its property that reader will be enable to quickly determine technology disclosure Matter.The summary is submitted in the case where understanding the make a summary scope or meaning that are not used to explain or limit claim.Together Sample, in the embodiment more than, multiple features can be grouped together to simplify present disclosure.This should not be solved The open feature for being interpreted as being not claimed is essential for any claim.On the contrary, subject matter is less than specific Open embodiment whole features in the case of there may also be.Therefore, following claims is incorporated into specific implementation herein In mode, each of which item claim is by itself as single embodiment, and it is contemplated that this embodiment can be with It is bonded to each other in the form of various combinations or arrangement.With reference to appended claims and should be the claim entitle The full breadth of equivalent come determine scope of the present disclosure.

Claims

1. a kind of semiconductor subassembly, including：

First die component, the first die component include：

First die with first die upper surface and first die lower surface, and

The first edge extended laterally from the first die, wherein the first edge is included close to the first die upper table The first top edge face in face and the first lower limb face of the close first die lower surface, the first die lower surface and institute State input and output array of the first lower limb face close to the semiconductor subassembly；

The second die assemblies on the first die component, second die assemblies include：

The second tube core with the second tube core upper surface and the second tube core lower surface,

The second edge of second tube core is extended in the horizontal, wherein the second edge is included close to the described second pipe The second top edge face of core upper surface and the second lower edge face of the close second tube core lower surface, and

Multiple conductive traces, the multiple conductive trace are extended outwardly beyond the described second pipe towards second lower edge Core；

Wherein at least described first top edge face is the uppermost surface of the first die component and the second lower edge face It is the lowermost surface of second die assemblies, and the intervention of the multiple conductive trace is in the first top edge face and institute State between the second lower edge face；And

Extend through at least one one or more vias in the first edge and the second edge, it is one or Multiple vias pass through at least one with described the in the multiple conductive trace and the first edge or the second edge One tube core and second tube core communication.

2. semiconductor subassembly according to claim 1, wherein, the first edge and the second edge are molded into Moulded resin around corresponding first die and the second tube core.

3. semiconductor subassembly according to claim 1, including formed in the first die and second tube core Dielectric portion on each tube core, the dielectric portion include one or more edges, one or more of mistakes Hole extends through the dielectric portion.

4. semiconductor subassembly according to claim 1, wherein, one or more of vias and the first die and institute The second tube core is stated to be spaced apart in the horizontal.

5. semiconductor subassembly according to claim 1, wherein, the multiple conductive trace offer conductive trace is fanned out to knot Structure, the conductive trace extend beyond the area occupied of second tube core.

6. semiconductor subassembly according to claim 1, wherein, the via be by second die-stack described After in first die, at least one middle formation in the corresponding edge drills out via.

7. semiconductor subassembly according to claim 1, including it is multiple comprising the first die and second tube core Tube core, edge extend laterally from each tube core in the multiple tube core, and the multiple tube core forms stacked structure, and institute State one or more vias and extend through at least two edges in the corresponding edge of the multiple tube core.

8. semiconductor subassembly according to claim 1, wherein, second tube core interlocks relative to the first die, Second tube core includes the bond pad for depending at least one exposure staggeredly.

9. semiconductor subassembly according to claim 8, wherein, one or more of vias pass through the first die The edge extends to the bond pad of at least one exposure of second tube core.

10. semiconductor subassembly according to claim 1, wherein, the first die component includes other multiple conductive marks Line, multiple conductive traces in addition extend outwardly beyond the first die and extended towards the first edge.

11. semiconductor subassembly according to claim 1, wherein, the second lower edge face of second tube core and institute The second tube core lower surface is stated to flush.

12. semiconductor subassembly according to claim 1, wherein, the second top edge face is located at second tube core The top of the second tube core upper surface.

13. semiconductor subassembly according to claim 2, wherein, the moulded resin is in the first die or described Extend on one or more of two tube cores.

14. semiconductor subassembly according to claim 1, wherein, at least Part I of the multiple conductive trace is located at Under second tube core, the Part II of the multiple conductive trace is located under the second edge.

15. a kind of method for manufacturing semiconductor subassembly, including：

First die component is formed, including：

First edge is formed in first die, the first edge extends laterally from the first die, and described first Edge includes the top edge face of the exposure close to the first die upper surface of the first die；

The second die assemblies are formed, including：

Second edge is formed on the second tube core, the second edge extends laterally from second tube core, and described second Edge includes the lower edge face of the exposure close to the second tube core lower surface of second tube core, and

Multiple conductive traces are formed, the multiple conductive trace extends beyond second tube core and reaches the following of the exposure Edge face；

The lower edge surface layer of the exposure of second die assemblies is put into the exposure in the first die component On top edge face, the intervention of the multiple conductive trace the top edge face of the exposure and the lower edge face of the exposure it Between；And

Formed and extend through at least one one or more vias in the first edge and the second edge, described one Individual or multiple vias communicate with the first die and second tube core.

16. according to the method for claim 15, wherein, form first edge and second edge is included in the first die With molded dielectric part on second tube core, the first edge and described second are formed using the dielectric portion Edge.

17. the method according to claim 11, including：

The first reconstruct die panel is formed, the first reconstruct die panel is included in more pipes of first moulded in panel frame Core, individual tube core more than described first include the first die, and

The second reconstruct die panel is formed, the second reconstruct die panel is included in second moulded in another panel frame Multiple tube cores, individual tube core more than described second include second tube core；And

Form the first edge and the second edge and surround the first reconstruct die panel using dielectric substance With the periphery of the tube core in the described second reconstruct die panel.

18. according to the method for claim 17, including choose in more than the first individual tube core and more than the second individual tube core The tube core, with ensure only by exercisable tube core be used for formed it is described first reconstruct die panel and it is described second reconstruct manage Core panel.

19. according to the method for claim 17, including from the described first reconstruct die panel and described second reconstruct tube core Panel isolates the first die and the independent assembly of second tube core.

20. according to the method for claim 15, wherein, one or more of vias are formed by laser drill, power auger One or more of hole or chemical etching form.

21. according to the method for claim 15, wherein, forming one or more of vias includes being formed through described the One or more continuous vias at one edge and each edge in the second edge.

22. the method according to claim 11, including multiple conductive traces in addition are formed, multiple conductive traces in addition Extend beyond the first die and reach the first edge, one or more of vias and the first die component and The multiple conductive trace communication of each die assemblies in second die assemblies.

23. the method according to claim 11, wherein, by the lower edge surface layer of the exposure of second die assemblies Put includes second tube core relative to described first on the top edge face of the exposure of the first die component Tube core is interleaved to expose at least one bond pad of second tube core.