CN104517934A

CN104517934A - Method for manufacturing interconnected and stacked semiconductor devices

Info

Publication number: CN104517934A
Application number: CN201410504407.8A
Authority: CN
Inventors: 赵俊峰
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2013-09-27
Filing date: 2014-09-26
Publication date: 2015-04-15
Anticipated expiration: 2034-09-26
Also published as: CN104517934B; CN107579011A

Abstract

The invention relates to a method for manufacturing semiconductor devices. The method includes: forming edges on a first tube core and a second tube core, wherein the edges extend transversely to get away from the first and second tube cores; stacking the second tube core on the first tube core, and after stacking, drilling one or more via holes by penetrating the edges. One semiconductor device comprises a redistribution layer extending on the first and second tube cores and at least one of the edges. The via holes extend to penetrate the corresponding edges, and communicate with the first and second tube cores via the edges.

Description

For the method for the semiconductor device of interconnect stack

Technical field

Embodiment described herein relates generally to multilayer manufacture in microelectronic component and electrical interconnection.

Background technology

Multilayer semiconductor device comprises multiple tube core, and described multiple tube core is stacking, and utilizes the electrical connection extended to carry out bonding therebetween.In one example, stacking device is formed by two or more wafers (comprising multiple tube core), and the interface place of described wafer between two or more wafer is coupled.The wafer of coupling to be cut into small pieces and by its wire-bonded to form multiple device.

In some instances, wafer some tube cores (chip such as, in tube core) defectiveness and cannot use.Due to the coupling between wafer, these defective tube cores are still included in multilayer semiconductor device, even and if other tube cores many in device can use completely, but the device produced also defectiveness and cannot using.Therefore, the total output of available multilayer device is reduced based on the manufacture of wafer.

In other example, provided the interconnection between the tube core in multilayer semiconductor device by the wire-bonded between each layer.Such as, two or more semiconductor elements stacking (such as, bonding) are on substrate, and electric wire extends to substrate along the wire bond pads of semiconductor element.On substrate, electrical interconnection is routed to the ball grid array on the opposite side of substrate further.Be molded stacking semiconductor element protecting tube core and electric wire.Electric wire provides the indirect coupling between two-layer or more the layer of multilayer device.The indirect coupling between two-layer or more the layer of combined leads is utilized to limit data and power delivery (such as, the speed of transfer of data and corresponding performance).In addition, the substrate on stacking tube core and the introducing of die cap increase the height (z height) of multilayer device.

Desirably solve multilayer manufacturing technology and the inter-level interconnects technology faster of the improvement of these and other technical barrier.

Accompanying drawing explanation

Fig. 1 is the cross-sectional view of multilayer semiconductor device, and described multilayer semiconductor device comprises the via hole at the edge extended through from tube core horizontal expansion.

Fig. 2 is the detailed cross sectional view of the multilayer semiconductor device of Fig. 1.

Fig. 3 is the process chart of an example of the method illustrated for the manufacture of multilayer semiconductor device.

Fig. 4 is the form of the difference in height that semiconductor device is shown.

Fig. 5 is the flow chart of an example of the method illustrated for the manufacture of multilayer semiconductor device.

Fig. 6 is the form compared with the Z height of the semiconductor device comprising the via hole in transverse edge the semiconductor device comprising wire-bonded.

Fig. 7 is the block diagram of another example of the method illustrated for the manufacture of multilayer semiconductor device.

Fig. 8 is the block diagram of another example of the method illustrated for the manufacture of multilayer semiconductor device.

Fig. 9 is the cross-sectional view of another example of the multilayer semiconductor device comprising the via hole extending through one or more transverse edge.

Figure 10 is the flow chart of another example of the method illustrated for the manufacture of multilayer semiconductor device.

Figure 11 is the schematic diagram of the electronic system of some embodiments according to present disclosure.

Embodiment

Below explanation and accompanying drawing fully show specific embodiment, put into practice these embodiments to enable those skilled in the art.Other embodiment can comprise in structure, in logic, electrically, technique and other change.In the part that the part of some embodiments and feature can be included in other embodiment and feature, or part and the feature of other embodiment can be replaced.The embodiment set forth in claims comprises whole available equivalents of these claims.

Fig. 1 shows an example of the semiconductor device 100 comprising multiple tube core 102.Such as, as shown in fig. 1, semiconductor device 100 at least comprises the first tube core 104 and the second tube core 106.As shown, the first tube core 104 and the second tube core 106 are along the upper surface of respective tube core and lower surface coupling.Illustrate as further illustrated in fig. 1, semiconductor device 100 comprises one or more edge 108, described one or more edge 108 such as according to the size of edge horizontal expansion 110 from each the tube core horizontal expansion tube core 102.In one example, as shown in about the first tube core 104 and the second tube core 106, corresponding edge 108 is extended the respective edges of the first tube core 104 and the second tube core 106 in the horizontal.

In one example, edge 108 is made up of polymeric material, but is not limited thereto, and described polymeric material is dielectric mold compound such as, and it is configured to molded around the first tube core 104 and the second tube core 106 and therefore protects tube core wherein.In another example, the first tube core 104 and the second tube core 106 are made up of the material harder than the mold compound used in edge 108, but are not limited thereto.Such as, the first tube core 104 and the second tube core 106 are made up of silicon.In another example, edge 108 is formed by being configured to protect the polymer of the first tube core 104 of semiconductor device 100 and the softer of the second tube core 106 (such as, comparatively low elastic modulus).The comparatively flexible polymer at edge 108 is easier to be penetrated like that as described herein (such as, laser drill, machine drilling, FIB removal, etching etc.).

Refer again to Fig. 1, as shown in the figure, multiple via hole 112 extends through one or more tube core 102.As herein by description, conductive via 112 allows communication between each tube core in tube core 102 and external circuit and data transmission, and described external circuit includes but not limited to the ball grid array 114, land grid array, pin grid array etc. that arrange along the surface of semiconductor device 100.As shown in the cross-sectional view of Fig. 1, form multiple via hole 112 through the edge 108 relative with the second tube core 106 with the first tube core 104.As herein by description, in one example, after being stacked in the structure shown in Fig. 1 by tube core 102, form via hole 112.Such as, via hole 112 gets in edge 108 by one or more in utilization machinery, chemistry (photoetching) and method for drilling holes.

As will be further described herein, in one example, each tube core in tube core 102 comprises redistributing layer, such as, and a series of conductive traces through composition that each tube core in adjacent die 102 provides.Redistributing layer extends and enters in edge 108 on the area occupied of tube core 102.Conductive trace along redistributing layer formation is arranged to and is coupled with via hole 112.Therefore, each tube core in the tube core 102 of semiconductor device 100 can be communicated with other tube core 102 one or more by via hole 112, and optionally communicates with ball grid array 114.By providing edge 108 and corresponding via hole 112 wherein for each tube core in tube core 102, as compared to the other indirect coupling being covered the wire-bonded of die cap (being adjusted to the size of the free lead wire of encapsulation) with the one or more tube cores in the underlying substrate with ball grid array by utilization and provide, achieve the direct-coupling between one or more tube core 102 and ball grid array 114.That is, in one example, from the edge 108 that multiple tube core 102 extends (such as, size according to edge horizontal expansion 110) provide mechanism for closely holding multiple via hole 112 wherein, it allow for the direct communication between the tube core 102 of semiconductor device 100, and does not need the die cap of the wire-bonded covering multiple tube core 102 to provide this with substrate etc. in addition to communicate.Therefore, the height (Z height) of semiconductor device 100 is substantially less than to comprise and utilizes wirebond interconnections and the multiple tube core be then encapsulated in die cap and have the height of the semiconductor device of underlying substrate.Such as, in some instances, relative to commeasurable wire-bonded device, the Z height of saving for the semiconductor device 100 with the via hole 112 provided in edge 108 can reach 0.2mm.

Refer again to Fig. 1, as illustrated further, in one example, semiconductor device 100 comprises ball grid array 114, and described ball grid array 114 comprises the multiple soldered balls 116 arranged along one or more tube core 102.In the example depicted in fig. 1, the first tube core 104 (redistributing layer of the first tube core 104 such as, described herein) and soldered ball 116 direct-coupling.Therefore, the data via via hole 112 of each tube core in tube core 102 transmit and are correspondingly sent to the first tube core 104 and other tube core 102 any via via hole 112.The soldered ball 116 provided in ball grid array 114 is provided to and from the input and output of semiconductor device 100, and avoids simultaneously and need the underlying substrate of multiple tube core 102 from semiconductor device reception information in addition and transmit information.That is, by ball grid array 114 being directly coupled to the redistributing layer of the first tube core 104, semiconductor device 100 shown in Fig. 1 does not need in addition for the substrate of some semiconductor device, thus achieves additional space and save and provide compacter device.By providing through multiple via holes 112 at edge 108 and along the direct-coupled ball grid array 114 of the first tube core 104, to contribute in semiconductor device 100 high-speed transfer of (and to and from), and make the overall height of semiconductor device 100 minimize simultaneously.

With reference now to Fig. 2, provide the more detailed cross-sectional view of the semiconductor device 100 shown in prior figures 1.In the detailed view of Fig. 2, in stacked structure, again illustrate multiple tube core 102, and each tube core in tube core 102 comprises such as according to the respective edges 108 of edge horizontal expansion 110 from tube core 102 horizontal expansion.In one example, each tube core in tube core 102 is a part for die assemblies 201, and described die assemblies 201 comprises corresponding tube core 102, edge 108 and redistributing layer 202 (and optional mold compound 200) as described in this article.

As shown in Figure 2, provide via hole 112 or multiple via hole through edge 108, and via hole 112 or multiple via hole extend between tube core 102 continuously.In another example, one or more via hole 112 extends through one or more edge 108, with the communication between two or more tube cores 102 providing semiconductor device 100 or between tube core 102 and ball grid array (by redistributing layer 202).That is, the via hole 112 provided in edge 108 partly or entirely extends through the stacked body of die assemblies 201.Other via hole 112 provided through edge 108 extends through two or more edges 108, correspondingly to provide communication between two or more tube cores 102 of stacking semiconductor device 100.In one example, get out via hole 112 from the both sides at edge 108, such as, hole from the upper surface 203 of semiconductor device 100 and basal surface 205.In another example, get out multiple via hole 112 from the one or both sides of semiconductor device 203,205.In another example, after stacking, get out via hole 112.Therefore, via hole 112 is easier to be alignd by previously stacking tube core 102.With the multiple independent via hole of formation and the stacking subsequently and via hole that aligns (such as, tube core) is contrary, hole in single valid function, this incorporates the formation of via hole in a single step.

As mentioned above, each die assemblies in die assemblies 201 comprises the redistributing layer 202 of tube core 102 and adjacent die 102 formation.As shown in the figure, redistributing layer 202 extends beyond area occupied (such as, the horizontal area occupied of tube core 102), and extends in edge 108.Such as, in one example, tube core 102 is encapsulated in mold compound 200, such as, in panel frame described herein.Be received into after in panel frame, mold compound 200 be incorporated in panel frame and harden around each tube core making it in tube core 102.Recompose-technique is used for the conductive trace providing redistributing layer 202 along each tube core in tube core 102.Such as, as shown in Figure 2, correspondingly from the horizontal expansion of multiple tube core 102 and through described multiple edge 108 on multiple edges 108 of redistributing layer 202 die assemblies of each in die assemblies 201.Redistributing layer 202 provides " fan-out " structure thus, and it allows the distributed interconnection (such as, by via hole 112) of each tube core in tube core 102 and other tube core in semiconductor device 100 and ball grid array 114.Therefore, the redistributing layer 202 of fan-out cooperates with the multiple via holes 112 provided through edge 108, minimize correspondingly to make the overall height of semiconductor device 100, and provide direct connection between each tube core simultaneously in tube core 102, and provide and be connected with the direct of ball grid array 114 below the first tube core 104.Redistributing layer provides the conductive trace from tube core horizontal expansion, then passes through via hole 112 by described die interconnect.In other words, via hole 108 and redistributing layer 202 provide the interconnection be contained in edge 108, and without the need to larger die cap (such as, for encapsulating free lead wire in addition).

As further shown in fig. 2, before stack chip, laterally and mold compound 200 (such as, forming the dielectric resin of corresponding polymer) is provided on the top of multiple tube core 102.In another example, the side of the multiple tube cores 102 contrary with the upper surface along each tube core in tube core 102 provides mold compound 200.Mold compound 200 horizontal expansion is to form the edge 108 of the edge horizontal expansion 110 had relative to tube core 102.As previously mentioned, after being molded multiple tube core 102 (as described in this article in the flat panel with wafer or panel construction), multiple tube core 102 is cut out from panel, its operability is tested, and is then stacked in the structure shown in Fig. 2 of the stacked structure of such as semiconductor device 100.In another example, before the die panel (described herein) separating and formed reconstruct from original Silicon Wafer, test multiple tube core.

Each tube core in tube core 102 utilizes the layer of bonding agent 204 or other mating substance provided between each die assemblies in die assemblies 201 coupled to each other.As shown in Figure 2, bonding agent 204 aligns with each tube core in tube core 102, and is remained in alignment structures by tube core 102.In one example, after stack chip 102, get out multiple via hole 112 through semiconductor device 100, the interconnection between each tube core in tube core 102 is provided with the redistributing layer 202 thus by each die assemblies in die assemblies 201.

In another example, in the structure in fig. 2, before stack chip assembly, in each die assemblies respectively in die assemblies 201, form via hole 112.Therefore, in stacking process, make via hole 112 align, correspondingly to guarantee the communication between each die assemblies (and ball grid array 114) in die assemblies 201.In one example, via hole 112 is filled with the electric conducting material of such as copper etc., sputtering or provide described electric conducting material by vapour deposition, with each tube core 102 of interconnecting semiconductor device 100 and be connected with ball grid array 114 by tube core 102.

Refer again to Fig. 2, as previously described herein, each via hole in via hole 112 is shown in edge 108, and spaced relative to each tube core in tube core 102.That is, tube core 102 is interconnected by the conductive via 112 provided by the edge 108 of horizontal expansion.Interconnection between tube core 102 is provided in the lateral part by each die assemblies in die assemblies 201, connection between each tube core in tube core 102 and ball grid array 114 is merged into via hole 112 and the redistributing layer 202 (such as, transverse edge 108) from each the tube core fan-out tube core 102.Therefore, accordingly avoid the parts of other semiconductor device, the conductive substrates such as provided below stacking tube core and be provided for encapsulating and protect the wire-bonded between each tube core and underlying substrate in the die cap of tube core and tube core.As an alternative, by semiconductor device 100, utilize mold compound to be molded each tube core in tube core 102, thus provide transversely-extending edges 108 for redistributing layer 202 and provide space for the via hole 112 of horizontally set.Therefore, relative to the Z height of other structure of the semiconductor device of (and the corresponding die cap on wire-bonded top) at the bottom of use wire-bonded and back lining, the vertical height of semiconductor device 100 or Z height are minimized.

In addition, owing to providing via hole 112 through edge 108, thus via hole 112 is easier to be formed in semiconductor device 100.Such as, at least some example, the silicon through tube core 102 provides via hole.Silicon is more difficult to be drilled through, because it is frangible and comparatively hard (such as having higher modulus of elasticity).But the convenient boring being each tube core in tube core 112 for the polymer in the mold compound 200 of semiconductor device 100 provides softer material (relative to silicon).The softer material at edge 108 correspondingly ensure that and is easy in semiconductor device 100 form via hole, and therefore, electric conducting material is easy to be deposited in via hole 112, with each redistributing layer in the redistributing layer 202 of the respective dies 102 of interconnecting tube core assembly 201.Similarly, formed because via hole 112 facilitates penetration of the mold compound at edge 108, thus make such as formed tube core 102 stacked structure before or after minimum to the damage of semiconductor device 100.By contrast, the silicon through one or more silicon die carries out boring existing problems, because the chip of the semiconductor in tube core or damage risky.An example of mold compound 200 includes but not limited to epoxy resin, and it comprises one or more additives, and described additive is configured to the character (such as, the encapsulation of semiconductor device 100) at adjustment edge 108 with satisfied encapsulation requirement.Such as, epoxy resin comprises additive, to adjust the one or more character in modulus of elasticity, thermal coefficient of expansion, curing temperature, curing time, glass transition temperature, thermal conductivity etc.

Fig. 3 shows the process chart of a series of schematic diagrames of an example of the technique of the manufacture of the semiconductor device for all semiconductor device 100 as shown in figs. 1 and 2.In the first stage 301, in monolithic semiconductor wafer 300, show multiple tube core 302.Such as, multiple tube core 302 is formed in Silicon Wafer, as previously known (by the mask of wafer and the mode of etching).Tube core 302 in detection Silicon Wafer 300 is to determine which tube core is exercisable (the operated tube core of nothing manufacture or performance deficiency).Cutting semiconductor wafer 300 is to be correspondingly separated each tube core in tube core 302.Optionally, after cutting and be then separated, detection tube core 302.

From remaining tube core 302, be separated exercisable tube core 306, and in the stage 303, exercisable tube core 306 be arranged in panel frame 304.As shown in Figure 3, in one example, panel frame 304 has substantially similar structure to the semiconductor crystal wafer 300 shown in the stage 301.In another example as herein described, panel frame 304 has another kind of shape, such as square or rectangle.Multiple exercisable tube core 306 is assembled in panel frame 304, and forms the die panel 308 of reconstruct.Such as, the mold compound hardening into the such as resin of dielectrical polymer etc. is supplied to panel frame 304.Mold compound hardens can operate around each the operated tube core in tube core 306, correspondingly to form the die assemblies 201 (comprising tube core 102 and corresponding edge 108) of the separation shown in Fig. 2.In the structure shown in the stage 303, the die panel 308 of reconstruct is convenient to stacking, such as, to form previously described one or more semiconductor device 100 herein.

In another example, after the die panel forming reconstruct (such as, be molded can operate tube core 306 after), define the redistributing layer 202 of each tube core in tube core 306.Such as, manufacture and photoetching are used for the conductive trace etching redistributing layer 202 on mold compound 200 and tube core 306.As previously mentioned, redistributing layer 202 has fan-out, and it is configured to extend (such as, seeing Fig. 2) on the area occupied that can operate tube core 306 and edge 108.

With reference now to the stage 305, in the decomposition texture being stacked each die panel in multiple die panel 310, show reconstruct die panel 308.As shown in the figure, the operated tube core 306 of each panel in multiple reconstruct die panel 310 is presented in substantially similar structure, and reconstruct die panel 310 in each between correspondingly align.That is, the operated tube core 306 of each die panel such as comprised in the die panel 310 of the first and second reconstruct die panel 312,314 is alignd, with in the later step of technique, when stacking tube core is separated (cutting), correspondingly provide stacking semiconductor device.As previously mentioned, in one example, multiple reconstruct die panel 310 each between coating adhesive 204, to guarantee the coupling between multiple reconstruct die panel 310, comprise the alignment of maintenance tube core wherein.

In the stage 307, multiple via hole 112 is formed in stacking multiple reconstruct die panel 310.Such as, shown in the stage 307, stack of panels assembly 316 comprises the multiple reconstruct die panel 310 in stacking and bonding structure.Therefore, multiple tube cores 102 (correspond to and can operate tube core 306) of align panel 310 in the structure of layout corresponding to the device 100 shown in Fig. 1 and 2.Be extended the interior formation in edge 108 (comprising the redistributing layer 202 shown in Fig. 2) via hole 112 of each tube core (306 shown in Fig. 3) in tube core 102 in the horizontal.

In one example, forming via hole 112 in batch process, holes in the edge 108 such as comprised through each tube core in corresponding tube core 102.That is, in stack of panels assembly 316 (before cutting), multiple via hole 112 is got out, correspondingly to contribute to the quick formation of the via hole 112 in each semiconductor device in the semiconductor device of single fabrication stage through stack of panels assembly 316.In another example, stack of panels assembly 316 is cut into multiple semiconductor device 100.After this, hole to be formed the via hole 112 extending through edge 108 respectively to the semiconductor device 100 of multiple separation.After via hole 112 is formed, the sputtering of the electric conducting material of such as copper or vapour deposition in the passage of via hole 112, with electric coupling tube core 306 (such as, by the redistributing layer 202 at edge 108).

Shown in the stage 309, additionally provide ball grid array 114 (also illustrating in fig 1 and 2).In one example, to be similar to the mode in stage 307, while still remaining in the stack of panels assembly 316 shown in the stage 307, form the ball grid array 114 of each semiconductor device in semiconductor device 100 along semiconductor device.Optionally, after dicing, such as, after being cut into the semiconductor device 100 shown in the stage 309, ball grid array 114 is formed along semiconductor device 100.

Refer again to the stage 309, the semiconductor device 100 completed is shown as the via hole 112 having stacking tube core 102 and extend through edge 108.Also on the bottom of semiconductor device 100, show ball grid array 114, such as, be coupled with redistributing layer, described redistributing layer is associated (as shown in Figure 2) with the first tube core 104.

Technique shown in Fig. 3 schematically provides multiple semiconductor device 100, such as, device shown in Fig. 1 and 2.Tube core 306 can be operated because each in panel frame 304 and corresponding reconstruct die panel 310 only comprise, therefore substantially avoid and comprise one or more semiconductor device 100 that is impaired or defective tube core 102.That is, refer again to the stage 305, previously tested each in the operated tube core 306 in each being included in multiple reconstruct die panel 310, and known that it is exercisable.Therefore, the semiconductor device 100 produced by stacking panel assembly 316 is correspondingly exercisable.Relative to such as use wherein have can operate, the existing manufacturing technology of the monolithic semiconductor wafer of defective and impaired semiconductor, the technique shown in figure makes defective or impaired semiconductor minimum or avoid and comprise defective or impaired semiconductor.In previous manufacturing technology, in the device that defective or impaired semiconductor has been included in, overall available device is in other cases caused to go out of use.In other words, utilize technique as herein described, one or more (such as, multiple) that there is provided in one or more semiconductor crystal wafer 300 defective or impaired tube core 302 can not enter in the complete in other cases exercisable semiconductor device 100 manufactured as mentioned above.

Therefore, the productive rate of semiconductor device 100 is substantially higher than other technique using the whole semiconductor crystal wafer 300 comprising exercisable and defectiveness or impaired tube core.Except higher productive rate, the direct interconnection each tube core in tube core 102 is such as provided through the configuration of the via hole 112 at edge 108, without the need to larger die cap and substrate, then need larger die cap and substrate when the semiconductor device of wire-bonded.Therefore, with respect to other semiconductor device that the mode of wirebond interconnections and substrate is formed, the semiconductor device 100 produced by the technique shown in Fig. 3 has more reliably can operating characteristic and minimized vertical height (Z height).

With reference now to Fig. 4, provide stage 403,405 the substituting as the stage 303 and 305 shown in Fig. 3 that two other.Such as, relative to the crystal circle structure of the panel frame 304 shown in the stage 303, the panel frame 400 shown in Fig. 4 has square or rectangle (such as, non-circular) structure.Therefore, panel frame 400 can operate tube core 306 and will be arranged in the grid of the pattern as having square rectangular structure.Then the reconstruct die panel 402 shown in the stage 403 is stacked in the multiple reconstruct die panel 404 as shown in the stage 405 in Fig. 4.As illustrated further in Fig. 4, multiple reconstruct die panel 404 at least comprises the first and second reconstruct die panel 406,408.

Then, previously described technique in Fig. 3 is implemented in the mode substantially similar to the multiple reconstruct die panel 404 provided in stacked structure.That is, in one example, the multiple edges 108 being passed in each tube core be transversely extended in tube core 102 form via hole 112.In one example, while remaining in stacked structure by tube core 102, (such as, before being cut), in edge 108, via hole 112 is formed.In a similar fashion, in the stage 307, while remaining in the stack of panels assembly shown in Fig. 3 by first of semiconductor device 100 the reconstruct die panel 406, ball grid array 114 is also applied to the first reconstruct die panel 406.In another example, as previously described herein, via hole 112 and ball grid array 114 are formed on independent semiconductor device 100, such as, after semiconductor device 100 cuts out from stacking multiple reconstruct die panel 404.

Fig. 5 shows a cross-sectional view of the semiconductor device 500 of the wire-bonded between the tube core 502 comprising underlying substrate 506 and device 500.As illustrated further in Fig. 5, being engaged with each tube core in tube core 502 by one or more lead-in wire 504 and to be extended through semiconductor device 500 (such as, through die cap 510), each tube core in tube core 502 is connected with substrate 506.As shown in the figure, at least some in a plurality of leads 504 by first extending to substrate 506 (substrate comprises multiple conductive trace) from corresponding tube core 502 and then extending to other tube core 502 one or more from substrate 506 by additional lead-in wire 504, and provides the interconnection between each tube core in tube core 502.As illustrated further in Fig. 5, the opposed surface along substrate 506 provides ball grid array 508, and by extending to the lead-in wire 504 of tube core 502 by ball grid array 508 and die interconnect from substrate 506.

Compared with the assembly shown in Fig. 5, semiconductor device 100 (Fig. 1 and 2) described herein comprises the multiple tube cores 102 in stacked structure, described stacked structure comprises the edge 108 of the multiple horizontal expansions from each tube core 102 horizontal expansion (such as, seeing horizontal expansion 110).Edge 108 provides the boring of the via hole 112 be arranged to wherein and the mold compound, resin etc. of formation.As previously described herein, each in die assemblies 201 is formed with redistributing layer 202, such as, to provide the fan-out structure of the conductive trace of the horizontal area occupied of each tube core extended beyond in tube core 102.Therefore, utilize the via hole 112 extending through redistributing layer 202, provide the electrical interconnection between each tube core in tube core 102 in the compact lateral attitude (such as, in edge 108) relative to tube core 102.Interconnection between tube core is provided in the horizontal space that each tube core in tube core 102 is adjacent, and does not need large die cap 510 to hold a plurality of leads 504 of the semiconductor device 500 shown in Fig. 5 in addition.In addition, extend between each in tube core 102 of via hole 112.Such as, via hole 112 extends between two or more tube cores 102, to provide the direct connection between tube core 102, and therefore avoids intermediate substrate 506 as shown in Figure 5.

In addition, the semiconductor device 100 shown in Fig. 1 and 2 there is no need for the substrate 506 inputting from device 100 or export to device 100.As an alternative, the ball grid array 114 that the device 100 comprising the tube core 102 and redistributing layer 202 interconnected with via hole 112 is configured to by being coupled along the redistributing layer 202 of the first tube core 104 provides input and output.In other words, the substrate 506 shown in Fig. 5 and die cap 510 is no longer needed in the semiconductor device 100 shown in Fig. 1 and 2.As an alternative, be that the redistributing layer 202 comprising its conductive trace and the via hole 112 got out through edge 108 provide space from the edge 108 of tube core 102 horizontal expansion.Therefore, by using semiconductor device 100, relative to the semiconductor device 500 (needing larger die cap 510 and substrate 506) shown in Fig. 5, (Z height) achieves space saving in vertical direction.In addition, the via hole 112 between the semiconductor device 100 shown in Fig. 1 comprises by each tube core in tube core 102 relatively directly connect (there is no intermediate substrate 506).This is arranged in tube core 102 and between the ball grid array 114 be associated with the redistributing layer 202 of the first tube core 104, (see Fig. 2) provides directly and therefore comparatively fast and more reliable transfer of data.

With reference now to Fig. 6, provide Z height for the multiple semiconductor device with provided structure (such as utilizing the structure shown in the device 100 of Fig. 1 and 2) herein and compare form.As described herein, semiconductor device 100 comprises one or more die assemblies 201, and each die assemblies has tube core 102, edge 108 and extends to one or more via holes of redistributing layer 202 through edge 108.The Z height 602 of the corresponding mold compound used in the edge 108 of each die assemblies and each die assemblies has been shown in the row of form " there is the semiconductor device of the via hole in edge ".Total Z height 602 corresponds to the quantity (each has the height of about 25 microns, and mold compound has the height of 10 microns) for the stacking die assemblies 201 of specific type of encapsulation.With ascending order arrangement semiconductor device 100, namely (dual-die encapsulates for the first device (single die encapsulation or SDP) comprising singulated dies assembly, second device with two die assemblies, DDP), etc. (such as, QDP comprises four assemblies, ODP comprises eight assemblies, and HDP comprises 16 assemblies).

The corresponding Z height 604 of the semiconductor device (semiconductor device 500 see shown in Fig. 5) comprising wire-bonded and substrate is provided in the first row of form.As shown in the figure, the die assemblies Z height of wire-bonded device is 25 microns, and the die cap of each die assemblies and spacing Z height change according to the quantity of the die assemblies of device.Under a line show total Z height of each device, it is multiplied by the quantity of the die assemblies of device based on die assemblies Z height and die cap and spacing Z height.

As shown in Figure 6, relative to the corresponding total Z height (such as comprising wire-bonded, die cap and substrate) of corresponding device with the layout shown in Fig. 5, there is the total Z height 602 of each in the device of the fan-out redistributing layer 202 of the via hole 112 comprised in edge 108 less.The saving of the Z height of each in corresponding die assemblies 201 is delivered to the stacking semiconductor device 100 with two or more die assemblies.That is, relative to using the respective dies assembly used in the encapsulation of wire-bonded, die cap and substrate, the Z height of each that the device (such as, die assemblies 201) comprised more than two tube cores with structure described herein adds in stacking die assemblies 201 is saved.

Fig. 7 shows an example of the method 700 of the Stacket semiconductor device for the manufacture of all semiconductor device 100 as previously described herein.When describing method 700, with reference to one or more parts as herein described, feature, function etc.In situation easily, with reference to the parts and feature with Reference numeral.Reference numeral is exemplary, and non-dedicated.Such as, the parts described in method 700, feature, function etc. include but not limited to the element of corresponding numbering, other individual features as herein described (numbering or unnumbered) and their equivalent.

At 702 places, method 700 is included on the first tube core 104 and the second tube core 106 and forms edge 108.Edge 108 is extended the first and second tube cores 104,106 in the horizontal.Such as, as shown in fig. 1, multiple edge 108 extends from each corresponding tube core according to edge horizontal expansion 110.

At 704 places, the second tube core 106 is stacked on the first tube core 104.Such as, as shown in Figure 2, such as, in stacked structure, the die assemblies 201 comprising corresponding tube core 102 and corresponding redistributing layer 202 is coupled.In one example, the die-stack of such as the second tube core 106 is comprised the surperficial coating adhesive at least between the first and second tube cores 104,106, correspondingly to be bonded together by tube core in laminated construction on the first tube core 104.

At 706 places, after the die assemblies 201 in the structure shown in stacking Fig. 2, get out one or more via hole 112 through edge 108.One or more via hole 112 at least extends between the first and second tube cores 104,106.In another example, method 700 comprises before stacking, such as, time in the panel frame multiple tube core 102 being remained on the panel frame 304 shown in the stage 303 in such as Fig. 3, gets out the one or more via holes 112 through edge 108.Then, multiple tube core 102 is arranged in laminated construction, and the mode that corresponding via hole 112 relative to each other aligns according to multiple tube core 102 (such as, die assemblies 201) is alignd.After holing to one or more via hole 112, such as, by vapour deposition, sputtering or plating, via via hole 112 coating electrically conductive material, with the tube core 102 that correspondingly interconnects.Such as, multiple via hole 112 is by providing interconnection with each redistributing layer be associated 202 in tube core 102.

In addition, in another example, one or more via hole 112 provide tube core 102 and along the redistributing layer 202 be associated with the first tube core 104 ball grid array 114 between interconnection.

With reference now to Fig. 8, provide another example of the method 800 for the manufacture of stacking semiconductor device 100.When describing method 800, with reference to one or more parts as herein described, feature, function etc.In situation easily, with reference to the parts and feature with Reference numeral.Reference numeral is exemplary, and non-dedicated.Such as, the parts described in method 800, feature, function etc. include but not limited to the element of corresponding numbering, other individual features as herein described (numbering or unnumbered) and their equivalent.

Refer again to Fig. 8, at 802 places, method 800 comprises selection tube core 302 such as, to obtain multiplely operating tube core, the operated tube core 306 shown in stage 303 in Fig. 3.Detect or test multiple tube core 306 that operates to determine its operability.At 804 places, at least form the first reconstruct die panel 308.

In one example, at 806 places, formed first reconstruct die panel (and additional dies panel) comprise by selection multiple tube cores 306 that operate be arranged in panel frame 304.In another example, the operated tube core 306 of selection is arranged in non-circular geometric face plate framework, such as, panel frame 400 shown in Fig. 4.At 808 places, multiple in panel frame 304 (or panel frame 400) operate moulded resin around tube core 306, to form the first reconstruct die panel 308.As described earlier in this article, edge 108 is formed in resin, and from multiple each horizontal expansion operating tube core 306.

In one example, at 804 places, the technique for the formation of reconstruct die panel is recycled and reused for additional dies panel, therefore to produce multiple reconstruct die panel 312 or 404 shown in figures 3 and 4 respectively.As described earlier in this article, then multiple reconstruct die panel being stacked into the corresponding square shown in stack of panels assembly 316 and Fig. 4 or non-circular structure, is that each in the semiconductor device 100 produced provides stacking a series of tube cores 102 with (in Fig. 3 stage 309 shown in) before cutting.

Time in stack of panels assembly 316, such as, shown in the stage 307 of Fig. 3, the edge 108 be associated through each tube core in the die assemblies 201 comprised in semiconductor device 100 forms multiple via hole 112.Such as, time in the stack of panels assembly 316 shown in 307, in batch process, form multiple via hole 112, correspondingly to reduce the time produced when other discrete-semiconductor device 100 needed for via hole 112.After formation via hole 112, cut out semiconductor device 100 from stack of panels assembly 316, to form shown in the stage 309 in Fig. 3 and the semiconductor device 100 be shown specifically further in fig 1 and 2.

In addition, in another example, be still a part for stack of panels assembly 316 at semiconductor device 100 while, ball grid array 114 (shown in Fig. 1 and 2) is supplied to the first tube core 104 be associated with each semiconductor device in semiconductor device 100.In another example, after cut out semiconductor device from stack of panels assembly 316, the ball grid array 114 forming via hole 112 and be associated with each semiconductor device in semiconductor device 100.

Fig. 9 shows another example of the semiconductor device 900 comprising multiple tube cores 102 with respective edges 904.As shown in Figure 9, in cross structure, (such as, displacement or hierarchic structure) provides tube core 102.Such as, each in die assemblies 902 is relative to each other shifted, to form staggered a series of tube cores in semiconductor device 900.As shown in Figure 9, each in tube core 102 is relative to each other shifted, to expose at least one side of one or more bond pads 905 of each tube core comprised in tube core 102.In one example, such as, to be shifted each tube core 102 according to tube core displacement 906, tube core displacement 906 correspondingly makes tube core interlock relative to adjacent tube core respectively.In another example, tube core 102 carries out the displacement of different brackets (and optionally different directions), correspondingly to expose one or more bond pad 905 according to displacement.That is, one or more tube core 102 according to the position of respective bond pad 905 with one or more larger or less grade or be shifted in different directions.

As shown in Figure 9, each on the equidirectional providing cross structure (staged) in staggered tube core, with the corresponding bond pad 905 of each (except the tube core 102 of the bottommost of semiconductor device 900) in correspondingly exposed die 102.As described earlier in this article, each tube core in tube core 102 is included in corresponding die assemblies 902.As shown in the figure, each die assemblies in die assemblies 902 comprises the one or more corresponding edge 904 of each tube core in tube core 102 and tube core 102.

As illustrated further in Fig. 9, such as, the bonding agent 908 provided on the surface of adjacent tube core 102 is provided, each tube core in multiple tube core 102 is engaged with each other.Each tube core in tube core 102 remains in cross structure by bonding agent 908, and correspondingly keep tube core displacement 906 (example of tube core displacement) as shown in Figure 9, thus bond pad 905 is remained in the structure of exposure, for final interconnection.In one example, before the mold compound applying mold compound 200 previously shown in such as Fig. 2 and so on, bonding agent 908 is utilized to be bonded together by multiple tube core 102.As previously mentioned, mold compound 202 is solidified into dielectrical polymer, and correspondingly for each die assemblies in die assemblies 902 provides edge 904.After each in bonding tube core 102, mold compound 202 is coated in around stacking tube core 102, correspondingly to form the intergrade of semiconductor device 900.

One or more via hole 912 is got out through one or more edge 904, correspondingly to provide the interconnection between tube core 102 and corresponding redistributing layer 910, described redistributing layer 910 is associated with one or more tube cores 102 (tube core of the bottommost such as, shown in Fig. 9) of contiguous ball grid array 114.As shown in Figure 9, each via hole in via hole 912 is coupled to the corresponding bond pad 905 for covering tube core 102 respectively.The multiple via holes 912 be associated to each tube core in tube core 102 correspondingly extend through the one or more edges 904 be associated with corresponding die assemblies 902 from bond pad 905.That is, the uppermost tube core 102 of semiconductor device 900 comprises one or more via holes 912 at the corresponding edge extending through lower die 102.

After formation via hole 912 (such as, by machine drilling, photoetching, laser drill etc.), provide the redistributing layer 910 being similar to the redistributing layer 202 shown in Fig. 2, for at least one tube core 102, such as, correspond to the tube core 102 of the bottom of the semiconductor device 900 adjacent with ball grid array 114.In one example, redistributing layer 910 provides the fan-out structure of the conductive trace extended on the area occupied of tube core 102 and corresponding total area occupied of stacking tube core 102.That is, as shown in Figure 9, the below of each tube core of redistributing layer 910 in tube core 102 extends, and provides conductive trace for interconnecting with via hole 912, and via hole 912 extends through edge 904 from the respective bond pad 905 of each tube core tube core 102.In another example, after formation redistributing layer 910, along redistributing layer 910, ball grid array 114 is applied to semiconductor device 900, connects to provide the input and output of semiconductor device 900.

With reference now to Figure 10, provide another example of the method for the formation of semiconductor (semiconductor device 900 such as, shown in Fig. 9).As the previous method shown in described and Fig. 5, in a series of schematic stage 1001,1003,1005,1007, method is shown.At 1001 places, the operability of the multiple tube cores 102 cut out from one or more monolithic semiconductor wafer is tested.Then exercisable tube core 102 (zero defect or damage) is assembled in die-stack body 1002.Such as, the tube core 102 of bonding one or more die-stack body 1002.As shown in the stage 1001, die-stack body 1002 has cross structure (ladder, displacement etc.), and it correspondingly exposes the bond pad 905 of at least one surface of each tube core in the tube core 102 of die-stack body 1002.As mentioned above, in another example, according to position and the quantity of respective bond pad 905, to be shifted tube core 102 with one or more different brackets or direction.

With reference now to the stage 1003 in Figure 10, be arranged in panel frame 1004 by each the die-stack body in die-stack body 1002, panel frame 1004 comprises size and shape can hold a series of cavitys of each in tube core stacked body 1002.After in cavity die-stack body 1002 being arranged on panel frame 1004, around the multiple die-stack bodies 1002 in panel frame 1004, be coated with mold compound, to form the edge 904 of die assemblies 902 previously shown in Fig. 9.As described herein, in one example, mold compound 202 is resins, and it is formed compares with the material (such as, silicon) of tube core the dielectrical polymer had compared with low elastic modulus.Faying face plate framework 1004 defines reconstruct die panel 1006, comprising multiple molded die-stack body.Stage 3 shows circle (wafer shape) panel frame 1004.In another example, panel frame has all rectangles as shown in Figure 4 or foursquare different shape.

As shown in the stage 1003, the die assemblies 902 formed by die-stack body 1002 comprises the edge 904 from each the tube core horizontal expansion tube core 102.As shown in this structure, die-stack body 1002 is staggered in mold compound 202.Each edge in the edge 904 of corresponding tube core 102 correspondingly changes on lateral dimension according to the deviation post of each tube core in the tube core 102 in die-stack body 1002.The bond pad 905 exposed by the displacement of tube core is in the face of the bottom (as shown in Figure 10) towards the die-stack body 1002 at the edge 904 of lower die 1002.

At stage 1005 place, multiple via hole 912 gets in the edge 904 below bond pad 905, each in tube core 102 and one of them redistributing layer provided 910 along tube core 102 to be interconnected.Such as, in the example in Fig. 10, the tube core (being uppermost tube core shown in this inverted structure) of bottommost is provided with redistributing layer 910.Optionally, before the conductive trace forming redistributing layer 910, multiple via hole 912 is got in edge 904, correspondingly to form the passage by holding electric conducting material, to interconnect with the redistributing layer 910 formed subsequently.Electric conducting material is coated onto the passage of via hole 912 so that the most multiple tube cores 102 of die-stack body 1002 and the redistributing layer of semiconductor device 900 interconnect.In another example, before the boring of via hole 912, form redistributing layer 910.

At stage 1007 place, complete semiconductor device 900 by ball grid array 114 being applied to the redistributing layer 910 previously formed in the stage 1005.Shown in the stage 1007, then from reconstruct die panel 1006, cut out semiconductor device 900.Multiple semiconductor device 900 is cut out from same reconstruct die panel 1006.

Provide as the semiconductor device 900 shown in aforesaid semiconductor device 100, Fig. 9 and 10 and be connected with redistributing layer 910 the direct of (redistributing layer 910 such as, be associated with tube core 102 and the die-stack body 1002 of bottommost).Multiple via hole 912 provides and is connected with the direct of redistributing layer 910, correspondingly comprises and encapsulate the multiple wire-bonded extending to the substrate (being greater than redistributing layer 910) below die-stack body from each tube core tube core without the need to other larger die cap.The cross structure of die-stack body 1002 exposes the bond pad 905 of one or more tube core 102, and thus allows the via hole 912 extending through edge 904 from bond pad 905 each tube core corresponding tube core 102 and redistributing layer 910 to be interconnected.Compared to the die cap of other comparatively dark (thicker) reliably needed for package lead, such as, shown in Fig. 5 504, bond pad 905 is directly connected the mold compound allowing shallow-layer with being provided by via hole 912 between redistributing layer.

In addition, as previously mentioned, due to the silicon with tube core 102 relatively hard materials compared with, softer material (comparatively low elastic modulus) via mold compound 202 carries out the boring through semiconductor device 900, thus by providing via hole 912 through mold compound 202 (dielectrical polymer), make the damage of semiconductor device 900 minimum.In addition, utilize the method shown in Figure 10, one of them of the formation technique of redistributing layer 901 and the tube core 102 of die-stack body 1002 is isolated.Such as, as described herein, redistributing layer 910 is supplied to the tube core 102 of the bottommost of die-stack body 1002.Therefore, via hole 912 extends to through the transverse edge 904 of the tube core 102 of die-stack body 1002 redistributing layer 910 be associated with bottommost tube core 102.Thus the interconnection of each redistributing layer in the multiple redistributing layers be associated with each tube core 102 is in addition merged into the single redistributing layer also provided with the interconnection of ball grid array 114 by redistributing layer 910.In another example, the tube core 102 of bottommost comprises the multiple redistributing layers (such as, multiple adjacent layer 910) being confined to tube core, and covers the remainder of dice of the tube core 102 of bottommost tube core 102 and via hole 912 interconnects.In another example, each tube core in tube core 102 comprises respective redistributing layer 910, and tube core 102 is interconnected by redistributing layer 910 and via hole 912.

Include the example of the electronic equipment of the semiconductor device 100,900 used as described in present disclosure, to illustrate the example of the equipment application of the higher level of present disclosure.Figure 11 is the block diagram of electronic equipment 1100, and it comprises at least one semiconductor device utilizing and construct according to manufacture method and the structure of at least one embodiment of present disclosure.Electronic equipment 1100 is only the use of an example of the electronic system of the embodiment of present disclosure.The example of electronic equipment 1100 includes but not limited to, personal computer, panel computer, mobile phone, game station, MP3 or other digital music player etc.In this example, electronic equipment 1100 comprises data handling system, and it comprises system bus 1102, with the various parts of coupled system.System bus 1102 provides communication link in the various parts of electronic equipment 1100, and may be implemented as single bus, bus combination or implement in any other suitable manner.

Electronic building brick 1110 is coupled to system bus 1102.Electronic building brick 1110 can comprise the combination of any circuit or circuit.In one embodiment, electronic building brick 1110 comprises the processor 1112 can with any type.As used herein, " processor " represents the computing circuit of any type, such as but not limited to processor or the treatment circuit of microprocessor, microcontroller, sophisticated vocabulary calculating (CISC) microprocessor, Jing Ke Cao Neng (RISC) microprocessor, very long instruction word (VLIW) microprocessor, graphic process unit, digital signal processor (DSP), polycaryon processor or other type any.

The circuit that can be included in other type in electronic building brick 1110 is custom circuit, application-specific integrated circuit (ASIC) (ASIC) etc., such as, for the one or more circuit (such as telecommunication circuit 1114) in wireless device, described wireless device is mobile phone, personal digital assistant, portable computer, two-way radio and similar electronic system such as.IC can perform the function of other type any.

Electronic equipment 1100 (such as, the driver of such as solid-state drive or flash memories) external memory storage 1120 can also be comprised, it correspondingly can comprise the one or more memory components being suitable for special applications, the main storage 1122 of such as random access memory (RAM) form, one or more hard disk drive 1124 or manage one or more drivers of removable medium 1126 of such as CD (CD), flash-storing card, Digital video disc (DVD) etc.

Electronic equipment 1100 can also comprise one or more display device 1116, one or more loud speaker 1118, keyboard or controller 1130, and described keyboard or controller 1130 optionally can comprise mouse, tracking ball, touch-screen, speech recognition apparatus or allow system user information to be input in electronic equipment 1100 and receive any miscellaneous equipment of information from electronic equipment 1100.

In order to illustrate method and apparatus disclosed herein better, there is provided herein the non-limiting list of embodiment:

Example 1 is the device for the method for the manufacture of stacking semiconductor device, and it comprises: on the first tube core and the second tube core, form edge, described edge is extended the first and second tube cores in the horizontal; By the second die-stack on the first tube core; And at heap poststack, get out one or more via hole through edge, described one or more via hole extends between the first and second tube cores.

In example 2, the subject content of example 1 optionally can comprise and utilizes the one or more via hole of filled with conductive material, with electrical interconnection first and second tube core.

In example 3, the subject content of any one in example 1-2 can optionally comprise: wherein, and formation edge is included on the first tube core and the second tube core and forms dielectric portion, utilizes dielectric portion to form described edge.

In example 4, the subject content of any one in example 1-3 can optionally comprise: wherein, forms dielectric portion and is included in moulded resin around the first tube core and the second tube core, utilizes resin to form edge.

In example 5, the subject content of any one in example 1-4 can optionally comprise: form the first reconstruct die panel, described first reconstruct die panel is included in more than first tube core molded in panel frame, and described more than first tube core comprises the first tube core; And forming the second reconstruct die panel, described second reconstruct die panel is included in more than second tube core molded in another panel frame, and described more than second tube core comprises the second tube core; And form edge and comprise the periphery utilizing dielectric substance to surround the tube core in the first and second reconstruct die panel.

In example 6, the subject content of any one in example 1-5 can optionally comprise: choose the tube core in described more than first tube core and more than second tube core, to guarantee only exercisable tube core to be reconstructed die panel for the formation of first and second.

In example 7, the subject content of any one in example 1-6 can optionally comprise: the independent stacked body being separated the first and second bonding tube cores from the first and second reconstruct die panel.

In example 8, the subject content of any one in example 1-7 can optionally comprise: wherein, gets out one or more via hole and is made up of one or more in laser drill, machine drilling or chemical etching.

In example 9, the subject content of any one in example 1-8 can optionally comprise: wherein, and the one or more via holes got out through the first and second tube cores are continuous print.

In example 10, the subject content of any one in example 1-9 can optionally comprise: the one or more redistributing layers one or more in the first or second tube core or described edge being formed conductive trace, one or more via hole communicates with conductive trace at edge.

In example 11, the subject content of any one in example 1-10 can optionally comprise: wherein, the first die-stack is comprised relative to staggered second tube core of the first tube core on the second tube core, to expose at least one bond pad of the second tube core.

In example 12, the subject content of any one in example 1-11 can optionally comprise: wherein, get out the edge that one or more via hole comprises through the first tube core and get out at least one via hole, at least one via hole described extends at least one bond pad of the second tube core.

In example 13, the subject content of any one in example 1-12 can optionally comprise: for the manufacture of the method for stacking semiconductor device, it comprises: multiple in sort out tube core operate tube core, test multiple operability operating tube core; And formation at least the first reconstruct die panel comprises: by multiple die arrangement that operate of selection in panel frame, and multiple in panel frame operate moulded resin around tube core, to form described first reconstruct die panel, the edge utilizing resin to be formed is from multiple each horizontal expansion operated tube core.

In example 14, the subject content of any one in example 1-13 can optionally comprise: repeat to arrange and be molded, to form the second reconstruct die panel, edge is extended multiple each tube core operating tube core of the second reconstruct die panel in the horizontal.

In example 15, the subject content of any one in example 1-14 can optionally comprise: the first reconstruct die panel is coupled to the second reconstruct die panel; And one or more via hole is got out in first and second reconstruct die panel of coupling, one or more via hole operates in the edge of tube core multiple, and one or more via hole extends between the first and second reconstruct die panel.

In example 16, the subject content of any one in example 1-15 can optionally comprise: wherein, the first reconstruct die panel is coupled to the second reconstruct die panel and comprises each multiple in the first and second reconstruct die panel are operated tube cores alignment.

In example 17, the subject content of any one in example 1-16 can optionally comprise: the first and second reconstruct die panel are divided into multiple multilayer encapsulation, each in multilayer encapsulation comprises: multiple at least two tube cores operated in tube core of the first and second reconstruct die panel, and at least one via hole in one or more via hole.

In example 18, the subject content of any one in example 1-17 can optionally comprise: wherein, gets out one or more via hole and comprise and get out one or more via hole through multiple edge operating tube core in the first and second reconstruct die panel of coupling.

In example 19, the subject content of any one in example 1-18 can optionally comprise: utilize the one or more via hole of filled with conductive material, to reconstruct die panel electric coupling by first and second.

In example 20, the subject content of any one in example 1-19 can optionally comprise: wherein, form at least the first reconstruct die panel to be included in and multiplely to operate the one or more redistributing layers forming conductive trace on tube core and corresponding edge, one or more via hole communicates with conductive trace at edge.

In example 21, the subject content of any one in example 1-20 can optionally comprise: wherein, selection multiple are operated die arrangement to comprise in panel frame selection multiplely operated in the one or more staggered die-stack body of die arrangement in panel frame, each die-stack body in one or more staggered die-stack body comprises two or more tube cores, and at least one of them and the adjacent tube core of two or more tube cores interlock.

In example 22, the subject content of any one in example 1-21 can optionally comprise: wherein, multiple each that operate that moulded resin around tube core is included in one or more staggered die-stack body around moulded resin.

In example 23, the subject content of any one in example 1-22 can optionally comprise: semiconductor device, and it comprises: the first tube core; Be stacked on the second tube core on the first tube core; Be extended the edge of each of the first and second tube cores in the horizontal; The first redistributing layer extended on the edge of the first tube core and the first tube core; And extending through at least one of them one or more via holes at corresponding edge, one or more via hole is communicated with the first and second tube cores by edge.

In example 24, the subject content of any one in example 1-23 can optionally comprise: wherein, corresponding edge is molded resin edge molded around corresponding first and second tube cores, one or more via hole extend through molded resin edge at least one of them.

In example 25, the subject content of any one in example 1-24 optionally can be included in the dielectric portion formed on each in the first and second tube cores, dielectric portion comprises one or more edge, and one or more via hole extends through dielectric portion.

In example 26, the subject content of any one in example 1-25 can optionally comprise: wherein, one or more via hole and the first and second tube cores spaced.

In example 27, the subject content of any one in example 1-26 can optionally comprise the second redistributing layer, and it extends on the edge of the second tube core and the second tube core.

In example 28, the subject content of any one in example 1-27 can optionally comprise: the first and second redistributing layers provide the fan-out structure of conductive trace, described conductive trace extends and exceeds on the corresponding area occupied of the first and second tube cores, and one or more via hole communicates with the first and second redistributing layers.

In example 29, the subject content of any one in example 1-27 can optionally comprise: wherein, and via hole is by after the second die-stack is on the first tube core, at the via hole got out at least formed in one of them at corresponding edge.

In example 30, the subject content of any one in example 1-29 optionally can comprise the multiple tube cores comprising the first and second tube cores, edge is from each the tube core horizontal expansion multiple tube core, multiple tube core is in stacked structure, and one or more via hole extends through at least two edges in the corresponding edge of multiple tube core.

In example 31, the subject content of any one in example 1-30 can optionally comprise: wherein, and the second tube core and the first tube core interlock, and the second tube core comprises and depends at least one staggered bond pad exposed.

In example 32, the subject content of any one in example 1-31 can optionally comprise: wherein, and one or more via hole extends at least one bond pad exposed of the second tube core through the edge of the first tube core.

Each in these non-limiting examples is independently, or can combine with the form of any arrangement or combination and other example one or more.

Above embodiment comprises the reference to accompanying drawing, which form a part for embodiment.Illustrate by way of example, accompanying drawing shows the specific embodiment wherein can putting into practice present disclosure.These embodiments are also referred to as " example " in this article.This example can comprise the key element except those key elements shown or described.But the present inventor also contemplates the example wherein only providing those key elements shown or described.In addition, relative to particular example (or one or more aspect), or relative to shown in herein or described other example (or one or more aspect), the present inventor also contemplate use shown in or the described combination in any of those key elements (or one or more aspect) or the example of arrangement.

In this document, as common in patent document, term " " for comprising one or more than one, independent of other example any or the use of " at least one " or " one or more ".In this document, term " or " be used in reference to without exclusiveness or, to make " A or B " comprise " A but be not B ", " B but be not A " and " A and B ", except as otherwise noted.In this document, term " comprises " and " wherein " " comprises " as corresponding term and the equivalent of popular language of " wherein ".Equally, in following claim, term " comprises " and " comprising " is open, that is, comprise except key element listed after this term in the claims, except the system of key element, equipment, goods, composition, formula or technique be still regarded as dropping in the scope of this claim.In addition, in following claim, term " first ", " second " and " the 3rd " etc. only with marking, and are not will apply numerical requirements to its object.

More than illustrate and be intended to be described but not limit.Such as, above-mentioned example (or one or more aspect) can be bonded to each other use.Such as, those of ordinary skill in the art can use other embodiment after illustrating more than reading.Provide summary to follow 37 C.F.R. § 1.72 (b), its character that will reader enable to determine technology disclosure rapidly.Described summary is submitted to when understanding summary and being not used to scope or the meaning explaining or limit claim.Equally, in above embodiment, multiple feature can be grouped in together to simplify present disclosure.This open feature that should not be interpreted as failed call protection is absolutely necessary for any claim.On the contrary, subject matter also can exist when being less than whole feature of specific disclosed embodiment.Therefore, following claim is incorporated in embodiment at this, and wherein each claim relies on self as independent embodiment, and it is expected to, and this embodiment can be bonded to each other with the form of various combination or arrangement.The scope of present disclosure should be determined with reference to claims and for the full breadth of equivalent of this claim entitle.

Claims

1., for the manufacture of a method for stacking semiconductor device, comprising:

First tube core and the second tube core form edge, and described edge is extended described first tube core and described second tube core in the horizontal;

By described second die-stack on described first tube core; And

At heap poststack, get out one or more via hole through described edge, described one or more via hole extends between described first tube core and described second tube core.

2. method according to claim 1, also comprises and utilizes one or more via hole described in filled with conductive material, with the first tube core described in electrical interconnection and described second tube core.

3. method according to claim 1, wherein, formation edge is included on described first tube core and described second tube core and forms dielectric portion, utilizes described dielectric portion to form described edge.

4. method according to claim 3, wherein, forms described dielectric portion and is included in moulded resin around described first tube core and described second tube core, utilize described resin to form described edge.

5. method according to claim 1, comprising:

Form the first reconstruct die panel, described first reconstruct die panel is included in more than first tube core molded in panel frame, and described more than first tube core comprises described first tube core, and

Form the second reconstruct die panel, described second reconstruct die panel is included in more than second tube core molded in another panel frame, and described more than second tube core comprises described second tube core; And

Form edge and comprise the periphery utilizing dielectric substance to surround the tube core in described first reconstruct die panel and described second reconstruct die panel.

6. method according to claim 5, comprises the described tube core in described more than first tube core of selection and described more than second tube core, to guarantee only exercisable tube core to be reconstructed die panel for the formation of described first reconstruct die panel and described second.

7. method according to claim 6, comprises the independent stacked body being separated the first and second bonding tube cores from described first reconstruct die panel and described second reconstruct die panel.

8. method according to claim 1, wherein, gets out described one or more via hole and is made up of one or more in laser drill, machine drilling or chemical etching.

9. method according to claim 1, wherein, getting out described one or more via hole through described first tube core and described second tube core is continuous print.

10. method according to claim 1, form one or more redistributing layers of conductive trace on to be included in described first tube core or described second tube core or described edge one or more, described one or more via hole communicates with described conductive trace in described edge.

11. methods according to claim 1, wherein, comprise described first die-stack and described second tube core are interlocked relative to described first tube core, to expose at least one bond pad of described second tube core on described second tube core.

12. methods according to claim 11, wherein, get out the described edge that described one or more via hole comprises through described first tube core and get out at least one via hole, at least one via hole described extends at least one bond pad described of described second tube core.

13. 1 kinds, for the manufacture of the method for stacking semiconductor device, comprising:

Selection tube core obtains multiplely operating tube core, tests described multiple operability operating tube core; And

Form at least the first reconstruct die panel, comprising:

By multiple die arrangement that operate of described selection in panel frame, and

Described multiple in described panel frame operate moulded resin around tube core, and to form described first reconstruct die panel, the edge utilizing described resin to be formed is from described multiple each operated tube core horizontal expansion operated tube core.

14. methods according to claim 13, comprise and repeat to arrange and be molded, and to form the second reconstruct die panel, edge is extended described multiple each tube core operated in tube core of described second reconstruct die panel in the horizontal.

15. methods according to claim 14, comprise and described first reconstruct die panel are coupled to described second reconstruct die panel; And

One or more via hole is got out in the first reconstruct die panel and the second reconstruct die panel of described coupling, described one or more via hole multiplely to operate in the described edge of tube core described, and described one or more via hole extends between described first reconstruct die panel and described second reconstruct die panel.

16. methods according to claim 15, wherein, described first reconstruct die panel is coupled to described second reconstruct die panel to comprise each described multiple in described first reconstruct die panel and described second reconstruct die panel are operated tube cores alignment.

17. methods according to claim 15, comprise and described first reconstruct die panel and described second reconstruct die panel are divided into multiple multilayer encapsulation, each in described multilayer encapsulation comprises:

Described multiple at least two tube cores operated in tube core of described first reconstruct die panel and described second reconstruct die panel, and

At least one via hole in described one or more via hole.

18. methods according to claim 15, wherein, get out one or more via hole and comprise and get out one or more via hole through described multiple described edge operating tube core in the first reconstruct die panel and described second reconstruct die panel of described coupling.

19. methods according to claim 15, comprise and utilize one or more via hole described in filled with conductive material, with the first reconstruct die panel described in electric coupling and described second reconstruct die panel.

20. methods according to claim 13, wherein, form at least described first reconstruct die panel to be included in and describedly multiplely to operate the one or more redistributing layers forming conductive trace on tube core and corresponding edge, described one or more via hole communicates with described conductive trace in described edge.

21. methods according to claim 13, wherein, multiple die arrangement that operate of described selection are comprised multiple die arrangement that operate of described selection in the one or more staggered die-stack body in described panel frame in described panel frame, each die-stack body in described one or more staggered die-stack body comprises two or more tube cores, and at least one of them and the adjacent tube core of two or more tube cores described interlock.

22. methods according to claim 21, wherein, multiplely to operate around tube core molded described resin described and are included in molded described resin around described one or more staggered die-stack body.

23. 1 kinds of stacking semiconductor device, comprising:

First tube core;

Second tube core, described second die-stack is on described first tube core;

Edge, described edge is extended each tube core in the first tube core and described second tube core in the horizontal;

First redistributing layer, described first redistributing layer extends on the edge of described first tube core and described first tube core; And

One or more via hole, described one or more via hole extend through corresponding edge at least one of them, described one or more via hole communicates with described second tube core with described first tube core via described edge.

24. stacking semiconductor device according to claim 23, wherein, corresponding edge is molded resin edge molded around corresponding first tube core and the second tube core, described one or more via hole extend through described molded resin edge at least one of them.

25. stacking semiconductor device according to claim 23, be included in the dielectric portion formed on each in described first tube core and described second tube core, described dielectric portion comprises described one or more edge, and described one or more via hole extends through described dielectric portion.

26. stacking semiconductor device according to claim 23, wherein, described one or more via hole and described first tube core and described second tube core spaced.

27. stacking semiconductor device according to claim 23, comprise the second redistributing layer, and described second redistributing layer extends on the edge of described second tube core and described second tube core.

28. stacking semiconductor device according to claim 27, described first redistributing layer and described second redistributing layer provide the fan-out structure of conductive trace, described conductive trace extends and exceeds on the corresponding area occupied of described first tube core and described second tube core, and described one or more via hole communicates with described second redistributing layer with described first redistributing layer.

29. stacking semiconductor device according to claim 23, wherein, described via hole is after described second die-stack is on described first tube core, at the via hole got out at least formed in one of them at corresponding edge.

30. stacking semiconductor device according to claim 23, comprise the multiple tube cores comprising described first tube core and described second tube core, edge is from each the tube core horizontal expansion described multiple tube core, described multiple tube core is in stacked structure, and described one or more via hole extends through at least two edges in the corresponding edge of described multiple tube core.

31. stacking semiconductor device according to claim 23, wherein, described second tube core interlocks relative to described first tube core, and described second tube core comprises and depends on described at least one staggered bond pad exposed.

32. stacking semiconductor device according to claim 31, wherein, described one or more via hole extends at least one bond pad exposed described of described second tube core through the described edge of described first tube core.