WO2008142764A1 - 積層型パッケージ、及び、積層型パッケージの形成方法 - Google Patents

積層型パッケージ、及び、積層型パッケージの形成方法 Download PDF

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Publication number
WO2008142764A1
WO2008142764A1 PCT/JP2007/060279 JP2007060279W WO2008142764A1 WO 2008142764 A1 WO2008142764 A1 WO 2008142764A1 JP 2007060279 W JP2007060279 W JP 2007060279W WO 2008142764 A1 WO2008142764 A1 WO 2008142764A1
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Prior art keywords
semiconductor chip
connection terminals
stacked package
semiconductor chips
stacking
Prior art date
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PCT/JP2007/060279
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English (en)
French (fr)
Inventor
Masato Ikeda
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Kabushiki Kaisha Nihon Micronics
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Publication date
Application filed by Kabushiki Kaisha Nihon Micronics filed Critical Kabushiki Kaisha Nihon Micronics
Priority to JP2009515033A priority Critical patent/JPWO2008142764A1/ja
Priority to PCT/JP2007/060279 priority patent/WO2008142764A1/ja
Priority to US12/596,088 priority patent/US8203202B2/en
Publication of WO2008142764A1 publication Critical patent/WO2008142764A1/ja

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    • H01L2924/3512—Cracking

Abstract

　各半導体チップへの回路の割り当てや各半導体チップの接続用端子の位置の自由度が高い、しかも、当該半導体チップモジュールを取付基板に容易に確実に取り付けることができる半導体チップモジュールを提供する。 　本発明は、表面に設けられている回路パターンと連結する接続用端子の一部が側面に設けられている、複数の半導体チップを重ね合わせて結合した半導体チップモジュールに関する。ここで、最下層の積層要素は、取付側の面に、複数の電極要素（例えば半田ボール）を配置すると共に、各電極要素といずれかの接続用端子とを回路パターンで接続した、外部の取付基板との取付専用のものである、半導体チップ又はインターポーザである。また、各半導体チップ及び最下層の積層要素における側面の接続用端子部分が、側面を延びている配線パターンによって相互に接続されている。
PCT/JP2007/060279 2007-05-18 2007-05-18 積層型パッケージ、及び、積層型パッケージの形成方法 WO2008142764A1 (ja)

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JP2009515033A JPWO2008142764A1 (ja) 2007-05-18 2007-05-18 積層型パッケージ、及び、積層型パッケージの形成方法
PCT/JP2007/060279 WO2008142764A1 (ja) 2007-05-18 2007-05-18 積層型パッケージ、及び、積層型パッケージの形成方法
US12/596,088 US8203202B2 (en) 2007-05-18 2007-05-18 Stacked package and method for forming stacked package

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