CN106571346A - 用于芯片封装件的结构和形成方法 - Google Patents

用于芯片封装件的结构和形成方法 Download PDF

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Publication number
CN106571346A
CN106571346A CN201610080185.0A CN201610080185A CN106571346A CN 106571346 A CN106571346 A CN 106571346A CN 201610080185 A CN201610080185 A CN 201610080185A CN 106571346 A CN106571346 A CN 106571346A
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layer
conductive component
chip package
encapsulated layer
boundary layer
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CN201610080185.0A
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CN106571346B (zh
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洪瑞斌
黄震麟
刘献文
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了芯片封装件的结构和形成方法。芯片封装件包括半导体管芯和部分或全部地包封半导体管芯的封装层。芯片封装件也包括穿透封装层的导电部件。芯片封装件还包括界面层，该界面层连续地围绕导电部件。界面层位于导电部件和封装层之间，并且界面层由金属氧化物材料制成。

Description

用于芯片封装件的结构和形成方法
技术领域
本发明的实施例涉及集成电路结构，更具体地，涉及用于芯片封装件的结构和形成方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体层以及使用光刻和蚀刻工艺图案化各个材料层以在半导体衬底上形成电路组件和元件来制造这些半导体器件。
半导体工业通过不断减小最小部件尺寸持续地改进各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多的组件集成至给定的区域。在一些应用中，这些更小的电子组件也使用利用更小的面积和更小的高度的更小的封装件。
已经开始开发诸如堆叠式封装(PoP)的新封装技术，其中，具有器件管芯的顶部封装件接合至具有另一器件管芯的底部封装件。通过采用新封装技术，将具有不同或类似功能的封装件集成在一起。这些用于半导体器件的新型的封装技术面临着制造挑战。
发明内容
本发明的实施例提供了一种芯片封装件，包括：半导体管芯；封装层，至少部分地包封所述半导体管芯；导电部件，位于所述封装层中；以及界面层，位于所述导电部件和所述封装层之间，其中，所述界面层由金属氧化物材料制成。
本发明的另一实施例提供了一种芯片封装件，包括：半导体管芯；封装层，至少部分地包封所述半导体管芯；导电部件，穿透所述封装层；以及界面层，连续地围绕所述导电部件，其中，所述界面层位于所述导电部件和所述封装层之间，并且所述界面层由金属氧化物材料制成。
本发明的又一实施例提供了一种用于形成芯片封装件的方法，包括：在载体衬底上方形成导电部件；在所述载体衬底上方设置半导体管芯；在所述载体衬底上方形成封装层以至少部分地包封所述半导体管芯和所述导电部件；以及在形成所述封装层之前加热所述导电部件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1N是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。
图2是根据一些实施例的芯片封装件中的导电部件的顶视图。
图3A至图3C是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。
图4是根据一些实施例的部分芯片封装件的截面图。
图5是根据一些实施例的部分芯片封装件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
描述了本发明的一些实施例。图1A至图1N是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。可以在图1A至图1N所描述的阶段之前、期间和/或之后提供额外的操作。对于不同的实施例，描述的一些阶段可以被替换或消除。可以将额外的部件添加至半导体器件结构。对于不同的实施例，以下所描述的一些部件可以被替换或消除。虽然以特定顺序实施的操作讨论了一些实施例，但是这些操作可以用另一逻辑顺序实施。
如图1A所示，根据一些实施例，在载体衬底100上方依次沉积或层压粘合层102和基层104。在一些实施例中，载体衬底100用作临时支撑衬底。载体衬底100可以由半导体材料、陶瓷材料、聚合物材料、金属材料、另一合适的材料或它们的组合制成。在一些实施例中，载体衬底100是玻璃衬底。在一些其它实施例中，载体衬底100是诸如硅晶圆的半导体衬底。
粘合层102可以由胶制成，或可以是诸如箔的层压材料。在一些实施例中，粘合层102是光敏的并且通过光照射容易从载体衬底100分离。例如，对载体衬底100照射紫外(UV)或激光用于使粘合层102分离。在一些实施例中，粘合层102是光热转换(LTHC)涂层。在一些其它实施例中，粘合层102是热敏的。
在一些实施例中，基层104是聚合物层或含聚合物层。基层104可以是聚对苯撑苯并双噻唑(PBO)层、聚酰亚胺(PI)层、阻焊(SR)层、味之素增强膜(ABF)、管芯附接膜(DAF)、另一合适的层或它们的组合。
之后，如图1B所示，根据一些实施例，在基层104上方沉积晶种层106。在一些实施例中，晶种层106由铜制成。在一些实施例中，晶种层106使用物理汽相沉积(PVD)工艺、化学汽相沉积(CVD)工艺、另一适用的工艺或它们的组合沉积。然而，本发明的实施例不限于此。其它导电膜也可以用作晶种层106。例如，晶种层106可以由Ti、Ti合金、Cu、Cu合金或它们的组合制成。Ti合金和Cu合金可以包括银、铬、镍、锡、金、钨、另一合适的元素或它们的组合。
如图1C所示，根据一些实施例，在晶种层106上方形成掩模层108。掩模层108具有暴露部分晶种层106的一个或多个开口110。掩模层108的开口限定了设计形成诸如封装通孔的导电部件的位置。在一些实施例中，掩模层108由光刻胶材料制成。掩模层108的开口可以通过光刻工艺形成。光刻工艺可以包括曝光和显影工艺。
之后，如图1D所示，根据一些实施例，形成导电部件112，去除掩模层108，以及图案化晶种层106以形成晶种元件106a。在一些实施例中，导电材料沉积在暴露的部分晶种层106上方以完全或部分地填充开口110。导电材料可以包括铜。之后，如图1D所示，去除掩模层108并且沉积的导电材料形成多个导电部件112(或导电柱)。在随后的晶种层106的蚀刻期间，导电部件112可以用作掩模元件。因此，图案化晶种层106以形成晶种元件106a。
如图1E所示，根据一些实施例，半导体管芯114附接在基层104上。在一些实施例中，半导体管芯114的后侧面向基层104，其中半导体管芯114的前侧面朝上。每个半导体管芯114均包括半导体衬底116、钝化层118、导电焊盘122、保护层120和位于半导体管芯的前侧处的连接器124。在半导体衬底116中或半导体衬底116上方可以形成多个器件元件。器件元件可以包括有源器件和/或无源器件。在半导体管芯114和基层104之间可以使用诸如管芯附接膜(DAF)的粘合膜(未示出)。
如图1F所示，根据一些实施例，加热导电部件112以形成导电部件112’。在一些实施例中，加热操作包括导电部件112中的晶粒的晶粒生长，引起导电部件112’的形成。在一些实施例中，导电部件112的平均晶粒大小在从约220μm至约240μm的范围内。在一些实施例中，导电部件112’的平均晶粒大小增加至在从约270μm至约290μm的范围内。在一些实施例中，导电部件112’的平均晶粒大小增加至在从约250μm至约320μm的范围内。
在一些实施例中，在温度处于从约200摄氏度至约250摄氏度的范围内实施加热操作。在一些其它实施例中，在温度处于在从约200摄氏度至约400摄氏度的范围内实施加热操作。操作时间可以在从约30分钟至约2小时的范围内。在一些实施例中，如图1F所示的结构放置到主要由氮气或其它惰性气体和诸如约20至约100ppm的低浓度的氧气填充的容器中。加热操作可以包括使用炉、灯、激光、另一合适的加热源或它们的组合加热导电部件。
在一些实施例中，导电部件112’的电阻率低于导电部件112的电阻率。由加热操作引起的晶粒生长可能会减小晶界的数量。在一些实施例中，导电部件112’的表面形貌不同于导电部件112的表面形貌。形貌的不同可能由晶粒生长引起。例如，由于加热操作之后的晶粒生长，导电部件112’的侧壁可能呈波浪形。之后将会更详细地描述导电部件112’的形貌。
在一些实施例中，如图1F所示，根据一些实施例，在加热操作期间，界面层113形成为围绕导电部件112’。在一些实施例中，界面层113由金属氧化物材料制成。由于加热操作期间的氧化反应，形成了界面层113。
在一些实施例中，导电部件112’包括金属材料，并且界面层113也包括导电部件112’的相同金属材料。在一些实施例中，导电部件112’包括铜，以及界面层113包括氧化铜。
在一些实施例中，每个界面层113均与相应的一个导电部件112’直接接触。在一些实施例中，每个界面层113的厚度在从约至约的范围内。在一些实施例中，界面层的厚度为从约至约
在一些实施例中，每个界面层113均连续地围绕相应的一个导电部件112’。图2是根据一些实施例的芯片封装件中的导电部件的顶视图。导电部件112’由界面层113连续地围绕。虽然图2中所示的导电部件112’具有圆形的顶视图，但是本发明的实施例不限于此。导电部件112’的顶视图的形状可以包括类圆形状、椭圆形状、正方形状、矩形形状或另一合适的形状。
如图1G所示，根据一些实施例，在基层104、导电部件112’和半导体管芯114上方形成封装层128。在一些实施例中，封装层128包括聚合物材料。在一些实施例中，封装层128包括模塑料。在一些实施例中，封装层128包封半导体管芯114，包括覆盖它们的顶面和侧壁。在一些其它实施例中，封装层128部分地包封半导体管芯114。例如，半导体管芯114的上部从封装层128的顶面突出。在一些实施例中，封装层128与界面层113直接接触。在一些实施例中，如图1G所示，界面层113将导电部件112’与封装层128分隔开。
在一些实施例中，在基层104、导电部件112’和半导体管芯114上方施加液体模塑料材料以包封导电部件112’和半导体管芯114。在一些实施例中，之后，施加热工艺以硬化模塑料材料并且将模塑料材料转换成封装层128。在一些实施例中，在温度处于从约200摄氏度至约230摄氏度的范围内实施热工艺。热工艺的操作时间可以在从约1小时至约3小时的范围内。
在封装层128的形成之前，已经加热导电部件112’以引起晶粒生长。由于在先前的加热操作之后，导电部件112’的晶粒大小已经增加，因此随后用于形成封装层128的热工艺可能不能引起导电部件112’的进一步晶粒生长。即使出现导电部件112’的晶粒生长，导电部件112’的进一步晶粒生长是有限的。因此，导电部件112’的形貌可以保持与热工艺之前的导电部件112’的形貌基本相同。在导电部件112’和封装层128之间没有引起高应力。可以确保导电部件112’和封装层128之间的粘合。
在一些其它情况下，在封装层的形成之前，不将导电部件加热至引起晶粒生长。用于形成封装层的热工艺可以引起导电部件的晶粒生长。因此，导电部件的表面形貌可能改变，将负面影响导电部件和封装层之间的粘合。因此，可能减小芯片封装件的可靠性和性能。
根据本发明的一些实施例，在封装层128的形成之前，加热导电部件112’。由于减小或避免了导电部件112’的形貌改变，因此在封装层128和围绕导电部件112’的界面层113基本没有形成应力或应变。相应地，提高了封装层128和围绕导电部件112’的界面层113之间的界面质量。因此，提高了芯片封装件的可靠性和性能。
如图1H所示，根据一些实施例，削薄封装层128以暴露半导体管芯114的连接器124和导电部件112’。可以使用平坦化工艺削薄封装层128。平坦化工艺可以包括研磨工艺、化学机械抛光(CMP)工艺、蚀刻工艺、另一合适的工艺或它们的组合。在一些实施例中，如图1H所示，在平坦化工艺期间，去除导电部件112’的顶部上的部分界面层113。在一些实施例中，在平坦化工艺期间，去除导电部件112’的上部。在一些实施例中，导电部件112’的顶部和半导体管芯114的连接器124基本是共面的。
之后，如图1I所示，根据一些实施例，在如图1H所示的结构上方形成包括再分布层130和钝化层132的再分布结构。再分布层130可以包括彼此不电连接的多个部分。再分布层130形成至导电部件112’和连接器124的多个电连接。例如，部分再分布层130通过一个连接器124电连接至一个导电焊盘122。部分再分布层130将一个连接器124电连接至一个导电部件112’。部分再分布层130电连接至一个导电部件112’。再分布层130的图案可以根据需求调整。例如，如果不同的电路布局用于建立导电部件112’和导电焊盘122之间的连接，则再分布层130的图案可以相应地改变。导电部件112’可以用作封装通孔(TPV)。在一些实施例中，TPV围绕半导体管芯114。
在一些实施例中，再分布层130由金属材料制成。金属材料可以包括铜、铝、钨、镍、钛、金、铂、另一合适的材料或它们的组合。在一些实施例中，钝化层132包括一层或多层。钝化层132可以具有暴露部分再分布层130的开口(未示出)。可以在暴露的再分布层130上方形成接合焊盘(未示出)。钝化层132由介电材料制成并且为随后的接合工艺期间引起的接合应力提供应力减轻。在一些实施例中，钝化层132由诸如聚酰亚胺、PBO等或它们的组合的聚合物材料制成。可选地或额外地，钝化层132可以包括苯并环丁烯(BCB)。在一些实施例中，钝化层132包括氧化硅、氮氧化硅、氮化硅、碳化硅、另一合适的材料或它们的组合。
可以使用多个沉积、涂布和/或蚀刻工艺以形成包括再分布层130和钝化层132的再分布结构。在一些实施例中，在形成再分布结构期间，实施一个或多个热工艺。例如，部分钝化层132可以由使用包括热工艺的工艺形成的聚合物材料制成。如上所述，由于已经加热导电部件112’而引起晶粒生长，因此，在再分布结构的形成之后，基本保持了导电部件112’的形貌。由于减小或避免了导电部件112’的形貌改变，因此封装层128和围绕导电部件112’的界面层113基本没有形成应力或应变。仍然保持了封装层128和围绕导电部件112’的界面层113之间的界面质量。因此，提高了芯片封装件的可靠性和性能。
如图1J所示，根据一些实施例，在钝化层132上方形成连接器134。连接器134可以通过钝化层132的开口(未示出)安装在(或连接至)再分布结构的接合焊盘(未示出)上。一些连接器134通过再分布层130电连接至一个半导体管芯114。一些连接器134通过再分布层130和一个导电部件112’电连接至其它元件。连接器134可以包括焊料凸块。可以在连接器134下面形成凸块下金属(UBM)层(未示出)。
如图1K所示，根据一些实施例，在形成连接器134之后，翻转如图1J所示的结构并且附接至载体136，并且去除载体衬底100。载体136包括光敏的或热敏的并且易从连接器134分离的胶带。在一些实施例中，去除载体衬底100和粘合层102。可以提供合适的光以去除粘合层102以及去除载体衬底100。
如图1L所示，根据一些实施例，去除部分基层104以形成暴露导电部件112’的开口138。在这些情况下，也去除了晶种元件106a。在一些其它实施例中，没有去除或没有全部去除晶种元件106a。在这些情况下，开口138暴露了晶种元件106a。在一些实施例中，施加激光钻孔工艺以形成开口138。诸如蚀刻工艺的另一适用的工艺也可以用于形成开口138。
在一些实施例中，实施切割工艺以将如图1L所示的结构分成多个芯片封装件。在一些其它实施例中，在切割工艺之前，可以在如图1L所示的结构上堆叠或接合更多元件。
如图1M所示，根据一些实施例，在如图1L所示的结构上方堆叠一个或多个元件140。在一些实施例中，每个元件140均包括包含一个或多个半导体管芯的另一封装结构。在一些其它实施例中，每个元件140均包括半导体管芯。
在一些实施例中，如图1M所示，使用一个或多个连接器142以实现元件140和导电元件112’之间的接合。每个连接器142可以包括焊料凸块、金属柱、另一合适的连接器或它们的组合。在一些实施例中，每个连接器142均与相应的一个导电部件112’和界面层113直接接触。
在一些实施例中，连接器142是焊料凸块，并且连接器142的形成涉及用于回流焊料材料的热工艺。如上所述，由于已经加热导电部件112’而引起晶粒生长，因此在形成连接器142之后，可以基本保持导电部件112’的形貌。由于减小或避免了导电部件112’的形貌改变，因此在封装层128和围绕导电部件112’的界面层113之间基本没有形成应力或应变。仍然保持了封装层128和围绕导电部件112’的界面层113之间的界面质量。因此提高了芯片封装件的可靠性和性能。
如图1N所示，根据一些实施例，实施切割工艺以将如图1M所示的结构分成彼此分隔开的多个芯片封装件。如图1N所示，图1N中示出了一个芯片封装件。在一些实施例中，去除了载体136。
可以对本发明的实施例作出许多变化和/或修改。例如，虽然图1A至图1N所示的实施例提供了具有“扇出”部件的芯片封装件，但是本发明的实施例不限于此。本发明的一些其它实施例包括具有“扇入”部件的芯片封装件。
可以对本发明的实施例作出许多变化和/或修改。例如，虽然在载体衬底上方设置半导体管芯之后加热导电部件，但是本发明的实施例不限于此。在一些实施例中，在载体衬底上方设置半导体管芯之前加热导电部件。
图3A至如3C是根据一些实施例的用于形成芯片封装件的工艺的各个阶段的截面图。如图3A所示，提供了类似于图1D所示的结构的结构。之后，如图3B所示，根据一些实施例，加热导电部件112以形成导电部件112’。如上所述，加热操作可以引起导电部件112’的晶粒生长得更大。之后，类似于图1E示出的，在载体衬底100上方设置半导体管芯114。之后，实施类似于图1G至图1N所示的多个工艺的多个工艺。因此，如图3C所示，形成了芯片封装件。
如上所述，由于加热操作之后的晶粒生长，导电部件112’的侧壁可能呈波浪形。图4是根据一些实施例的部分芯片封装件的截面图。在一些实施例中，图4是图1N中所示的区域A的放大截面图。
如图4所示，根据一些实施例，一个导电部件112’的侧壁具有波浪形形貌。由于导电部件112’内部的晶粒生长，可以引起波浪形的形貌。在一些实施例中，在一个导电部件112’的侧壁的最高部分和最低部分之间的高度变化R1在从约10nm至约130nm的范围内。在一些实施例中，导电部件112’由电镀的光亮铜制成。在这些情况下，一个导电部件112’的侧壁的高度变化可能在从约10nm至约20nm的范围内。
在一些实施例中，界面层113与导电部件112’直接接触。在一个导电部件112’和一个界面层113之间的界面402也具有波浪形的形貌。在一些实施例中，界面层113是共形层。因此，在一个界面层113和封装层128之间的界面404也具有波浪形的形貌。在一些实施例中，在界面404的最高部分和最低部分之间的高度变化R2基本与高度变化R1相同。在一些实施例中，界面404基本平行于界面402。
在一些实施例中，在界面层113和封装层128之间没有形成间隙。然而，本发明的实施例不限于此。在一些情况下，在界面层113和封装层128之间可以形成小的间隙。图5是根据一些实施例的部分芯片封装件的截面图。在一些实施例中，图5是图1N所示的区域A的放大截面图。
在一些实施例中，在界面层113和封装层128之间形成了间隙G。因为预先加热导电部件112’引起晶粒生长，所以减小了导电部件112’和封装层128之间的应力或应变。因此，可以将间隙G控制为较小。在一些实施例中，间隙的宽度W小于高度变化R1或高度变化R2。
本发明的实施例提供了芯片封装件的结构和形成方法。芯片封装件包括穿透诸如模塑料的封装层的导电部件，该封装层包封一个或多个半导体管芯。在封装层的形成之前，加热导电部件以引起晶粒生长。因此，在随后的芯片封装件的封装层或其它元件的形成期间的热操作基本没有引起导电部件的进一步晶粒生长或引起高应力。在随后的热操作之后，可以基本保持导电部件的形貌。由于减小或避免了导电部件的形貌改变，因此在封装层和导电部件中基本没有形成应力或应变。因而保持了封装层和导电部件之间的界面质量。显著地提高了芯片封装件的可靠性和性能。
根据一些实施例，提供了芯片封装件。该芯片封装件包括半导体管芯和部分地或全部地包封半导体管芯的封装层。该芯片封装件也包括封装层中的导电部件。该芯片封装件还包括位于导电部件和封装层之间的界面层。该界面层由金属氧化物材料制成。
在上述芯片封装件中，其中，所述导电部件包括金属材料，以及所述金属氧化物材料包括与所述金属材料的金属元素相同的金属元素。
在上述芯片封装件中，其中，所述导电部件包括金属材料，以及所述金属氧化物材料包括与所述金属材料的金属元素相同的金属元素，所述金属元素包括铜，以及所述金属氧化物材料包括氧化铜。
在上述芯片封装件中，其中，所述封装层包括模塑料。
在上述芯片封装件中，其中，所述界面层与所述导电部件直接接触。
在上述芯片封装件中，其中，所述界面层与所述封装层直接接触。
在上述芯片封装件中，其中，所述界面层将所述导电部件与所述封装层分隔开。
在上述芯片封装件中，其中，所述界面层的厚度在从约至约的范围内。
在上述芯片封装件中，还包括：再分布层，位于所述封装层和所述半导体管芯上方，其中，所述再分布层电连接至所述半导体管芯。
在上述芯片封装件中，还包括：再分布层，位于所述封装层和所述半导体管芯上方，其中，所述再分布层电连接至所述半导体管芯，其中，所述导电部件通过所述再分布层电连接至所述半导体管芯。
根据一些实施例，提供了芯片封装件。该芯片封装件包括半导体管芯和部分地或全部地包封半导体管芯的封装层。该芯片封装件也包括穿透封装层的导电部件。该芯片封装件还包括连续地围绕导电部件的界面层。该界面层位于导电部件和封装层之间，并且该界面层由金属氧化物材料制成。
在上述芯片封装件中，其中，所述导电部件包括金属材料，并且所述金属氧化物材料包括与所述金属材料的金属元素相同的金属元素。
在上述芯片封装件中，其中，所述界面层的厚度在从约至约的范围内。
在上述芯片封装件中，其中，所述界面层与所述导电部件直接接触。
在上述芯片封装件中，其中，所述封装层包括聚合物材料。
根据一些实施例，提供了用于形成芯片封装件的方法。该方法包括在载体衬底上方形成导电部件并且在载体衬底上方设置半导体管芯。该方法也包括在载体衬底上方形成封装层以至少部分地包封半导体管芯和导电部件。该方法还包括在形成封装层之前加热导电部件。
在上述方法中，其中，在所述导电部件的加热期间，形成氧化物层以围绕所述导电部件。
在上述方法中，还包括：在所述载体衬底上方形成晶种层；在所述晶种层上方形成掩模层，其中，所述掩模层具有暴露部分所述晶种层的开口；以及在由开口暴露的部分所述晶种层上方电镀导电材料以形成所述导电部件。
在上述方法中，其中，在所述载体衬底上方设置所述半导体管芯之后，加热所述导电部件。
在上述方法中，还包括：去除所述载体衬底；以及在所述半导体管芯上方堆叠封装件结构。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种芯片封装件，包括：
半导体管芯；
封装层，至少部分地包封所述半导体管芯；
导电部件，位于所述封装层中；以及
界面层，位于所述导电部件和所述封装层之间，其中，所述界面层由金属氧化物材料制成。
2.根据权利要求1所述的芯片封装件，其中，所述导电部件包括金属材料，以及所述金属氧化物材料包括与所述金属材料的金属元素相同的金属元素。
3.根据权利要求2所述的芯片封装件，其中，所述金属元素包括铜，以及所述金属氧化物材料包括氧化铜。
4.根据权利要求1所述的芯片封装件，其中，所述封装层包括模塑料。
5.根据权利要求1所述的芯片封装件，其中，所述界面层与所述导电部件直接接触。
6.根据权利要求1所述的芯片封装件，其中，所述界面层与所述封装层直接接触。
7.根据权利要求1所述的芯片封装件，其中，所述界面层将所述导电部件与所述封装层分隔开。
8.根据权利要求1所述的芯片封装件，其中，所述界面层的厚度在从约至约的范围内。
9.一种芯片封装件，包括：
半导体管芯；
封装层，至少部分地包封所述半导体管芯；
导电部件，穿透所述封装层；以及
界面层，连续地围绕所述导电部件，其中，所述界面层位于所述导电部件和所述封装层之间，并且所述界面层由金属氧化物材料制成。
10.一种用于形成芯片封装件的方法，包括：
在载体衬底上方形成导电部件；
在所述载体衬底上方设置半导体管芯；
在所述载体衬底上方形成封装层以至少部分地包封所述半导体管芯和所述导电部件；以及
在形成所述封装层之前加热所述导电部件。
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