CN107768311A - 封装结构的形成方法 - Google Patents

封装结构的形成方法 Download PDF

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Publication number
CN107768311A
CN107768311A CN201611071805.0A CN201611071805A CN107768311A CN 107768311 A CN107768311 A CN 107768311A CN 201611071805 A CN201611071805 A CN 201611071805A CN 107768311 A CN107768311 A CN 107768311A
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China
Prior art keywords
layer
integrated
molding compound
certain embodiments
circuit die
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CN201611071805.0A
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English (en)
Inventor
郑余任
黄育智
陈志华
陈玉芬
蔡豪益
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107768311A publication Critical patent/CN107768311A/zh
Pending legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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Abstract

本公开的实施例提供封装结构及其形成方法，此方法包含提供第一集成电路晶粒并形成重布线结构于第一集成电路晶粒上方，形成基底层于重布线结构上方，基底层具有多个第一开口和多个第二开口，且第一开口宽于第二开口，形成多个第一凸块于重布线结构上方，第一凸块具有下部填入第一开口中。此外，此方法包含通过具有下部填入第二开口中的多个第二凸块将第二集成电路晶粒接合至重布线结构，在第二集成电路晶粒与基底层之间有一空间。此方法也包含形成模塑化合物层于基底层上方，模塑化合物层填入此空间中并围绕第一凸块和第二凸块。

Description

封装结构的形成方法
技术领域
本公开涉及半导体技术，且特别涉及半导体封装结构及其形成方法。
背景技术
半导体装置被使用于各种电子应用中，例如个人电脑、手机、数码相机和其他电子设备。半导体装置的制造是通过依序地沉积绝缘层或介电层、导电层和半导体层于半导体基底上方，并通过微影工艺和蚀刻工艺将各种材料层图案化，以形成半导体基底上的电路组件和元件。许多集成电路一般制造于单一的半导体晶片上，且晶片上个别的晶粒是沿着集成电路之间的切割线切割而单离(singulated)为。一般将个别的晶粒分别封装为例如多芯片模块或其他类型的封装。
半导体产业通过持续降低最小特征部件的尺寸，其可使更多的组件集成于既定面积中，以持续改善各种电子组件(例如晶体管、二极管、电阻器、电容器等等)的集成密度。在一些应用中，这些较小的电子组件也使用较少面积或较小高度的较小封装。
新的封装技术，例如层叠封装(package on package，PoP)已开始发展，其中有着装置晶粒的顶部封装结构接合至有着另一装置晶粒的底部封装结构。通过采用新的封装技术，将各种有着不同或类似功能的封装结构集成在一起。半导体装置的这些相对新类型的封装技术面临制造上的挑战，且这些封装技术并非在全方位皆完全令人满意。
发明内容
在一些实施例中，本公开提供封装结构的形成方法，其包含提供第一集成电路晶粒，形成重布线结构于第一集成电路晶粒上方，形成基底层于重布线结构上方，其中基底层具有多个第一开口和多个第二开口，且第一开口宽于第二开口。此方法还包含形成多个第一凸块于重布线结构上方，其中第一凸块具有一下部填入第一开口中。此方法更包含通过多个第二凸块将第二集成电路晶粒接合至重布线结构，其中第二凸块具有下部填入第二开口中，且在第二集成电路晶粒与基底层之间有一空间，以及形成模塑化合物层于基底层上方，其中模塑化合物层填入此空间中并围绕第一凸块和第二凸块。
在其他实施例中，本公开提供封装结构的形成方法，其包含提供第一集成电路晶粒，实施第一模封成型工艺以形成围绕第一集成电路晶粒的封装层，形成重布线结构于第一集成电路晶粒和封装层上方，形成多个第一凸块于重布线结构上方。此方法还包含在第一凸块形成之后，通过多个第二凸块将第二集成电路晶粒接合至重布线结构，以及实施第二模封成型工艺以形成模塑化合物层于这些第一凸块之间和这些第二凸块之间，其中在第二模封成型工艺期间，模塑化合物层覆盖第一凸块和第二凸块的表面。
在另外一些实施例中，本公开提供封装结构，其包含第一集成电路晶粒，重布线结构位于第一集成电路晶粒上方，基底层位于重布线结构上方，其中基底层具有多个第一开口和多个第二开口。此封装结构包含多个第一凸块填入这些第一开口中，多个第二凸块填入这些第二开口中，其中第一凸块具有大于第二凸块的高度。此封装结构更包含第二集成电路晶粒位于第二凸块上方，其中在第二集成电路晶粒与基底层之间有一空间，以及模塑化合物层位于基底层上方，其中模塑化合物层填入此空间中并围绕第一凸块和第二凸块。
附图说明
根据以下的详细说明并配合所附附图做完整公开。应注意的是，根据本产业的一般作业，附图中的各种特征部件并未必按照比例绘制。事实上，可能任意的放大或缩小各种特征部件的尺寸，以做清楚的说明。
图1A-图1H显示依据本公开的一些实施例的形成封装结构的工艺的各种阶段的剖面示意图。
图2显示依据本公开的一些实施例的封装结构放大的剖面示意图。
图3显示依据本公开的一些实施例的封装结构的剖面示意图。
附图标记说明：
100 承载基底
110 粘着层
120 基底层
130 重布线结构
140、160、260 导电层
150、170、220、250 钝化层
180 导电特征部件
190 粘着膜
200 集成电路晶粒
210 半导体基底
230 导电垫
240 封装层
242、352 填料
270 保护层
280 保护基板
290 载板
300、310 开口
320、330 连接器
320A、330A 上部
320B、330B 下部
340 元件(集成电路晶粒)
341、342 空间
345 回焊工艺
350 模塑化合物层
360 顶表面
370 底表面
400、500 封装结构
A 区域
D1、D2、D3、D4 距离
具体实施方式
要了解的是本说明书以下的公开内容提供许多不同的实施例或范例，以实施本公开的不同特征部件。而本说明书以下的公开内容是叙述各个构件及其排列方式的特定范例，以求简化本公开的说明。当然，这些特定的范例并非用以限定本公开。例如，元件的尺寸并不局限于本公开的范围或值，而可取决于装置的工艺条件及/或所需性质。再者，若是本说明书以下的公开内容叙述了将一第一特征部件形成于一第二特征部件之上或上方，即表示其包含了所形成的上述第一特征部件与上述第二特征部件是直接接触的实施例，亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与上述第二特征部件可能未直接接触的实施例。另外，本发明的说明中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字是为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或特征部件与另一(复数)元件或(复数)特征部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所绘示的方位之外，空间相关用语涵盖使用或操作中的装置的不同方位。例如，若翻转附图中的装置，描述为位于其他元件或特征部件“下方”或“在...之下”的元件，将定位为位于其他元件或特征部件“上方”。因此，范例的用语“下方”可涵盖上方及下方的方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。
本公开描述一些实施例的封装结构及其形成方法。图1A-图1H显示依据本公开的一些实施例的形成封装结构的工艺的各种阶段的剖面示意图。虽然以特定的顺序讨论一些实施例的操作实施，但是可依其他合乎逻辑的顺序实施这些操作，可在图1A-图1H描述的阶段之前、期间及/或之后提供额外的操作，且所描述的一些操作在其他实施例中可被取代或删除。封装结构可加入额外的特征部件，且以下描述的一些特征部件在其他实施例中可被取代或删除。
如图1A所示，依据本公开的一些实施例，提供承载基底100。在一些实施例中，承载基底100用作暂时基底。暂时基底在后续的工艺步骤期间提供机械性和结构性的支撑，其将在后续更加详细描述。承载基底100由半导体材料、陶瓷材料、高分子材料、金属材料、其他合适的材料或前述的组合制成。在一些实施例中，承载基底100为玻璃基底。在一些其他实施例中，承载基底100为半导体基底，例如硅晶片。
之后，依据本公开的一些实施例，将粘着层110设置于承载基底100上方。粘着层110可由粘胶制成或可为例如金属薄片(foil)的贴合材料。在一些实施例中，粘着层110为感光性的，且容易通过光照射脱离承载基底100。举例来说，将紫外(ultra-violet，UV)光或激光照射至承载基底100上，以分离粘着层110。在一些实施例中，粘着层110为光热转换(light-to-heat conversion，LTHC)涂层。在一些其他实施例中，粘着层110为感热性的，且当暴露于热时容易脱离承载基底100。
之后，依据本公开的一些实施例，将基底层(base layer)120沉积或贴合至粘着层110上方。基底层120提供接合集成电路晶粒的结构性的支撑，其将在后续更加详细描述，且帮助减少晶粒偏移的问题。在一些实施例中，基底层120为高分子层或含高分子层。基底层120可为聚对二唑苯(poly-p-phenylenebenzobisthiazole，PBO)层、聚酰亚胺(polyimide，PI)层、阻焊(solder resist，SR)层、味之素增层膜(Ajinomoto buildup film，ABF)、晶粒附接膜(die attach film，DAF)、其他合适层或前述的组合。
如图1A所示，依据本公开的一些实施例，重布线结构130形成于基底层120上方。重布线结构130包含一或多个导电层以及一或多个钝化层。举例来说，重布线结构130包含导电层140和160以及钝化层150和170。
导电层140形成于基底层120上方。钝化层150沉积于基底层120上方，且部分覆盖导电层140。部分的导电层140从钝化层150中的开口暴露出来。导电层160形成于钝化层150上方。导电层160通过钝化层150的开口电性连接导电层140。钝化层170沉积于钝化层150上方，且覆盖导电层160。
在一些实施例中，重布线结构130中的导电层140和160由金属材料制成，此金属材料包含铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)、钽合金、其他合适的材料或前述的组合。在一些实施例中，重布线结构130中的导电层140和160通过电镀工艺、无电电镀工艺、溅镀工艺、化学气相沉积(chemical vapor deposition，CVD)工艺或其他适用的工艺形成。
在一些实施例中，重布线结构130中的钝化层150和170由聚苯并恶唑(polybenzoxazole，PBO)、苯环丁烯(benzocyclobutene，BCB)、硅氧树脂、丙烯酸酯、硅氧烷、其他合适的材料或前述的组合制成。在一些其他实施例中，重布线结构130中的钝化层150和170由非有机材料制成，这些非有机材料包含氧化硅、未掺杂硅酸盐玻璃、氮氧化硅、阻焊剂(SR)、氮化硅、碳化硅、六甲基二硅氮烷(hexamethyldisilazane，HMDS)、其他合适的材料或前述的组合。可使用多个沉积工艺、涂布工艺及/或蚀刻工艺形成重布线结构130。
之后，依据本公开的一些实施例，多个导电特征部件180形成于重布线结构130上方。在一些实施例中，导电特征部件180为导电柱或其他合适的结构。导电特征部件180可被称为贯穿中介层导通孔(through interposer vias，TIVs)。导电特征部件180物理性和电性连接重布线结构130中的其中一个导电层。举例来说，钝化层170具有开口部分地暴露出导电层160。导电特征部件180通过钝化层170中的开口电性连接导电层160。
在一些实施例中，导电特征部件180包含铜(Cu)、铝(Al)、镍(Ni)、铂(Pt)、无铅焊料(例如SnAg、SnCu、SnAgCu)、其他合适的导电材料或前述的组合。在一些实施例中，导电特征部件180通过使用电镀工艺、物理气相沉积(physical vapor deposition，PVD)工艺、化学气相沉积(CVD)工艺、电化学沉积(electrochemical deposition，ECD)工艺、分子束外延(molecular beam epitaxy，MBE)工艺、原子层沉积(atomic layer deposition，ALD)工艺或其他适用的工艺形成。
如图1B所示，依据本公开的一些实施例，将集成电路晶粒200设置于重布线结构130上。在一些实施例中，集成电路晶粒200的前侧(主动面)远离重布线结构130，集成电路晶粒200的背侧(非主动面)面向重布线结构130。然而，本公开的实施例不限于此。在一些其他的实施例中，集成电路晶粒200的前侧面向重布线结构130。
集成电路晶粒200可为包含晶体管、二极管或其他合适的集成电路元件的装置晶粒。装置晶粒也可包含电容器、电感器、电阻器、其他集成电路元件或前述的组合。在一些实施例中，集成电路晶粒200为传感晶粒、逻辑晶粒、中央处理单元(central processingunit，CPU)晶粒、存储器晶粒或其他合适的晶粒。
在一些实施例中，集成电路晶粒200包含半导体基底210、钝化层220和导电垫230。集成电路晶粒200也包含在导电垫230上的连接器，以及围绕连接器的保护层。各种装置元件可形成于半导体基底210中或半导体基底210上方，这些装置元件包含有源元件及/或无源元件。在一些实施例中，装置元件包含指纹辨识装置。在一些其他实施例中，装置元件包含影像传感装置、逻辑装置、存储器装置、其他适用类型的装置或前述的组合。
虽然图1B显示一个集成电路晶粒200在重布线结构130上，但本公开的实施例不限于此。在一些其他的实施例中，多个集成电路晶粒200在重布线结构130上。
在一些实施例中，使用粘着膜190接合或连接集成电路晶粒200和重布线结构130。粘着膜190包含晶粒附接膜(DAF)、其他合适层或前述的组合。
之后，依据本公开的一些实施例，将封装层240沉积于重布线结构130上方。因此，可通过封装层240封装导电特征部件180和集成电路晶粒200。
在一些实施例中，封装层240包含高分子材料。在一些实施例中，封装层240包含模塑化合物(molding compound)。在一些实施例中，封装层240包含填料242分散于其中。填料242可包含绝缘纤维、绝缘粒子、其他合适的元件或前述的组合。在一些实施例中，填料242具有从约2μm至约30μm的范围内的直径。在一些实施例中，填料242的直径在约15μm至约30μm的范围内。
在一些实施例中，可施加液态的模塑化合物材料在重布线结构130上方。液态的模塑化合物材料包含环氧树脂、硅石(silica)、其他合适的材料或前述的组合。在一些实施例中，接着实施热工艺以硬化模塑化合物材料并将模塑化合物材料转变为封装层240。
在一些实施例中，使用模封成型工艺(molding process)沉积封装层240。模封成型工艺包含压缩成型工艺或其他适用的工艺。在一些实施例中，沉积的封装层240的顶表面与导电特征部件180和集成电路晶粒200的顶表面大致共平面。
在一些其他实施例中，沉积的封装层240覆盖导电特征部件180和集成电路晶粒200的顶表面。之后，将沉积的封装层240薄化。因此，暴露出导电特征部件180和集成电路晶粒200。可使用平坦化工艺将沉积的封装层240薄化。平坦化工艺包含研磨工艺、化学机械研磨(chemical mechanical polishing，CMP)工艺、蚀刻工艺、其他适用的工艺或前述的组合。
如图1C所示，依据本公开的一些实施例，包含钝化层250和导电层260的重布线结构形成于封装层240上方。在封装层240上方的重布线结构可包含多个导电层和钝化层。使用多个沉积工艺、涂布工艺及/或蚀刻工艺以形成包含钝化层250和导电层260的重布线结构。
钝化层250沉积于封装层240上方。钝化层250由介电材料制成并为后续的接合工艺期间产生的接合应力提供应力缓和。在一些实施例中，钝化层250由聚苯并恶唑(PBO)、苯环丁烯(BCB)、硅氧树脂、丙烯酸酯、硅氧烷、其他合适的材料或前述的组合制成。在一些其他实施例中，钝化层250由非有机材料制成，这些非有机材料包含氧化硅、未掺杂硅酸盐玻璃、氮氧化硅、阻焊剂(SR)、氮化硅、碳化硅、六甲基二硅氮烷(HMDS)、其他合适的材料或前述的组合。
导电层260埋置于钝化层250中。导电层260电性连接至导电特征部件180和集成电路晶粒200。在一些实施例中，导电层260由金属材料制成，此金属材料包含铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)、钽合金、其他合适的材料或前述的组合。在一些实施例中，导电层260通过电镀工艺、无电电镀工艺、溅镀工艺、化学气相沉积(CVD)工艺或其他适用的工艺形成。
之后，依据本公开的一些实施例，将保护层270沉积于钝化层250上方。保护层270为彩色膜、其他合适层或前述的组合。彩色膜可用以避免封装结构中例如导电层260的一些层暴露于使用者。在一些其他实施例中，不形成保护层270。
之后，依据本公开的一些实施例，提供保护基板280于保护层250上方。在一些实施例中，保护基板280用作指纹辨识装置的面板。保护基板280由非有机材料或其他合适的材料制成。在一些实施例中，保护基板280为玻璃基底、蓝宝石基底或其他合适的基底。在一些其他实施例中，不形成保护基板280。
如图1D所示，依据本公开的一些实施例，将图1C显示的结构翻转并附着至载板290。载板290包含感光性或感热性的胶带，且容易从保护基板280或保护层270脱离。
如上所述，在一些实施例中，不形成保护基板280。因此，保护层270直接接触载板290。然而，本公开的实施例不限于此。在一些实施例中，不形成保护层270和保护基板280。因此，钝化层250直接接触载板290。
之后，将承载基底100移除。在一些实施例中，将承载基底100和粘着层110都移除。可提供合适的光以移除粘着层110和承载基底100。
之后，依据本公开的一些实施例，将基底层120的多个部分移除以形成开口300和310。开口300和310暴露出部分的重布线结构130，例如部分的导电层140。开口300位于导电特征部件180上方，开口310位于集成电路晶粒200上方。开口300的尺寸大于开口310的尺寸。举例来说，开口300宽于开口310。
两个开口300之间的空间大于两个开口310之间的空间。在一些实施例中，其中一个开口300与其中一个开口310之间的空间大致相同于两个开口300之间的空间。在一些其他实施例中，其中一个开口300与其中一个开口310之间的空间不同于两个开口300之间的空间。
在一些实施例中，实施激光钻孔(laser drilling)工艺以形成开口300和310。也可使用其他适用的工艺，例如蚀刻工艺，以形成开口300和310。
如图1E所示，依据本公开的一些实施例，将多个连接器320沉积于重布线结构130上方。连接器320填入开口300中并从基底层120突出。连接器320电性连接至重布线结构130中的导电层140。连接器320包含焊料凸块、金属柱、其他合适的连接器或前述的组合。
在一些实施例中，导电层140为凸块下金属(under bump metallurgy，UBM)结构。导电层140直接接触连接器320，但本公开的实施例不限于此。在一些其他实施例中，一个凸块下金属(UBM)结构位于其中一个连接器320与导电层140之间。凸块下金属(UBM)结构可包含接合垫和一个或多个凸块下金属(UBM)层。
如图1F所示，依据本公开的一些实施例，将元件340堆叠于重布线结构130上方。在一些实施例中，在元件340与基底层120之间有空间341。元件340和集成电路晶粒200在基底层120的相对两侧上。元件340和连接器320并排设置。在一些实施例中，连接器320在元件340的相对两侧上。在一些其他实施例中，连接器320不连续地围绕元件340。
在一些实施例中，元件340为集成电路晶粒。举例来说，此集成电路晶粒为高电压晶粒(high-voltage die)或其他合适的晶粒。然而，本公开的实施例不限于此。在一些其他实施例中，元件340包含封装结构，此封装结构含有一个或多个集成电路晶粒。可依据需求改变元件340。
在一些实施例中，元件340的前侧(主动面)面向集成电路晶粒200的背侧(非主动面)。然而，本公开的实施例不限于此。在一些其他的实施例中，元件340的前侧(主动面)面向集成电路晶粒200的前侧(主动面)。
虽然图1F显示一个元件340在重布线结构130上，但本公开的实施例不限于此。在一些其他的实施例中，多个元件340在重布线结构130上。
在一些实施例中，使用一个或多个连接器330以达成元件340与重布线结构130之间的接合，如图1F所示。连接器330填入开口310中并从基底层120突出。连接器330通过开口310电性连接至重布线结构130中的导电层140。连接器330包含焊料凸块、金属柱、其他合适的连接器或前述的组合。连接器330的尺寸小于连接器320。在一些实施例中，连接器320具有的高度大于连接器330的高度。
如图1F所示，依据本公开的一些实施例，实施回焊(reflow)工艺345于连接器320、元件340和连接器330上方。在一些实施例中，不实施用以沉积底部填充材料的点胶(dispensing)工艺于图1F所示的结构上方。在一些实施例中，在元件340与基底层120之间没有底部填充材料。在一些实施例中，连接器330不被底部填充材料包裹住。
如图1G所示，依据本公开的一些实施例，将模塑化合物层350沉积于重布线结构130上方。模塑化合物层350连续地围绕连接器320并延伸至元件340与重布线结构130之间。因此，可通过模塑化合物层350封装连接器320和连接器330。
模塑化合物层350从连接器320的侧表面连续地延伸至连接器330的侧表面。在一些实施例中，模塑化合物层350直接接触连接器330的侧表面和连接器320的侧表面。在一些实施例中，一部分的模塑化合物层350横向地夹设于其中一个连接器320与其中一个连接器330之间。
在一些实施例中，在形成模塑化合物层350之前，连接器320和330的侧表面从基底层120部分地暴露出来。在一些实施例中，在模塑化合物层350的形成期间覆盖连接器320暴露的侧表面。举例来说，模塑化合物层350和基底层120大致完全覆盖连接器320的侧表面。在一些实施例中，在模塑化合物层350的形成期间覆盖连接器330暴露的侧表面。
模塑化合物层350具有顶表面360和底表面370，顶表面360远离集成电路晶粒200。在一些实施例中，顶表面360大致为平坦的。底表面370面向集成电路晶粒200。在一些实施例中，连接器320的上部320A从顶表面360突出。在一些实施例中，连接器320的下部320B从底表面370突出。在一些实施例中，连接器330的上部330A埋置于模塑化合物层350中。在一些实施例中，连接器330的下部330B从底表面370突出。
在一些实施例中，模塑化合物层350连续地围绕连接器320、连接器330和元件340。模塑化合物层350填入元件340与基底层120之间的空间341中并延伸于连接器320之间。在一些实施例中，在形成模塑化合物层350之前，空间341未被密封。模塑化合物层350也填入其中一个连接器320与元件340之间的空间342中。因此，连接器320、连接器330和元件340埋置于相同的材料层(即模塑化合物层350)中。
模塑化合物层350从连接器320的侧表面连续地延伸至元件(或集成电路晶粒)340的侧表面。在一些实施例中，元件340的侧表面被模塑化合物层350部分地或完全地覆盖。在一些实施例中，在模塑化合物层350的形成期间覆盖元件(或集成电路晶粒)340的侧表面。在一些实施例中，模塑化合物层350直接接触元件340的侧表面。在一些实施例中，一部分的模塑化合物层350横向地夹设于其中一个连接器320与元件340之间。
在一些实施例中，元件340的顶表面从模塑化合物层350暴露出来。在一些其他实施例中，模塑化合物层350覆盖元件340的顶表面。
在一些实施例中，模塑化合物层350包含高分子材料。模塑化合物层350大致不包含底部填充材料，例如变形胶或硅橡胶。在一些实施例中，模塑化合物层350和封装层240包含大致相同的材料。在一些其他实施例中，模塑化合物层350和封装层240包含不同的材料。
在一些实施例中，模塑化合物层350的黏度在约10Pa·s至约25Pa·s的范围内。在一些实施例中，模塑化合物层350的黏度在约16Pa·s至约25Pa·s的范围内。底部填充材料的黏度在约5Pa·s至约15Pa·s的范围内。
在一些实施例中，模塑化合物层350包含填料352分散于其中。填料352可包含绝缘纤维、绝缘粒子、其他合适的元件或前述的组合。在一些实施例中，填料352具有从约2μm至约30μm的范围内的直径。在一些实施例中，填料352的直径在约2μm至约15μm的范围内。在一些实施例中，其中一个在空间314中的填料352与另一个在连接器320之间的填料352具有大致相同的直径。
在一些实施例中，分散于模塑化合物层350的填料352的尺寸大于分散于底部填充材料的填料的尺寸。分散于底部填充材料的填料具有在约0.1μm至约5μm的范围内的直径。举例来说，分散于底部填充材料的填料的直径约1μm。在一些实施例中，填料352的直径不小于5μm。因此，模塑化合物层350相较于底部填充材料提供较强的结构强度。
在一些实施例中，模塑化合物层350和封装层240包含相同填料。在一些其他实施例中，模塑化合物层350和封装层240包含不同类型的填料。在一些实施例中，分散于模塑化合物层350的填料352的尺寸小于分散于封装层240的填料242的尺寸。填料352的尺寸，例如直径，可大致与填料242相同。在一些实施例中，空间341中的其中一个填料352与其中一个填料242可具有大致相同的直径。
在一些实施例中，可施加液态的模塑化合物材料在重布线结构130上方。液态的模塑化合物材料包含环氧树脂、硅石、其他合适的材料或前述的组合。在一些实施例中，接着实施热工艺以硬化模塑化合物材料并将模塑化合物材料转变为模塑化合物层350。
在一些实施例中，使用模封成型工艺沉积模塑化合物层350。模封成型工艺包含压缩成型工艺或其他适用的工艺。在一些实施例中，沉积的模塑化合物层350的顶表面360低于元件340的顶表面。在一些其他实施例中，沉积的模塑化合物层350的顶表面360与元件340的顶表面大致共平面。
在一些实施例中，在元件340的接合之后以及在模塑化合物层350的形成之前，不实施点胶工艺。在一些实施例中，在模塑化合物层350的形成之后以及在例如单离(singulation)工艺的后续工艺之前，不实施点胶工艺。
之后，依据本公开的一些实施例，实施单离工艺以将图1G所示的结构分离为多个封装结构。因此，将模塑化合物层350和封装层240切割。之后，将载板290移除。其中一个封装结构(即封装结构400)如图1H所示。
在一些实施例中，封装结构400更接合至基底。基底为印刷电路板、其他封装结构或其他合适的基底。在一些实施例中，图1G所示的结构不包含保护基板280。可在单离工艺之后，提供保护基板280于封装结构400上方。
虽然图1H显示保护基板280的尺寸相同于封装结构400的尺寸，但本公开的实施例不限于此。在一些其他实施例中，保护基板280的尺寸大于封装结构400的尺寸。举例来说，保护基板280的宽度大于封装结构400的宽度。
图2显示依据本公开的一些实施例的封装结构放大的剖面示意图。在一些实施例中，图2显示图1H所示的区域A的放大的剖面示意图。
如图2所示，在两个连接器320之间具有距离D1。在一些实施例中，距离D1在约300μm至约500μm的范围内。在元件340与相邻于元件340的其中一个连接器320之间具有距离D2。在一些实施例中，距离D2在约100μm至约200μm的范围内。在一些实施例中，距离D2小于距离D1。本公开的实施例不限于此。在一些其他实施例中，距离D2大致相同于或大于距离D1。
如图2所示，两个连接器330之间具有距离D3。在一些实施例中，距离D3在约20μm至约150μm的范围内。距离D3小于距离D1。在一些实施例中，距离D3大致与距离D2相同。本公开的实施例不限于此。在一些其他实施例中，距离D3小于或大于距离D2。
在一些实施例中，在模塑化合物层350的顶表面360与元件340的顶表面之间的距离D4在约0μm至约100μm的范围内。
在一些情况下，将底部填充材料应用至晶粒下方。可通过点胶的方法提供底部填充材料。举例来说，通过点胶设备注射液态底部填充材料。液态底部填充材料通过毛细作用(capillary action)流动至晶粒下方然后固化。为了使用点胶设备注射液态底部填充材料，晶粒四周需要有足够大的空间。此外，因为液态底部填充材料通过毛细作用流动，有一个大的空间未填充底部填充材料层。
依据本公开的一些实施例，在元件340与重布线结构130之间有模塑化合物层350。因为模塑化合物层350不包含底部填充材料，可省略一个或多个点胶工艺。因此，元件340与其中一个连接器320之间的空间不受限制。举例来说，可更加缩小距离D2。因此，依据本公开的一些实施例，可增加输入和输出(input/output，I/O)的连接点的数目。因此，可提高封装结构的设计弹性。
依据本公开的一些实施例，在相同的阶段期间通过模塑化合物层350封装元件340旁的连接器320和元件340下方的连接器330。实施模封成型工艺以沉积包含在每一封装结构中的模塑化合物层350。模塑化合物层350较底部填充材料便宜。因此，可显著地减少成本和制造时间。本公开的实施例提供较简易且较快速的封装工艺。
模塑化合物层350具有高空隙填充(gap-filling)能力。因此，模塑化合物层350的形成不受限于空隙面积及/或空隙高度之间的差异。在一些实施例中，距离D1大于距离D3。模塑化合物层350填充连接器320之间的空间和元件340与基底层120之间的空间。在一些实施例中，距离D2远大于距离D3。模塑化合物层350填充其中一个连接器320与元件340之间的空间和元件340与基底层120之间的空间。因此，连接器320和连接器330一起被包围在模塑化合物层350中。模塑化合物层350提供连接器320和连接器330足够的保护。因此，可改善封装结构的装置效能和可靠度。
可对本公开的实施例作许多变化及/或修改。举例来说，虽然图1A-图1H所示的实施例提供具有“扇出型(fan-out)”特征部件的封装结构，但本公开的实施例不限于此。本公开的一些其他实施例包含具有“扇入型(fan-in)”特征部件的封装结构。
可对本公开的实施例作许多变化及/或修改。举例来说，虽然图1A-图1H所示的实施例提供芯片封装(chip on package，CoP)结构或层叠封装(package on package，PoP)结构，但本公开的实施例不限于此。
图3显示依据本公开的一些实施例的封装结构的剖面示意图。如图3所示，封装结构500中的元件340并非堆叠于封装特征部件上方。元件340堆叠于集成电路晶粒200上方，集成电路晶粒200并未包封于封装层中。封装结构500的材料及/或形成方法相同或类似于前述实施例说明的封装结构400的材料及/或形成方法，不在此重复描述。
如图3所示，提供半导体基底210。在一些实施例中，半导体基底210为半导体晶片，例如硅晶片。各种装置元件可形成于半导体基底210中或半导体基底210上方。钝化层220和钝化层220中的导电垫230形成于半导体基底210上方。
在一些实施例中，重布线结构130形成于半导体基底210上方。重布线结构130电性连接至导电垫230和半导体基底210中或半导体基底210上方的装置元件。
之后，依据本公开的一些实施例，将钝化层170的多个部分移除以形成开口300和310。开口300和310暴露出部分的重布线结构130，例如部分的导电层160。
之后，连接器320填入开口300中。元件340通过连接器330接合至重布线结构130。模塑化合物层350封装连接器320、连接器330和元件340。接着，实施单离工艺以形成多个包含封装结构500的封装结构。
如图3所示，模塑化合物层350的顶表面360与元件340的顶表面大致共平面。因此，元件340的侧表面大致完全被模塑化合物层350包围。连接器320的上部320A从顶表面360突出。在一些其他实施例中，顶表面360低于元件340的顶表面。
本公开的实施例提供封装结构及其形成方法。此封装结构包含有着第一连接器的集成电路晶粒。此集成电路晶粒和第二连接器并排设置。在相同的阶段期间通过模塑化合物层一起围绕第一连接器和第二连接器。因此，可显著地减少成本和制造时间。集成电路晶粒与第二连接器之间的空间不受限。因此，本公开的实施例提供有着高设计弹性和可靠度的封装结构，并提供较简易且较快速的封装工艺。
依据本公开的一些实施例，提供封装结构的形成方法。此方法包含提供第一集成电路晶粒。此方法也包含形成重布线结构于第一集成电路晶粒上方。此方法更包含形成基底层于重布线结构上方，基底层具有多个第一开口和多个第二开口，第一开口宽于第二开口。此外，此方法包含形成多个第一凸块于重布线结构上方，第一凸块具有下部填入第一开口中。此方法也包含通过多个第二凸块将第二集成电路晶粒接合至重布线结构，第二凸块具有下部填入第二开口中。在第二集成电路晶粒与基底层之间有一空间。此方法更包含形成模塑化合物层于基底层上方，模塑化合物层填入此空间中并围绕第一凸块和第二凸块。
在一些其他实施例中，其中在实施模封成型工艺以形成模塑化合物层之前，此空间未被密封。
在一些其他实施例中，其中模封成型工艺为压缩成型工艺。
在一些其他实施例中，其中此方法不包含在接合第二集成电路晶粒之后以及在模塑化合物层的形成之前实施点胶(dispensing)工艺。
在一些其他实施例中，其中第二集成电路晶粒具有侧表面，且在模塑化合物层的形成期间模塑化合物层覆盖侧表面。
在一些其他实施例中，其中模塑化合物层具有第一填料在此空间中，且模塑化合物层具有第二填料在第一凸块之间，且其中第一填料与第二填料具有大致相同的直径。
在一些其他实施例中，上述方法更包含形成封装层围绕第一集成电路晶粒，其中在此空间中的模塑化合物层和封装层包含大致相同的材料。
依据本公开的一些实施例，提供封装结构的形成方法。此方法包含提供第一集成电路晶粒。此方法也包含实施第一模封成型工艺以形成围绕第一集成电路晶粒的封装层。此方法更包含形成重布线结构于第一集成电路晶粒和封装层上方。此外，此方法包含形成多个第一凸块于重布线结构上方。此方法也包含在第一凸块形成之后，通过多个第二凸块将第二集成电路晶粒接合至重布线结构。此方法更包含实施第二模封成型工艺以形成模塑化合物层于这些第一凸块之间和这些第二凸块之间。在第二模封成型工艺期间，模塑化合物层覆盖第一凸块和第二凸块的表面。
在一些其他实施例中，上述方法更包含在第二模封成型工艺之前，实施回焊(reflow)工艺于第一凸块和第二凸块上方，其中此方法不包含在回焊工艺之后以及在第二模封成型工艺之前实施点胶工艺。
在一些其他实施例中，其中第二集成电路晶粒具有侧表面，且在实施第二模封成型工艺之前，暴露出此侧表面。
在一些其他实施例中，其中模塑化合物层具有第一填料分散于其中，且封装层具有第二填料分散于其中，且其中第一填料与第二填料具有大致相同的直径。
在一些其他实施例中，其中模塑化合物层具有大致平坦的顶表面，且第一凸块具有上部从此顶表面突出。
在一些其他实施例中，其中第一凸块之间具有第一距离，且第二集成电路晶粒与其中一个第一凸块之间具有第二距离，且其中第一距离大于第二距离。
在一些其他实施例中，其中第二集成电路晶粒与其中一个第一凸块之间具有第二距离，且第二凸块之间具有第三距离，且其中第二距离大致与第三距离相同。
依据本公开的一些实施例，提供封装结构。此封装结构包含第一集成电路晶粒。此封装结构也包含重布线结构位于第一集成电路晶粒上方，封装层围绕第一集成电路晶粒。此封装结构更包含基底层位于重布线结构上方，基底层具有多个第一开口和多个第二开口。此外，此封装结构包含多个第一凸块填入这些第一开口中。此封装结构也包含多个第二凸块填入这些第二开口中，第一凸块具有大于第二凸块的高度。此封装结构更包含第二集成电路晶粒位于第二凸块上方，在第二集成电路晶粒与基底层之间有一空间。此封装结构包含模塑化合物层位于基底层上方，模塑化合物层填入此空间中并围绕第一凸块和第二凸块。
在一些其他实施例中，其中模塑化合物层具有第一填料在此空间中，且模塑化合物层具有第二填料在第一凸块之间，且其中第一填料与第二填料具有大致相同的直径。
在一些其他实施例中，此封装结构更包含形成封装层围绕第一集成电路晶粒，其中模塑化合物层具有第一填料在此空间中，且封装层具有与第一填料大致相同的直径的第二填料。
在一些其他实施例中，其中第一凸块之间具有第一距离，且第二集成电路晶粒与其中一个第一凸块之间具有第二距离，且其中第一距离大于第二距离。
在一些其他实施例中，其中第二集成电路晶粒与其中一个第一凸块之间具有第二距离，且第二凸块之间具有第三距离，且其中第二距离大致与第三距离相同。
在一些其他实施例中，其中模塑化合物层具有大致平坦的顶表面，且第一凸块具有上部从此顶表面突出。
前述内文概述了许多实施例的特征，使本领域技术人员可以从各个方面更佳地了解本公开。本领域技术人员应可理解，且可轻易地以本公开为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本领域技术人员也应了解这些相等的结构并未背离本公开的发明精神与范围。在不背离本公开的发明精神与范围的前提下，可对本公开进行各种改变、置换或修改。

Claims (1)

1.一种封装结构的形成方法，包括:
提供一第一集成电路晶粒；
形成一重布线结构于该第一集成电路晶粒上方；
形成一基底层于该重布线结构上方，其中该基底层具有多个第一开口和多个第二开口，且该些第一开口宽于该些第二开口；
形成多个第一凸块于该重布线结构上方，其中该些第一凸块具有一下部填入该些第一开口中；
通过多个第二凸块将一第二集成电路晶粒接合至该重布线结构，其中该些第二凸块具有一下部填入该些第二开口中，且在该第二集成电路晶粒与该基底层之间有一空间；以及
形成一模塑化合物层于该基底层上方，其中该模塑化合物层填入该空间中并围绕该些第一凸块和该些第二凸块。
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