TW201807761A - 封裝結構的形成方法 - Google Patents

封裝結構的形成方法 Download PDF

Info

Publication number
TW201807761A
TW201807761A TW105138222A TW105138222A TW201807761A TW 201807761 A TW201807761 A TW 201807761A TW 105138222 A TW105138222 A TW 105138222A TW 105138222 A TW105138222 A TW 105138222A TW 201807761 A TW201807761 A TW 201807761A
Authority
TW
Taiwan
Prior art keywords
layer
molding compound
integrated circuit
circuit die
bumps
Prior art date
Application number
TW105138222A
Other languages
English (en)
Inventor
鄭余任
黃育智
陳志華
陳玉芬
蔡豪益
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201807761A publication Critical patent/TW201807761A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露之實施例提供封裝結構及其形成方法，此方法包含提供第一積體電路晶粒並形成重佈線結構於第一積體電路晶粒上方，形成基底層於重佈線結構上方，基底層具有複數個第一開口和複數個第二開口，且第一開口寬於第二開口，形成複數個第一凸塊於重佈線結構上方，第一凸塊具有下部填入第一開口中。此外，此方法包含透過具有下部填入第二開口中的複數個第二凸塊將第二積體電路晶粒接合至重佈線結構，在第二積體電路晶粒與基底層之間有一空間。此方法也包含形成模塑化合物層於基底層上方，模塑化合物層填入此空間中並圍繞第一凸塊和第二凸塊。

Description

封裝結構的形成方法
本發明實施例係有關於半導體技術，且特別是有關於半導體封裝結構及其形成方法。
半導體裝置被使用於各種電子應用中，例如個人電腦、手機、數位相機和其他電子設備。半導體裝置的製造是透過依序地沉積絕緣層或介電層、導電層和半導體層於半導體基底上方，並透過微影製程和蝕刻製程將各種材料層圖案化，以形成半導體基底上的電路組件和元件。許多積體電路一般製造於單一的半導體晶圓上，且晶圓上個別的晶粒係沿著積體電路之間的切割線切割而單離(singulated)為。一般將個別的晶粒分別封裝為例如多晶片模組或其他類型的封裝。
半導體產業透過持續降低最小特徵部件的尺寸，其可使更多的組件集成於既定面積中，以持續改善各種電子組件(例如電晶體、二極體、電阻器、電容器等等)的集成密度。在一些應用中，這些較小的電子組件也使用較少面積或較小高度的較小封裝。
新的封裝技術，例如層疊封裝(package on package，PoP)已開始發展，其中有著裝置晶粒的頂部封裝結構接合至有著另一裝置晶粒的底部封裝結構。透過採用新的封 裝技術，將各種有著不同或類似功能的封裝結構集成在一起。半導體裝置的這些相對新類型之封裝技術面臨製造上的挑戰，且這些封裝技術並非在全方位皆完全令人滿意。
在一些實施例中，提供封裝結構的形成方法，其包含提供第一積體電路晶粒，形成重佈線結構於第一積體電路晶粒上方，形成基底層於重佈線結構上方，其中基底層具有複數個第一開口和複數個第二開口，且第一開口寬於第二開口。此方法還包含形成複數個第一凸塊於重佈線結構上方，其中第一凸塊具有一下部填入第一開口中。此方法更包含透過複數個第二凸塊將第二積體電路晶粒接合至重佈線結構，其中第二凸塊具有下部填入第二開口中，且在第二積體電路晶粒與基底層之間有一空間，以及形成模塑化合物層於基底層上方，其中模塑化合物層填入此空間中並圍繞第一凸塊和第二凸塊。
在一些其他實施例中，提供封裝結構的形成方法，其包含提供第一積體電路晶粒，實施第一模封成型製程以形成圍繞第一積體電路晶粒的封裝層，形成重佈線結構於第一積體電路晶粒和封裝層上方，形成複數個第一凸塊於重佈線結構上方。此方法還包含在第一凸塊形成之後，透過複數個第二凸塊將第二積體電路晶粒接合至重佈線結構，以及實施第二模封成型製程以形成模塑化合物層於這些第一凸塊之間和這些第二凸塊之間，其中在第二模封成型製程期間，模塑化合物層覆蓋第一凸塊和第二凸塊的表面。
在另外一些實施例中，提供封裝結構，其包含第 一積體電路晶粒，重佈線結構位於第一積體電路晶粒上方，基底層位於重佈線結構上方，其中基底層具有複數個第一開口和複數個第二開口。此封裝結構包含複數個第一凸塊填入這些第一開口中，複數個第二凸塊填入這些第二開口中，其中第一凸塊具有大於第二凸塊的高度。此封裝結構更包含第二積體電路晶粒位於第二凸塊上方，其中在第二積體電路晶粒與基底層之間有一空間，以及模塑化合物層位於基底層上方，其中模塑化合物層填入此空間中並圍繞第一凸塊和第二凸塊。
100‧‧‧承載基底
110‧‧‧黏著層
120‧‧‧基底層
130‧‧‧重佈線結構
140、160、260‧‧‧導電層
150、170、220、250‧‧‧鈍化層
180‧‧‧導電特徵部件
190‧‧‧黏著膜
200‧‧‧積體電路晶粒
210‧‧‧半導體基底
230‧‧‧導電墊
240‧‧‧封裝層
242、352‧‧‧填料
270‧‧‧保護層
280‧‧‧保護基板
290‧‧‧載板
300、310‧‧‧開口
320、330‧‧‧連接器
320A、330A‧‧‧上部
320B、330B‧‧‧下部
340‧‧‧元件(積體電路晶粒)
341、342‧‧‧空間
345‧‧‧回焊製程
350‧‧‧模塑化合物層
360‧‧‧頂表面
370‧‧‧底表面
400、500‧‧‧封裝結構
A‧‧‧區域
D1、D2、D3、D4‧‧‧距離
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示中的各種特徵部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種特徵部件的尺寸，以做清楚的說明。
第1A-1H圖顯示依據本揭露的一些實施例之形成封裝結構的製程的各種階段的剖面示意圖。
第2圖顯示依據本揭露的一些實施例之封裝結構放大的剖面示意圖。
第3圖顯示依據本揭露的一些實施例之封裝結構的剖面示意圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本揭露的不同特徵部件。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化本揭露的說明。當然，這些特定的範例並非用以 限定本揭露。例如，元件的尺寸並不侷限於本揭露的範圍或值，而可取決於裝置的製程條件及/或所需性質。再者，若是本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。例如，若翻轉圖式中的裝置，描述為位於其他元件或特徵部件“下方”或“在...之下”的元件，將定位為位於其他元件或特徵部件“上方”。因此，範例的用語“下方”可涵蓋上方及下方的方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
本揭露描述一些實施例的封裝結構及其形成方法。第1A-1H圖顯示依據本揭露的一些實施例之形成封裝結構的製程的各種階段的剖面示意圖。雖然以特定的順序討論一些 實施例的操作實施，但是可依其他合乎邏輯的順序實施這些操作，可在第1A-1H圖描述之階段之前、期間及/或之後提供額外的操作，且所描述的一些操作在其他實施例中可被取代或刪除。封裝結構可加入額外的特徵部件，且以下描述的一些特徵部件在其他實施例中可被取代或刪除。
如第1A圖所示，依據本揭露的一些實施例，提供承載基底100。在一些實施例中，承載基底100用作暫時基底。暫時基底在後續的製程步驟期間提供機械性和結構性的支撐，其將在後續更加詳細描述。承載基底100由半導體材料、陶瓷材料、高分子材料、金屬材料、其他合適的材料或前述之組合製成。在一些實施例中，承載基底100為玻璃基底。在一些其他實施例中，承載基底100為半導體基底，例如矽晶圓。
之後，依據本揭露的一些實施例，將黏著層110設置於承載基底100上方。黏著層110可由黏膠製成或可為例如金屬薄片(foil)的貼合材料。在一些實施例中，黏著層110為感光性的，且容易藉由光照射脫離承載基底100。舉例來說，將紫外(ultra-violet，UV)光或雷射光照射至承載基底100上，以分離黏著層110。在一些實施例中，黏著層110為光熱轉換(light-to-heat conversion，LTHC)塗層。在一些其他實施例中，黏著層110為感熱性的，且當暴露於熱時容易脫離承載基底100。
之後，依據本揭露的一些實施例，將基底層(base layer)120沉積或貼合至黏著層110上方。基底層120提供接合積體電路晶粒之結構性的支撐，其將在後續更加詳細描述，且幫 助減少晶粒偏移的問題。在一些實施例中，基底層120為高分子層或含高分子層。基底層120可為聚對二唑苯(poly-p-phenylenebenzobisthiazole，PBO)層、聚亞醯胺(polyimide，PI)層、阻焊(solder resist，SR)層、味之素增層膜(Ajinomoto buildup film，ABF)、晶粒附接膜(die attach film，DAF)、其他合適層或前述之組合。
如第1A圖所示，依據本揭露的一些實施例，重佈線結構130形成於基底層120上方。重佈線結構130包含一或多個導電層以及一或多個鈍化層。舉例來說，重佈線結構130包含導電層140和160以及鈍化層150和170。
導電層140形成於基底層120上方。鈍化層150沉積於基底層120上方，且部分覆蓋導電層140。部分的導電層140從鈍化層150中的開口暴露出來。導電層160形成於鈍化層150上方。導電層160透過鈍化層150的開口電性連接導電層140。鈍化層170沉積於鈍化層150上方，且覆蓋導電層160。
在一些實施例中，重佈線結構130中的導電層140和160由金屬材料製成，此金屬材料包含銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)、鉭合金、其他合適的材料或前述之組合。在一些實施例中，重佈線結構130中的導電層140和160透過電鍍製程、無電電鍍製程、濺鍍製程、化學氣相沉積(chemical vapor deposition，CVD)製程或其他適用的製程形成。
在一些實施例中，重佈線結構130中的鈍化層150和170由聚苯并噁唑(polybenzoxazole，PBO)、苯環丁烯 (benzocyclobutene，BCB)、矽氧樹脂、丙烯酸酯、矽氧烷、其他合適的材料或前述之組合製成。在一些其他實施例中，重佈線結構130中的鈍化層150和170由非有機材料製成，這些非有機材料包含氧化矽、未摻雜矽酸鹽玻璃、氮氧化矽、阻焊劑(SR)、氮化矽、碳化矽、六甲基二矽氮烷(hexamethyldisilazane，HMDS)、其他合適的材料或前述之組合。可使用多個沉積製程、塗佈製程及/或蝕刻製程形成重佈線結構130。
之後，依據本揭露的一些實施例，多個導電特徵部件180形成於重佈線結構130上方。在一些實施例中，導電特徵部件180為導電柱或其他合適的結構。導電特徵部件180可被稱為貫穿中介層導通孔(through interposer vias，TIVs)。導電特徵部件180物理性和電性連接重佈線結構130中的其中一個導電層。舉例來說，鈍化層170具有開口部分地暴露出導電層160。導電特徵部件180透過鈍化層170中的開口電性連接導電層160。
在一些實施例中，導電特徵部件180包含銅(Cu)、鋁(Al)、鎳(Ni)、鉑(Pt)、無鉛焊料(例如SnAg、SnCu、SnAgCu)、其他合適的導電材料或前述之組合。在一些實施例中，導電特徵部件180透過使用電鍍製程、物理氣相沉積(physical vapor deposition，PVD)製程、化學氣相沉積(CVD)製程、電化學沉積(electrochemical deposition，ECD)製程、分子束磊晶(molecular beam epitaxy，MBE)製程、原子層沉積(atomic layer deposition，ALD)製程或其他適用的製程形成。
如第1B圖所示，依據本揭露的一些實施例，將積 體電路晶粒200設置於重佈線結構130上。在一些實施例中，積體電路晶粒200的前側(主動面)遠離重佈線結構130，積體電路晶粒200的背側(非主動面)面向重佈線結構130。然而，本揭露的實施例不限於此。在一些其他的實施例中，積體電路晶粒200的前側面向重佈線結構130。
積體電路晶粒200可為包含電晶體、二極體或其他合適之積體電路元件的裝置晶粒。裝置晶粒也可包含電容器、電感器、電阻器、其他積體電路元件或前述之組合。在一些實施例中，積體電路晶粒200為感測晶粒、邏輯晶粒、中央處理單元(central processing unit，CPU)晶粒、記憶體晶粒或其他合適的晶粒。
在一些實施例中，積體電路晶粒200包含半導體基底210、鈍化層220和導電墊230。積體電路晶粒200也包含在導電墊230上的連接器，以及圍繞連接器的保護層。各種裝置元件可形成於半導體基底210中或半導體基底210上方，這些裝置元件包含主動元件及/或被動元件。在一些實施例中，裝置元件包含指紋辨識裝置。在一些其他實施例中，裝置元件包含影像感測裝置、邏輯裝置、記憶體裝置、其他適用類型的裝置或前述之組合。
雖然第1B圖顯示一個積體電路晶粒200在重佈線結構130上，但本揭露的實施例不限於此。在一些其他的實施例中，多個積體電路晶粒200在重佈線結構130上。
在一些實施例中，使用黏著膜190接合或連接積體電路晶粒200和重佈線結構130。黏著膜190包含晶粒附接膜 (DAF)、其他合適層或前述之組合。
之後，依據本揭露的一些實施例，將封裝層240沉積於重佈線結構130上方。因此，可透過封裝層240封裝導電特徵部件180和積體電路晶粒200。
在一些實施例中，封裝層240包含高分子材料。在一些實施例中，封裝層240包含模塑化合物(molding compound)。在一些實施例中，封裝層240包含填料242分散於其中。填料242可包含絕緣纖維、絕緣粒子、其他合適的元件或前述之組合。在一些實施例中，填料242具有從約2μm至約30μm的範圍內的直徑。在一些實施例中，填料242的直徑在約15μm至約30μm的範圍內。
在一些實施例中，可施加液態的模塑化合物材料在重佈線結構130上方。液態的模塑化合物材料包含環氧樹脂、矽石(silica)、其他合適的材料或前述之組合。在一些實施例中，接著實施熱製程以硬化模塑化合物材料並將模塑化合物材料轉變為封裝層240。
在一些實施例中，使用模封成型製程(molding process)沉積封裝層240。模封成型製程包含壓縮成型製程或其他適用的製程。在一些實施例中，沉積的封裝層240的頂表面與導電特徵部件180和積體電路晶粒200的頂表面大致共平面。
在一些其他實施例中，沉積的封裝層240覆蓋導電特徵部件180和積體電路晶粒200的頂表面。之後，將沉積的封裝層240薄化。因此，暴露出導電特徵部件180和積體電路晶粒200。可使用平坦化製程將沉積的封裝層240薄化。平坦化製程 包含研磨製程、化學機械研磨(chemical mechanical polishing，CMP)製程、蝕刻製程、其他適用的製程或前述之組合。
如第1C圖所示，依據本揭露的一些實施例，包含鈍化層250和導電層260的重佈線結構形成於封裝層240上方。在封裝層240上方的重佈線結構可包含多個導電層和鈍化層。使用多個沉積製程、塗佈製程及/或蝕刻製程以形成包含鈍化層250和導電層260的重佈線結構。
鈍化層250沉積於封裝層240上方。鈍化層250由介電材料製成並為後續之接合製程期間產生的接合應力提供應力緩和。在一些實施例中，鈍化層250由聚苯并噁唑(PBO)、苯環丁烯(BCB)、矽氧樹脂、丙烯酸酯、矽氧烷、其他合適的材料或前述之組合製成。在一些其他實施例中，鈍化層250由非有機材料製成，這些非有機材料包含氧化矽、未摻雜矽酸鹽玻璃、氮氧化矽、阻焊劑(SR)、氮化矽、碳化矽、六甲基二矽氮烷(HMDS)、其他合適的材料或前述之組合。
導電層260埋置於鈍化層250中。導電層260電性連接至導電特徵部件180和積體電路晶粒200。在一些實施例中，導電層260由金屬材料製成，此金屬材料包含銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)、鉭合金、其他合適的材料或前述之組合。在一些實施例中，導電層260透過電鍍製程、無電電鍍製程、濺鍍製程、化學氣相沉積(CVD)製程或其他適用的製程形成。
之後，依據本揭露的一些實施例，將保護層270沉積於鈍化層250上方。保護層270為彩色膜、其他合適層或前述 之組合。彩色膜可用以避免封裝結構中例如導電層260的一些層暴露於使用者。在一些其他實施例中，不形成保護層270。
之後，依據本揭露的一些實施例，提供保護基板280於保護層250上方。在一些實施例中，保護基板280用作指紋辨識裝置的面板。保護基板280由非有機材料或其他合適的材料製成。在一些實施例中，保護基板280為玻璃基底、藍寶石基底或其他合適的基底。在一些其他實施例中，不形成保護基板280。
如第1D圖所示，依據本揭露的一些實施例，將第1C圖顯示的結構翻轉並附著至載板290。載板290包含感光性或感熱性的膠帶，且容易從保護基板280或保護層270脫離。
如上所述，在一些實施例中，不形成保護基板280。因此，保護層270直接接觸載板290。然而，本揭露的實施例不限於此。在一些實施例中，不形成保護層270和保護基板280。因此，鈍化層250直接接觸載板290。
之後，將承載基底100移除。在一些實施例中，將承載基底100和黏著層110都移除。可提供合適的光以移除黏著層110和承載基底100。
之後，依據本揭露的一些實施例，將基底層120的多個部份移除以形成開口300和310。開口300和310暴露出部分的重佈線結構130，例如部分的導電層140。開口300位於導電特徵部件180上方，開口310位於積體電路晶粒200上方。開口300的尺寸大於開口310的尺寸。舉例來說，開口300寬於開口310。
兩個開口300之間的空間大於兩個開口310之間的空間。在一些實施例中，其中一個開口300與其中一個開口310之間的空間大致相同於兩個開口300之間的空間。在一些其他實施例中，其中一個開口300與其中一個開口310之間的空間不同於兩個開口300之間的空間。
在一些實施例中，實施雷射鑽孔(laser drilling)製程以形成開口300和310。也可使用其他適用的製程，例如蝕刻製程，以形成開口300和310。
如第1E圖所示，依據本揭露的一些實施例，將多個連接器320沉積於重佈線結構130上方。連接器320填入開口300中並從基底層120突出。連接器320電性連接至重佈線結構130中的導電層140。連接器320包含焊料凸塊、金屬柱、其他合適的連接器或前述之組合。
在一些實施例中，導電層140為凸塊下金屬(under bump metallurgy，UBM)結構。導電層140直接接觸連接器320，但本揭露的實施例不限於此。在一些其他實施例中，一個凸塊下金屬(UBM)結構位於其中一個連接器320與導電層140之間。凸塊下金屬(UBM)結構可包含接合墊和一個或多個凸塊下金屬(UBM)層。
如第1F圖所示，依據本揭露的一些實施例，將元件340堆疊於重佈線結構130上方。在一些實施例中，在元件340與基底層120之間有空間341。元件340和積體電路晶粒200在基底層120的相對兩側上。元件340和連接器320並排設置。在一些實施例中，連接器320在元件340的相對兩側上。在一些其他 實施例中，連接器320不連續地圍繞元件340。
在一些實施例中，元件340為積體電路晶粒。舉例來說，此積體電路晶粒為高電壓晶粒(high-voltage die)或其他合適的晶粒。然而，本揭露的實施例不限於此。在一些其他實施例中，元件340包含封裝結構，此封裝結構含有一個或多個積體電路晶粒。可依據需求改變元件340。
在一些實施例中，元件340的前側(主動面)面向積體電路晶粒200的背側(非主動面)。然而，本揭露的實施例不限於此。在一些其他的實施例中，元件340的前側(主動面)面向積體電路晶粒200的前側(主動面)。
雖然第1F圖顯示一個元件340在重佈線結構130上，但本揭露的實施例不限於此。在一些其他的實施例中，多個元件340在重佈線結構130上。
在一些實施例中，使用一個或多個連接器330以達成元件340與重佈線結構130之間的接合，如第1F圖所示。連接器330填入開口310中並從基底層120突出。連接器330透過開口310電性連接至重佈線結構130中的導電層140。連接器330包含焊料凸塊、金屬柱、其他合適的連接器或前述之組合。連接器330的尺寸小於連接器320。在一些實施例中，連接器320具有的高度大於連接器330的高度。
如第1F圖所示，依據本揭露的一些實施例，實施回焊(reflow)製程345於連接器320、元件340和連接器330上方。在一些實施例中，不實施用以沉積底部填充材料的點膠(dispensing)製程於第1F圖所示的結構上方。在一些實施例中， 在元件340與基底層120之間沒有底部填充材料。在一些實施例中，連接器330不被底部填充材料包裹住。
如第1G圖所示，依據本揭露的一些實施例，將模塑化合物層350沉積於重佈線結構130上方。模塑化合物層350連續地圍繞連接器320並延伸至元件340與重佈線結構130之間。因此，可透過模塑化合物層350封裝連接器320和連接器330。
模塑化合物層350從連接器320的側表面連續地延伸至連接器330的側表面。在一些實施例中，模塑化合物層350直接接觸連接器330的側表面和連接器320的側表面。在一些實施例中，一部分的模塑化合物層350橫向地夾設於其中一個連接器320與其中一個連接器330之間。
在一些實施例中，在形成模塑化合物層350之前，連接器320和330的側表面從基底層120部分地暴露出來。在一些實施例中，在模塑化合物層350的形成期間覆蓋連接器320暴露的側表面。舉例來說，模塑化合物層350和基底層120大致完全覆蓋連接器320的側表面。在一些實施例中，在模塑化合物層350的形成期間覆蓋連接器330暴露的側表面。
模塑化合物層350具有頂表面360和底表面370，頂表面360遠離積體電路晶粒200。在一些實施例中，頂表面360大致為平坦的。底表面370面向積體電路晶粒200。在一些實施例中，連接器320的上部320A從頂表面360突出。在一些實施例中，連接器320的下部320B從底表面370突出。在一些實施例中，連接器330的上部330A埋置於模塑化合物層350中。在一些 實施例中，連接器330的下部330B從底表面370突出。
在一些實施例中，模塑化合物層350連續地圍繞連接器320、連接器330和元件340。模塑化合物層350填入元件340與基底層120之間的空間341中並延伸於連接器320之間。在一些實施例中，在形成模塑化合物層350之前，空間341未被密封。模塑化合物層350也填入其中一個連接器320與元件340之間的空間342中。因此，連接器320、連接器330和元件340埋置於相同的材料層(即模塑化合物層350)中。
模塑化合物層350從連接器320的側表面連續地延伸至元件(或積體電路晶粒)340的側表面。在一些實施例中，元件340的側表面被模塑化合物層350部份地或完全地覆蓋。在一些實施例中，在模塑化合物層350的形成期間覆蓋元件(或積體電路晶粒)340的側表面。在一些實施例中，模塑化合物層350直接接觸元件340的側表面。在一些實施例中，一部分的模塑化合物層350橫向地夾設於其中一個連接器320與元件340之間。
在一些實施例中，元件340的頂表面從模塑化合物層350暴露出來。在一些其他實施例中，模塑化合物層350覆蓋元件340的頂表面。
在一些實施例中，模塑化合物層350包含高分子材料。模塑化合物層350大致不包含底部填充材料，例如變形膠或矽橡膠。在一些實施例中，模塑化合物層350和封裝層240包含大致相同的材料。在一些其他實施例中，模塑化合物層350和封裝層240包含不同的材料。
在一些實施例中，模塑化合物層350的黏度在約10Pa．s至約25Pa．s的範圍內。在一些實施例中，模塑化合物層350的黏度在約16Pa．s至約25Pa．s的範圍內。底部填充材料的黏度在約5Pa．s至約15Pa．s的範圍內。
在一些實施例中，模塑化合物層350包含填料352分散於其中。填料352可包含絕緣纖維、絕緣粒子、其他合適的元件或前述之組合。在一些實施例中，填料352具有從約2μm至約30μm的範圍內的直徑。在一些實施例中，填料352的直徑在約2μm至約15μm的範圍內。在一些實施例中，其中一個在空間314中的填料352與另一個在連接器320之間的填料352具有大致相同的直徑。
在一些實施例中，分散於模塑化合物層350之填料352的尺寸大於分散於底部填充材料之填料的尺寸。分散於底部填充材料的填料具有在約0.1μm至約5μm的範圍內的直徑。舉例來說，分散於底部填充材料之填料的直徑約1μm。在一些實施例中，填料352的直徑不小於5μm。因此，模塑化合物層350相較於底部填充材料提供較強的結構強度。
在一些實施例中，模塑化合物層350和封裝層240包含相同填料。在一些其他實施例中，模塑化合物層350和封裝層240包含不同類型的填料。在一些實施例中，分散於模塑化合物層350之填料352的尺寸小於分散於封裝層240之填料242的尺寸。填料352的尺寸，例如直徑，可大致與填料242相同。在一些實施例中，空間341中的其中一個填料352與其中一個填料242可具有大致相同的直徑。
在一些實施例中，可施加液態的模塑化合物材料在重佈線結構130上方。液態的模塑化合物材料包含環氧樹脂、矽石、其他合適的材料或前述之組合。在一些實施例中，接著實施熱製程以硬化模塑化合物材料並將模塑化合物材料轉變為模塑化合物層350。
在一些實施例中，使用模封成型製程沉積模塑化合物層350。模封成型製程包含壓縮成型製程或其他適用的製程。在一些實施例中，沉積的模塑化合物層350的頂表面360低於元件340的頂表面。在一些其他實施例中，沉積的模塑化合物層350的頂表面360與元件340的頂表面大致共平面。
在一些實施例中，在元件340的接合之後以及在模塑化合物層350的形成之前，不實施點膠製程。在一些實施例中，在模塑化合物層350的形成之後以及在例如單離(singulation)製程的後續製程之前，不實施點膠製程。
之後，依據本揭露的一些實施例，實施單離製程以將第1G圖所示的結構分離為多個封裝結構。因此，將模塑化合物層350和封裝層240切割。之後，將載板290移除。其中一個封裝結構(即封裝結構400)如第1H圖所示。
在一些實施例中，封裝結構400更接合至基底。基底為印刷電路板、其他封裝結構或其他合適的基底。在一些實施例中，第1G圖所示的結構不包含保護基板280。可在單離製程之後，提供保護基板280於封裝結構400上方。
雖然第1H顯示保護基板280的尺寸相同於封裝結構400的尺寸，但本揭露的實施例不限於此。在一些其他實施 例中，保護基板280的尺寸大於封裝結構400的尺寸。舉例來說，保護基板280的寬度大於封裝結構400的寬度。
第2圖顯示依據本揭露的一些實施例之封裝結構放大的剖面示意圖。在一些實施例中，第2圖顯示第1H圖所示的區域A之放大的剖面示意圖。
如第2圖所示，在兩個連接器320之間具有距離D1。在一些實施例中，距離D1在約300μm至約500μm的範圍內。在元件340與相鄰於元件340的其中一個連接器320之間具有距離D2。在一些實施例中，距離D2在約100μm至約200μm的範圍內。在一些實施例中，距離D2小於距離D1。本揭露的實施例不限於此。在一些其他實施例中，距離D2大致相同於或大於距離D1。
如第2圖所示，兩個連接器330之間具有距離D3。在一些實施例中，距離D3在約20μm至約150μm的範圍內。距離D3小於距離D1。在一些實施例中，距離D3大致與距離D2相同。本揭露的實施例不限於此。在一些其他實施例中，距離D3小於或大於距離D2。
在一些實施例中，在模塑化合物層350的頂表面360與元件340的頂表面之間的距離D4在約0μm至約100μm的範圍內。
在一些情況下，將底部填充材料應用至晶粒下方。可透過點膠的方法提供底部填充材料。舉例來說，透過點膠設備注射液態底部填充材料。液態底部填充材料透過毛細作用(capillary action)流動至晶粒下方然後固化。為了使用點膠 設備注射液態底部填充材料，晶粒四周需要有足夠大的空間。此外，因為液態底部填充材料透過毛細作用流動，有一個大的空間未填充底部填充材料層。
依據本揭露的一些實施例，在元件340與重佈線結構130之間有模塑化合物層350。因為模塑化合物層350不包含底部填充材料，可省略一個或多個點膠製程。因此，元件340與其中一個連接器320之間的空間不受限制。舉例來說，可更加縮小距離D2。因此，依據本揭露的一些實施例，可增加輸入和輸出(input/output，I/O)的連接點的數目。因此，可提高封裝結構的設計彈性。
依據本揭露的一些實施例，在相同的階段期間透過模塑化合物層350封裝元件340旁的連接器320和元件340下方的連接器330。實施模封成型製程以沉積包含在每一封裝結構中的模塑化合物層350。模塑化合物層350較底部填充材料便宜。因此，可顯著地減少成本和製造時間。本揭露的實施例提供較簡易且較快速的封裝製程。
模塑化合物層350具有高空隙填充(gap-filling)能力。因此，模塑化合物層350的形成不受限於空隙面積及/或空隙高度之間的差異。在一些實施例中，距離D1大於距離D3。模塑化合物層350填充連接器320之間的空間和元件340與基底層120之間的空間。在一些實施例中，距離D2遠大於距離D3。模塑化合物層350填充其中一個連接器320與元件340之間的空間和元件340與基底層120之間的空間。因此，連接器320和連接器330一起被包圍在模塑化合物層350中。模塑化合物層350提 供連接器320和連接器330足夠的保護。因此，可改善封裝結構的裝置效能和可靠度。
可對本揭露的實施例作許多變化及/或修改。舉例來說，雖然第1A-1H圖所示的實施例提供具有“扇出型(fan-out)”特徵部件的封裝結構，但本揭露的實施例不限於此。本揭露的一些其他實施例包含具有“扇入型(fan-in)”特徵部件的封裝結構。
可對本揭露的實施例作許多變化及/或修改。舉例來說，雖然第1A-1H圖所示的實施例提供晶片封裝(chip on package，CoP)結構或層疊封裝(package on package，PoP)結構，但本揭露的實施例不限於此。
第3圖顯示依據本揭露的一些實施例之封裝結構的剖面示意圖。如第3圖所示，封裝結構500中的元件340並非堆疊於封裝特徵部件上方。元件340堆疊於積體電路晶粒200上方，積體電路晶粒200並未包封於封裝層中。封裝結構500的材料及/或形成方法相同或類似於前述實施例說明的封裝結構400的材料及/或形成方法，不在此重複描述。
如第3圖所示，提供半導體基底210。在一些實施例中，半導體基底210為半導體晶圓，例如矽晶圓。各種裝置元件可形成於半導體基底210中或半導體基底210上方。鈍化層220和鈍化層220中的導電墊230形成於半導體基底210上方。
在一些實施例中，重佈線結構130形成於半導體基底210上方。重佈線結構130電性連接至導電墊230和半導體基底210中或半導體基底210上方的裝置元件。
之後，依據本揭露的一些實施例，將鈍化層170的多個部分移除以形成開口300和310。開口300和310暴露出部分的重佈線結構130，例如部分的導電層160。
之後，連接器320填入開口300中。元件340透過連接器330接合至重佈線結構130。模塑化合物層350封裝連接器320、連接器330和元件340。接著，實施單離製程以形成多個包含封裝結構500的封裝結構。
如第3圖所示，模塑化合物層350的頂表面360與元件340的頂表面大致共平面。因此，元件340的側表面大致完全被模塑化合物層350包圍。連接器320的上部320A從頂表面360突出。在一些其他實施例中，頂表面360低於元件340的頂表面。
本揭露的實施例提供封裝結構及其形成方法。此封裝結構包含有著第一連接器的積體電路晶粒。此積體電路晶粒和第二連接器並排設置。在相同的階段期間透過模塑化合物層一起圍繞第一連接器和第二連接器。因此，可顯著地減少成本和製造時間。積體電路晶粒與第二連接器之間的空間不受限。因此，本揭露的實施例提供有著高設計彈性和可靠度的封裝結構，並提供較簡易且較快速的封裝製程。
依據本揭露的一些實施例，提供封裝結構的形成方法。此方法包含提供第一積體電路晶粒。此方法也包含形成重佈線結構於第一積體電路晶粒上方。此方法更包含形成基底層於重佈線結構上方，基底層具有複數個第一開口和複數個第二開口，第一開口寬於第二開口。此外，此方法包含形成複數個第一凸塊於重佈線結構上方，第一凸塊具有下部填入第一開 口中。此方法也包含透過複數個第二凸塊將第二積體電路晶粒接合至重佈線結構，第二凸塊具有下部填入第二開口中。在第二積體電路晶粒與基底層之間有一空間。此方法更包含形成模塑化合物層於基底層上方，模塑化合物層填入此空間中並圍繞第一凸塊和第二凸塊。
在一些其他實施例中，其中在實施模封成型製程以形成模塑化合物層之前，此空間未被密封。
在一些其他實施例中，其中模封成型製程為壓縮成型製程。
在一些其他實施例中，其中此方法不包含在接合第二積體電路晶粒之後以及在模塑化合物層的形成之前實施點膠(dispensing)製程。
在一些其他實施例中，其中第二積體電路晶粒具有側表面，且在模塑化合物層的形成期間模塑化合物層覆蓋側表面。
在一些其他實施例中，其中模塑化合物層具有第一填料在此空間中，且模塑化合物層具有第二填料在第一凸塊之間，且其中第一填料與第二填料具有大致相同的直徑。
在一些其他實施例中，上述方法更包含形成封裝層圍繞第一積體電路晶粒，其中在此空間中的模塑化合物層和封裝層包含大致相同的材料。
依據本揭露的一些實施例，提供封裝結構的形成方法。此方法包含提供第一積體電路晶粒。此方法也包含實施第一模封成型製程以形成圍繞第一積體電路晶粒的封裝層。此 方法更包含形成重佈線結構於第一積體電路晶粒和封裝層上方。此外，此方法包含形成複數個第一凸塊於重佈線結構上方。此方法也包含在第一凸塊形成之後，透過複數個第二凸塊將第二積體電路晶粒接合至重佈線結構。此方法更包含實施第二模封成型製程以形成模塑化合物層於這些第一凸塊之間和這些第二凸塊之間。在第二模封成型製程期間，模塑化合物層覆蓋第一凸塊和第二凸塊的表面。
在一些其他實施例中，上述方法更包含在第二模封成型製程之前，實施回焊(reflow)製程於第一凸塊和第二凸塊上方，其中此方法不包含在回焊製程之後以及在第二模封成型製程之前實施點膠製程。
在一些其他實施例中，其中第二積體電路晶粒具有側表面，且在實施第二模封成型製程之前，暴露出此側表面。
在一些其他實施例中，其中模塑化合物層具有第一填料分散於其中，且封裝層具有第二填料分散於其中，且其中第一填料與第二填料具有大致相同的直徑。
在一些其他實施例中，其中模塑化合物層具有大致平坦的頂表面，且第一凸塊具有上部從此頂表面突出。
在一些其他實施例中，其中第一凸塊之間具有第一距離，且第二積體電路晶粒與其中一個第一凸塊之間具有第二距離，且其中第一距離大於第二距離。
在一些其他實施例中，其中第二積體電路晶粒與其中一個第一凸塊之間具有第二距離，且第二凸塊之間具有第三距離，且其中第二距離大致與第三距離相同。
依據本揭露的一些實施例，提供封裝結構。此封裝結構包含第一積體電路晶粒。此封裝結構也包含重佈線結構位於第一積體電路晶粒上方，封裝層圍繞第一積體電路晶粒。此封裝結構更包含基底層位於重佈線結構上方，基底層具有複數個第一開口和複數個第二開口。此外，此封裝結構包含複數個第一凸塊填入這些第一開口中。此封裝結構也包含複數個第二凸塊填入這些第二開口中，第一凸塊具有大於第二凸塊的高度。此封裝結構更包含第二積體電路晶粒位於第二凸塊上方，在第二積體電路晶粒與基底層之間有一空間。此封裝結構包含模塑化合物層位於基底層上方，模塑化合物層填入此空間中並圍繞第一凸塊和第二凸塊。
在一些其他實施例中，其中模塑化合物層具有第一填料在此空間中，且模塑化合物層具有第二填料在第一凸塊之間，且其中第一填料與第二填料具有大致相同的直徑。
在一些其他實施例中，此封裝結構更包含形成封裝層圍繞第一積體電路晶粒，其中模塑化合物層具有第一填料在此空間中，且封裝層具有與第一填料大致相同的直徑的第二填料。
在一些其他實施例中，其中第一凸塊之間具有第一距離，且第二積體電路晶粒與其中一個第一凸塊之間具有第二距離，且其中第一距離大於第二距離。
在一些其他實施例中，其中第二積體電路晶粒與其中一個第一凸塊之間具有第二距離，且第二凸塊之間具有第三距離，且其中第二距離大致與第三距離相同。
在一些其他實施例中，其中模塑化合物層具有大致平坦的頂表面，且第一凸塊具有上部從此頂表面突出。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
120‧‧‧基底層
130‧‧‧重佈線結構
140、160、260‧‧‧導電層
150、170、220、250‧‧‧鈍化層
180‧‧‧導電特徵部件
190‧‧‧黏著膜
200‧‧‧積體電路晶粒
210‧‧‧半導體基底
230‧‧‧導電墊
240‧‧‧封裝層
270‧‧‧保護層
280‧‧‧保護基板
300、310‧‧‧開口
320、330‧‧‧連接器
320A、330A‧‧‧上部
320B、330B‧‧‧下部
340‧‧‧元件(積體電路晶粒)
341、342‧‧‧空間
350‧‧‧模塑化合物層
360‧‧‧頂表面
370‧‧‧底表面
400‧‧‧封裝結構
A‧‧‧區域

Claims (1)

  1. 一種封裝結構的形成方法，包括：提供一第一積體電路晶粒；形成一重佈線結構於該第一積體電路晶粒上方；形成一基底層於該重佈線結構上方，其中該基底層具有複數個第一開口和複數個第二開口，且該些第一開口寬於該些第二開口；形成複數個第一凸塊於該重佈線結構上方，其中該些第一凸塊具有一下部填入該些第一開口中；透過複數個第二凸塊將一第二積體電路晶粒接合至該重佈線結構，其中該些第二凸塊具有一下部填入該些第二開口中，且在該第二積體電路晶粒與該基底層之間有一空間；以及形成一模塑化合物層於該基底層上方，其中該模塑化合物層填入該空間中並圍繞該些第一凸塊和該些第二凸塊。
TW105138222A 2016-08-18 2016-11-22 封裝結構的形成方法 TW201807761A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/240,422 2016-08-18
US15/240,422 US10658334B2 (en) 2016-08-18 2016-08-18 Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die

Publications (1)

Publication Number Publication Date
TW201807761A true TW201807761A (zh) 2018-03-01

Family

ID=61192108

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105138222A TW201807761A (zh) 2016-08-18 2016-11-22 封裝結構的形成方法

Country Status (3)

Country Link
US (1) US10658334B2 (zh)
CN (1) CN107768311A (zh)
TW (1) TW201807761A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI679744B (zh) * 2018-10-04 2019-12-11 力成科技股份有限公司 多層封裝基板

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI624022B (zh) * 2016-11-15 2018-05-11 致伸科技股份有限公司 指紋辨識模組及其製造方法
US10103038B1 (en) * 2017-08-24 2018-10-16 Micron Technology, Inc. Thrumold post package with reverse build up hybrid additive structure
US20190067248A1 (en) 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
US10969359B1 (en) * 2018-02-16 2021-04-06 National Technology & Engineering Solutions Of Sandia, Llc Planar electrode arrays and fabrication methods thereof
DE102018111989B4 (de) * 2018-05-18 2024-05-08 Rogers Germany Gmbh Elektronikmodul und Verfahren zur Herstellung desselben
TWI710032B (zh) * 2018-08-01 2020-11-11 矽品精密工業股份有限公司 封裝堆疊結構及其製法暨封裝結構
CN110797293A (zh) * 2018-08-01 2020-02-14 矽品精密工业股份有限公司 封装堆叠结构及其制法暨封装结构
US10714454B2 (en) * 2018-08-14 2020-07-14 Semiconductor Components Industries, Llc Stack packaging structure for an image sensor
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
DE102018133479A1 (de) * 2018-12-21 2020-06-25 Rogers Germany Gmbh Verfahren zur Herstellung eines Elektronikmoduls und Elektronikmodul
WO2020166567A1 (ja) * 2019-02-15 2020-08-20 株式会社村田製作所 電子モジュール及び電子モジュールの製造方法
US11476198B2 (en) * 2019-12-11 2022-10-18 Intel Corporation Multi-level components for integrated-circuit packages
US11024576B1 (en) * 2019-12-31 2021-06-01 Texas Instruments Incorporated Semiconductor package with underfill between a sensor coil and a semiconductor die
US11830851B2 (en) 2020-04-07 2023-11-28 Mediatek Inc. Semiconductor package structure
DE102021107982B4 (de) 2020-04-07 2024-02-22 Mediatek Inc. Halbleiter-packagestruktur

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3821173B2 (ja) * 1996-12-19 2006-09-13 信越化学工業株式会社 エポキシ樹脂組成物
TWI221336B (en) * 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
TWI338941B (en) * 2007-08-22 2011-03-11 Unimicron Technology Corp Semiconductor package structure
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8039304B2 (en) * 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8008121B2 (en) * 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8669651B2 (en) * 2010-07-26 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structures with reduced bump bridging
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8482134B1 (en) * 2010-11-01 2013-07-09 Amkor Technology, Inc. Stackable package and method
TWI538071B (zh) * 2010-11-16 2016-06-11 星科金朋有限公司 具連接結構之積體電路封裝系統及其製造方法
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8779601B2 (en) * 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8981559B2 (en) * 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8546932B1 (en) * 2012-08-15 2013-10-01 Apple Inc. Thin substrate PoP structure
US8963339B2 (en) * 2012-10-08 2015-02-24 Qualcomm Incorporated Stacked multi-chip integrated circuit package
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9165876B2 (en) * 2013-03-11 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and methods for forming the same
US8970024B2 (en) * 2013-03-14 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding material forming steps
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8951834B1 (en) * 2013-06-28 2015-02-10 Stats Chippac Ltd. Methods of forming solder balls in semiconductor packages
US10068862B2 (en) * 2015-04-09 2018-09-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a package in-fan out package
US9898645B2 (en) * 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US10269773B1 (en) * 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10636775B2 (en) * 2017-10-27 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US11322449B2 (en) * 2017-10-31 2022-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package with fan-out structures
US10879183B2 (en) * 2018-06-22 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI679744B (zh) * 2018-10-04 2019-12-11 力成科技股份有限公司 多層封裝基板

Also Published As

Publication number Publication date
CN107768311A (zh) 2018-03-06
US10658334B2 (en) 2020-05-19
US20180053745A1 (en) 2018-02-22

Similar Documents

Publication Publication Date Title
US10658334B2 (en) Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
US11996401B2 (en) Packaged die and RDL with bonding structures therebetween
US11776935B2 (en) Semiconductor device and method of manufacture
US11094641B2 (en) Fan-out package having a main die and a dummy die
US9859229B2 (en) Package structure and method for forming the same
US10515937B2 (en) Semiconductor device and method of manufacture
TWI642157B (zh) 半導體封裝件及其形成方法
CN108074822B (zh) 封装结构的形成方法
TWI610412B (zh) 封裝結構及其形成方法
US20190006316A1 (en) Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same
US9859267B2 (en) Package structures and methods of forming the same
US9583420B2 (en) Semiconductor device and method of manufactures
TW201814850A (zh) 封裝結構及其形成方法
TW201608651A (zh) 半導體封裝及其形成方法
TW201919190A (zh) 封裝結構及其製造方法
US9870975B1 (en) Chip package with thermal dissipation structure and method for forming the same
TW201633476A (zh) 在緩衝層中具有開口的積體扇出結構
US11205615B2 (en) Semiconductor device and method of manufacture