CN104979334B - 半导体器件及方法 - Google Patents

半导体器件及方法 Download PDF

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Publication number
CN104979334B
CN104979334B CN201410256010.1A CN201410256010A CN104979334B CN 104979334 B CN104979334 B CN 104979334B CN 201410256010 A CN201410256010 A CN 201410256010A CN 104979334 B CN104979334 B CN 104979334B
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semiconductor element
substrate
layer
conductive
sealant
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CN104979334A (zh
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蔡承佑
魏琮商
林育生
邱文智
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了半导体器件及其制造方法。根据实施例，第一半导体管芯和第二半导体管芯接合至第一衬底。在第一半导体管芯和第二半导体管芯的上方并且在它们之间形成保护盖。将密封剂布置在保护盖的上方，并且去除密封剂的部分以露出保护盖，或者可选地露出第一半导体器件和第二半导体器件。然后，第一衬底可接合至第二衬底。

Description

半导体器件及方法
技术领域
本发明一般地涉及半导体技术领域，更具体地，涉及半导体器件及方法。
背景技术
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断改善，半导体工业已经历了快速的发展。在多数情况下，集成度的这种改善来自于最小部件尺寸的不断减小(例如，朝着小于20nm节点缩小半导体工艺节点)，从而允许更多的部件集成在给定的区域内。近年来，随着对微型化、更高的速度、更大的带宽以及更低的功耗和延迟的需求增长，对半导体管芯的更小和更具创造性的封装技术的需要也增长。
随着半导体技术进一步发展，作为有效替代品出现了堆叠的和接合的半导体器件以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中，将有源电路(诸如，逻辑电路、存储器电路以及处理器电路等)至少部分地制造在单独的衬底上，然后使它们物理接合和电接合在一起以形成功能器件。这种接合工艺应用尖端技术，并且期望得到改善。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：第一半导体器件，接合至第一衬底的第一面，所述第一半导体器件包括第一侧壁；第二半导体器件，接合至所述第一衬底的第一面，所述第二半导体器件包括第二侧壁；导电保护盖，与所述第一侧壁、所述第二侧壁以及所述第一衬底物理接触；以及密封剂，介于所述第一半导体器件和所述第二半导体器件之间，所述密封剂位于所述导电保护盖的至少一部分的上方。
在该半导体器件中，所述第一半导体器件具有背离所述第一衬底的第一表面，所述导电保护盖具有与所述第一表面平齐的顶面。
在该半导体器件中，所述第一半导体器件具有背离所述第一衬底的第一表面，所述导电保护盖覆盖所述第一表面。
该半导体器件还包括：第二衬底，在与所述第一半导体器件相对的面上接合至所述第一衬底。
在该半导体器件中，所述保护盖是钛。
在该半导体器件中，所述保护盖是铝。
在该半导体器件中，所述保护盖从所述第一侧壁延伸至所述第二侧壁。
根据本发明的另一方面，提供了一种半导体器件，包括：第一半导体管芯，与第二半导体管芯横向分离开；导电层，从所述第一半导体管芯的侧壁延伸至所述第二半导体管芯的侧壁，其中，所述导电层覆盖所述第一半导体管芯的侧壁和所述第二半导体管芯的侧壁；密封剂，位于所述导电层的上方并且介于所述第一半导体管芯和所述第二半导体管芯之间；第一衬底，接合至所述第一半导体管芯和所述第二半导体管芯；以及第二衬底，与所述第一半导体管芯相对地接合至所述第一衬底。
在该半导体器件中，所述导电层包括钛。
在该半导体器件中，所述导电层包括铝。
在该半导体器件中，所述导电层包括复合层。
在该半导体器件中，所述导电层没有延伸到所述第一半导体管芯的上方。
在该半导体器件中，所述导电层具有第一顶面，所述密封剂具有第二顶面，并且所述第一半导体管芯具有第三顶面，其中，所述第一顶面、所述第二顶面和所述第三顶面相互平齐。
在该半导体器件中，所述导电层具有第一顶面，所述密封剂具有第二顶面，并且所述第一半导体管芯具有第三顶面，其中，所述第一顶面和所述第二顶面相互平齐，但不与所述第三顶面平齐。
根据本发明的另一方面，提供了一种制造半导体器件的方法，所述方法包括：将第一半导体管芯和第二半导体管芯接合至第一衬底；在所述第一半导体管芯、所述第二半导体管芯以及所述第一衬底上方形成导电覆盖层；将密封剂施加在所述导电覆盖层的上方；以及去除所述密封剂的一部分，其中，去除所述密封剂的一部分露出所述导电覆盖层。
该方法还包括：将所述第一衬底接合至第二衬底。
在该方法中，去除所述密封剂的一部分还去除所述导电覆盖层的一部分，去除所述导电覆盖层的一部分露出所述第一半导体管芯。
在该方法中，在露出所述第一半导体管芯之前，结束去除所述密封剂的一部分。
在该方法中，形成所述导电覆盖层形成了第一材料的第一层和不同于所述第一材料的第二材料的第二层。
该方法还包括：减薄所述第二衬底以露出导电通孔。
附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明的各个方面。应该注意的是，根据工业中的标准实践，各种部件不是按照比例绘制。实际上，为了清楚讨论，可随意增大或减小各种部件的尺寸。
图1示出了根据一些实施例接合至第一衬底的第一半导体管芯和第二半导体管芯；
图2示出了根据一些实施例的保护盖的形成；
图3示出了根据一些实施例的密封剂的布置；
图4示出了根据一些实施例去除密封剂的一部分；
图5示出了根据一些实施例的载具的附接；
图6示出了根据一些实施例的第一衬底的减薄；
图7示出了根据一些实施例将第一衬底接合至第二衬底；
图8示出了根据实施例的去除密封剂但没有去除保护层；
图9示出了根据一些实施例的载具附接至保护盖；
图10示出了根据一些实施例将第一衬底接合至第二衬底；以及
图11示出了根据一些实施例的工艺流程图。
具体实施方式
以下公开内容提供了许多不同的实施例或实例以实现所提供主题的不同特征。下面描述了部件和布置的具体实例以简化本发明。当然，这些只是实例而并非意欲限定本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可包括以直接接触的方式形成第一部件和第二部件的实施例，且也可包括附加部件可形成在第一部件和第二部件之间，使得第一部件和第二部件可不直接接触的实施例。此外，本发明在各个实例中可能会重复参考标号和/或字母。这种重复是出于简化和清楚的目的，但其本身并不表明所讨论的各个实施例和/或配置之间的关系。
现在参照图1，示出了附接至第一衬底105的第一半导体管芯101和第二半导体管芯103。在实施例中，第一半导体管芯101和第二半导体管芯103可以是半导体器件(诸如，逻辑管芯、DRAM管芯、SRAM管芯或它们的组合等)。此外，尽管第一半导体管芯101和第二半导体管芯103可以是同一类型的器件(例如，二者都是DRAM管芯)，但它们可以可选地为不同类型的管芯(例如，第一半导体管芯101可以是逻辑管芯，而第二半导体管芯103可以是DRAM管芯)。第一半导体管芯101和第二半导体管芯103也可包括多个管芯的堆叠件。可以可选地使用任何适合的半导体管芯的组合以及任意数目的半导体管芯，并且所有这些数目、组合和功能都完全意欲包括在各实施例的范围内。
第一半导体管芯101可包括第二衬底107、位于第二衬底上的第一有源器件(未单独地示出)、第一金属化层(在图1中，由标号为109的单层表示)、第一钝化层110以及第一外部接触件111(在图1中示出为已接合至第三外部接触件123，下文会进一步进行讨论)。在实施例中，第二衬底107可包括掺杂或未掺杂的块状硅或绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括半导体材料(诸如，硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合)的层。可使用的其他衬底包括多层衬底、梯度衬底或混合取向衬底。
第一有源器件包括多种有源器件和无源器件(诸如，电容器、电阻器以及电感器等)，它们可用于生成满足期望的结构和功能要求的第一半导体管芯101的设计。可使用任何适合的方法在第二衬底107内或上形成第一有源器件。
第一金属化层109形成在第二衬底107和第一有源器件的上方，并且被设计为连接各种第一有源器件以形成功能电路。在实施例中，第一金属化层109由介电材料和导电材料的交替层形成，并且可通过任何适合的工艺(诸如，沉积、镶嵌以及双镶嵌等)来形成。在实施例中，具有通过至少一个层间介电层(ILD)与第二衬底107分隔开的四个金属化层，但是第一金属化层109的精确的数目取决于第一半导体管芯101的设计。
第一钝化层110可形成在第一金属化层的上方，以为下方的结构提供一定程度的保护。第一钝化层110可由一种或多种适合的介电材料(诸如，氧化硅、氮化硅、诸如掺碳氧化物的低k电介质、诸如掺多孔碳二氧化硅的超低k电介质或它们的组合等)制成。第一钝化层110可通过诸如化学汽相沉积(CVD)的工艺来形成，但是可使用任何适合的工艺，并且其厚度可介于约0.5μm和约5μm(诸如，约)之间。
第一外部接触件111可形成为穿过第一钝化层110从而提供介于第一金属化层109和例如位于第一衬底105上的第三外部接触件123(在图1中示出为已接合至第一外部接触件111)之间的接触件的导电区。在实施例中，第一外部接触件111可以是诸如微凸块的接触凸块，并且可包括诸如锡的材料或者诸如银或铜的其他适合的材料。在第一外部接触件111是焊锡凸块的实施例中，可通过任何适合的方法(诸如，蒸发、电镀、印刷、焊料转印以及植球)最初形成锡层来形成第一外部接触件111。一旦锡层已形成在结构上，执行回流以将材料成形为直径为例如约20μm的期望的凸块形状，但是可以可选地使用任何适合的尺寸。
然而，本领域的技术人员将意识到，尽管上文中已将第一外部接触件描述为微凸块，但是这些仅意欲说明而不意欲限制实施例。相反，可以可选地使用任何适合类型的外部接触件，诸如，可控塌陷芯片连接(C4)凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb层或它们的组合等。任何适合的外部连接件以及用于形成外部连接件的任何适合的工艺可用于第一外部接触件111，并且所有的这些外部连接件完全意欲包括在各实施例的范围内。
第二半导体管芯103可包括第三衬底113、第二有源器件(没有在图1中单独示出)、第二金属化层(在图1中由标号为115的单层表示)、第二钝化层116以及第二外部接触件117(在图1中示出为已接合至第三外部接触件123)。在实施例中，第三衬底113、第二有源器件、第二金属化层115、第二钝化层116以及第二外部接触件117可分别类似于第二衬底107、第一有源器件、第一金属化层109、第一钝化层110以及第一外部接触件111，但是它们可以可选地具有不同材料并且由不同工艺形成。例如，各个器件和层的准确的布置和形成至少部分取决于第二半导体管芯103的期望功能。
例如，第一衬底105可以是具有衬底通孔(TSV)601(在图1中没有示出，而是在下文中参照图6示出并对其进行描述)的中介层600(在图1中完全没有示出，而是在下文中参照图6示出并对其进行描述)的一部分。在该实施例中，第一衬底105可以是例如掺杂或未掺杂的硅衬底或绝缘体上硅(SOI)衬底的有源层。然而，第一衬底105可以可选地为玻璃衬底、陶瓷衬底、聚合物衬底或可提供适合保护和/或互连功能的其他任何衬底。这些材料和其他任何适合的材料可以可选地用于第一衬底105。
在一些实施例中，第一衬底105可包括电元件，诸如，电阻器、电容器、信号分配电路或它们的组合等。这些电元件可以是有源的、无源的或它们的组合。在其他实施例中，第一衬底105中不含有源和无源电元件。所有的这些组合完全意欲包括在各实施例的范围内。
此外，在一些实施例中，在制造工艺的该阶段中，第一衬底105是半导体晶圆，诸如，十二英寸的半导体晶圆。例如，第一衬底105可延伸超过图1中所示的边界以包括附加部分，该附加部分还包括用于制造附加结构的TSV。这样，当第一半导体管芯101和第二半导体管芯103接合至第一衬底105(如下文中仍然参照图1进一步描述的)时，组合结构为晶圆上芯片(CoW)配置。
可通过最初形成部分地穿过第一衬底105的TSV导体121来形成TSV通孔601。可通过以下步骤来形成TSV导体121：向第一衬底105施加适合的光刻胶并且使该光刻胶显影，然后蚀刻第一衬底105以生成TSV开口(如下文所讨论的，稍后填充的)。在该阶段可形成用于TSV导体121的开口以在第一衬底105内延伸至至少大于完成的第一衬底105的最终期望高度的深度处。因此，尽管深度取决于中介层600的总体设计，但是在第一衬底105的表面下方的深度可介于约1μm和约700μm之间，例如，具有约为50μm的深度。用于TSV导体121的开口可形成为介于约1μm和约100μm之间(诸如，约6μm)的直径。
一旦形成用于TSV导体121的开口，可以用例如衬里(在图1中没有单独示出)、势垒层(在图1中也没有单独示出)以及导电材料来填充用于TSV导体121的开口。在实施例中，衬里可以是通过工艺(诸如，化学汽相沉积、氧化、物理汽相沉积或原子层沉积等)而形成的介电材料(诸如，氮化硅、氧化硅、电介质聚合物或它们的组合等)。
势垒层可包括诸如氮化钛的导电材料，但是可以可选地使用其他材料(诸如，氮化钽、钛或另一电介质等)。可使用诸如PECVD的CVD工艺来形成势垒层。然而，可以可选地使用其他可选工艺(诸如，溅射、金属有机化学汽相沉积(MOCVD)、原子层沉积(ALD))。可形成势垒层以与用于TSV导体121的开口的下方的形状相符(contour to)。
导电材料可包括铜，但是可以可选地使用其他适合的材料(诸如，铝、钨、合金、掺杂的多晶硅以及它们的组合等)。可通过以下步骤来形成导电材料：沉积晶种层，然后在晶种层上电镀铜，填充并且过填充TSV导体121的开口。一旦已填充TSV导体121的开口，就可以通过研磨工艺(诸如，化学机械抛光(CMP))去除TSV导体121的开口的外部的多余的势垒层和多余的导电材料，但是可使用任何适合的去除工艺。
一旦已形成TSV导体121，就可在第一衬底105的第一面上形成第一再分布层119以提供TSV导体121、第三外部接触件123、第一半导体管芯101以及第二半导体管芯103之间的互连。可使用常用的方法来形成第一再分布层119从而形成集成电路中的互连线。在实施例中，第一再分布层119包括由金属(诸如，铝、铜、钨、钛以及它们的组合)所形成的至少一个导电层。可通过以下步骤来形成该至少一个导电层：形成晶种层、用图案化的光刻胶(未示出)覆盖晶种层，然后在光刻胶的开口内将金属镀在晶种层上。一旦完成，去除光刻胶和晶种层的位于光刻胶下方的部分，以保留厚度介于约2μm至约30μm之间、宽度约为5μm的该至少一个导电层。
本领域的技术人员应该理解，根据期望的特性，第一再分布层119可以是导电材料的单层或者可以可选地为导电材料的多层。例如，如上文中形成的第一再分布层119可镀有另一导电材料(诸如，金或铬)以为随后形成的连接件(在下文中描述的)提供良好的粘附性。可通过诸如CVD的工艺来完成该镀步骤。
在已形成第一再分布层119之后，可在第一再分布层119的上方形成第三钝化层120，并且可形成穿过介电材料的通孔以提供通向第一再分布层119的电通路。在实施例中，第三钝化层120可由一种或多种适合的介电材料(诸如，氧化硅、氮化硅、诸如掺碳氧化物的低k电介质、诸如掺多孔碳二氧化硅的超低k电介质或它们的组合等)制成。可通过诸如化学汽相沉积(CVD)的工艺来形成第三钝化层120，但是可使用任何适合的工艺，并且其厚度可介于约0.5μm和约5μm之间(诸如，约)。
一旦第一再分布层119和第三钝化层120已形成，第三外部接触件123就可形成为与位于第一衬底105的第一面上的第一再分布层119电连接。在实施例中，第三外部接触件123可类似于第一外部接触件111和第二外部接触件117，诸如，为使用回流工艺所形成的微凸块。然而，可以可选地使用任何适合类型的外部接触件以及其他任何适合的形成工艺，并且所有的这些类型和工艺完全意欲包括在各实施例的范围内。
一旦准备好，就可使用例如接合工艺将第一半导体管芯101和第二半导体管芯103接合至第一衬底105。在第一外部接触件111、第二外部接触件117和第三外部接触件123是焊料微凸块的实施例中，可通过以下步骤来执行接合工艺：首先将第一外部接触件111和第二外部接触件117与第三外部接触件123中各自的对应部分对准，然后将第一外部接触件111和第二外部接触件117布置为与第三外部接触件123物理接触。一旦接触，然后可执行回流工艺，以使第一外部接触件111、第二外部接触件117和第三外部接触件123回流，从而将第一外部接触件111和第二外部接触件117与第三外部接触件123接合。
一旦接合，可在第一半导体管芯101、第二半导体管芯103和第一衬底105之间的空间内注入或以其他方式形成第一底部填充材料125。第一底部填充材料125例如可包括分配在第一半导体管芯101、第二半导体管芯103与第一衬底105之间的液体环氧树脂，然后其固化变硬。该第一底部填充材料125可用于防止在第一外部接触件111、第二外部接触件117和第三外部接触件123内形成裂纹，其中，裂纹通常由热应力引起。
可选地，可变形的凝胶或硅橡胶可形成在第一半导体管芯101、第二半导体管芯103与第一衬底105之间以帮助防止在第一外部接触件111、第二外部接触件117和第三外部接触件123内出现裂纹。可通过在第一半导体管芯101、第二半导体管芯103与第一衬底105之间注入或以其他方式布置凝胶或硅橡胶来形成该凝胶或硅橡胶。可变形的凝胶或硅橡胶也可在随后的处理期间释放应力。
图2示出了在第一半导体管芯101的上方、第二半导体管芯103的上方以及在第一半导体管芯101和第二半导体管芯103之间形成与中介层600(下文中参照图6进行描述)的顶面接触的保护盖201。在实施例中，为了在第一半导体管芯101、第二半导体管芯103和中介层600之间提供等电位以及为了增大第一半导体管芯101、第二半导体管芯103与中介层600之间的粘附性，保护盖201可以是导电的。通过提供等电位，可使在制造工艺期间可能出现的任何电荷累积(可能破坏第一半导体管芯101、第二半导体管芯103或两者)在第一半导体管芯101、第二半导体管芯103以及中介层600之间达到分布均衡。这有助于减小或消除由电荷分布不均产生的损坏或其他有害影响。
在实施例中，保护盖201可以是金属材料，诸如，钛、铝、铝铜(AlCu)等。可使用工艺(诸如，物理汽相沉积、等离子体增强物理汽相沉积、化学汽相沉积、等离子体增强化学汽相沉积、原子层沉积或它们的组合等)来形成保护盖201。保护盖201也形成为使其厚度适于使电荷均衡。这样，可使用允许导电的任何适合的厚度，但是在一些实施例中，厚度可介于约和约之间。然而，也可使用任何适合的导电材料(诸如，多晶硅)以及其他任何适合的形成工艺。
此外，尽管在上文中讨论了保护盖201并且在图2中将其示出为单层，但是这仅意欲是示出实施例而不意在限制。例如，在其他实施例中，保护盖201可以是包括保护盖201内的两个或多个单独的层的复合层(在图2中由标号为203的虚线表示)。在特定的实施例中，保护盖201可包括例如钛的第一层和例如铝的第二层。可以可选地使用任何适合的层组合以形成用于保护盖201的复合材料。
图3示出了将密封剂301布置在第一半导体管芯101上方、第二半导体管芯103上方以及第一半导体管芯101和第二半导体管芯103之间。在实施例中，密封剂301可以是模塑料、聚酰亚胺、PPS、PEEK、PES、耐热水晶树脂或它们的组合等。在实施例中，可将接合后的第一半导体管芯101、第二半导体管芯103以及第一衬底105布置在成型室(未示出)内，并且可将密封剂301注入或以其他方式布置在成型室内。成型室将密封剂301成形为期望的形状以密封第一半导体管芯101、第二半导体管芯103以及第一衬底105从而为第一半导体管芯101、第二半导体管芯103以及第一衬底105提供支持和保护。
一旦准备就绪，可固化密封剂301以使密封剂301变硬从而提供最优保护。尽管确切的固化工艺至少部分取决于选作密封剂301的特定材料，但是在模塑料被选作密封剂301的实施例中，可通过工艺(诸如，在约60秒至约3000秒(诸如，约600秒)的时间段内将密封剂301加热至约100℃和约130℃之间(诸如，约125℃))来发生固化。此外，可将引发剂和/或催化剂包括在密封剂301内以更好地控制固化工艺。
通过将密封剂301布置在保护盖201的上方，在形成保护盖201期间不会将密封剂301放置在该位置处。特别是，在例如使用PVD来形成保护盖201的实施例中，密封剂301在PVD工艺期间的工艺条件下是不存在的。因为这种PVD工艺条件会导致密封剂301的材料(例如，模塑料)的除气(outgassing)，所以要避免这种除气和它对大批量制造工艺的工艺设备的后续影响。
图4示出了从第一半导体管芯101和第二半导体管芯103的表面去除密封剂。在实施例中，例如可使用CMP工艺去除或减薄密封剂，其中，化学蚀刻剂和研磨剂用于使密封剂301发生反应并且将其研磨掉直到通过密封剂301露出第一半导体管芯101和第二半导体管芯103，从而保留密封剂301的介于以及环绕第一半导体管芯101和第二半导体管芯103的部分。这样，第一半导体管芯101和第二半导体管芯103可具有也与密封剂301平齐的平坦表面。
此外，在该实施例中，除了减薄和去除密封剂301之外，CMP工艺也将减薄和去除保护盖201的部分。具体地，CMP工艺将去除保护盖201的位于第一半导体管芯101和第二半导体管芯103上方的部分，从而露出第一半导体管芯101和第二半导体管芯103的表面。这样，第一半导体管芯101、第二半导体管芯103、密封剂301以及保护盖201都将彼此平齐，并且保护盖201没有延伸到第一半导体管芯101和第二半导体管芯103上方。
图5示出了例如使用粘合剂503将载具501附接至露出的第一半导体管芯101、第二半导体管芯103、保护盖201以及密封剂301。在实施例中，载具501可包括例如玻璃、氧化硅、氧化铝等。载具501的厚度可大于约12毫寸(mils)。
粘合剂503可用于将载具501粘合至第一半导体管芯101和第二半导体管芯103。粘合剂503可以是任何适合的粘合剂，诸如，当暴露于UV光而失去其粘性的紫外线(UV)胶。然而，也可使用其他类型的粘合剂(诸如，压敏粘合剂、可辐射固化粘合剂、环氧树脂或它们的组合等)。可使用任何适合的粘合剂以将载具501粘合至第一半导体管芯101、第二半导体管芯103、密封剂301以及保护盖201，并且所有这些粘合剂均完全意欲包括在各实施例的范围内。
图6示出了一旦附接载具501，可进一步对第一衬底105进行处理以形成中介层600。在实施例中，减薄第一衬底105以露出TSV导体121(例如，见图1)从而形成延伸穿过第一衬底105的TSV 601。在实施例中，减薄第一衬底105的第二面可保留内衬有衬里的TSV601，或者也去除衬里的一部分以露出导电材料。可通过研磨、化学机械抛光(CMP)和蚀刻的组合来执行减薄第一衬底105的第二面。
例如，可执行物理研磨工艺以最初去除第一数量的第一衬底105。在已去除最初的第一数量之后，可以物理研磨工艺之后进行CMP工艺从而使用化学反应剂和研磨剂的组合以去除附加数量的第一衬底105并且露出TSV导体121内的导电材料。一旦将第一衬底105的第二面的一部分去除后，然后可应用蚀刻工艺(诸如，干蚀刻工艺)以使第一衬底105的第二面凹进(如果期望的话)，并且允许TSV 601从第一衬底105的第二面凸起。在实施例中，TSV601可从第一衬底105的第二面凸起的距离介于约0.5μm至约10μm之间(诸如，约5μm)。
一旦TSV 601从第一衬底105凸起，可形成第四钝化层604以保护TSV601。在实施例中，第四钝化层604可由一种或多种适合的介电材料(诸如，氧化硅、氮化硅、诸如掺碳氧化物的低k电介质、诸如掺多孔碳二氧化硅的超低k电介质或它们的组合等)制成。第四钝化层604可通过低温工艺(诸如，低温化学汽相沉积(LTCVD))形成(为了帮助避免密封剂301的任何除气)，并且可具有介于约0.5μm和约5μm之间(诸如，约)的厚度。然而，尽管在特定实施例中描述了低温沉积工艺，但是可以可选地使用任何适合的沉积工艺，诸如，CVD、PVD、ALD或它们的组合等。
在已形成第四钝化层604之后，也可减薄第四钝化层604以再次露出TSV 601。在实施例中，化学机械抛光工艺可用于减薄第四钝化层604直到露出TSV 601。可选地，在已露出TSV 601之后，例如可使用干蚀刻使第四钝化层604凹进，从而使TSV 601从第四钝化层604凸起。
图6也示出了第二再分布层603、第五钝化层605以及第四外部接触件607的形成。可使用常用的方法来形成类似于第一再分布层119(上文中参照图1做了讨论)的第二再分布层603，从而形成集成电路中的互连线。在实施例中，第二再分布层603包括由金属(诸如，铝、铜、钨、钛以及它们的组合等)所形成的至少一个导电再分布层。可通过以下步骤来形成该至少一个导电再分布层：形成晶种层、用图案化的光刻胶(未示出)覆盖晶种层，然后在光刻胶的开口内的晶种层上镀金属。一旦完成，去除光刻胶和晶种层的位于光刻胶下方的部分，保留厚度介于约2μm和约30μm之间、宽度约为5μm的至少一个导电再分布层。
此外，本领域的技术人员应该意识到，根据期望的特性，第二再分布层603可以是单层导电材料或者可以可选地为多层导电材料。例如，以上形成的第二再分布层603可镀有另一种导电材料(诸如，金或铬)以为随后形成的连接件(下文中将描述的)提供良好的粘合性。可通过诸如CVD的工艺来完成该镀的步骤。
一旦已形成第二再分布层603，可在第二再分布层603的上方形成第五钝化层605。第五钝化层605可形成在第二再分布层603的上方，并且可形成穿过第五钝化层605的通孔以提供通向第二再分布层603的电通路。在实施例中，第五钝化层605可由一种或多种适合的介电材料(诸如，氧化硅、氮化硅、诸如掺碳氧化物的低k电介质、诸如掺多孔碳二氧化硅的超低k电介质或它们的组合等)制成。可通过诸如低温化学汽相沉积(CVD)的工艺来形成第五钝化层605，但是可使用其他任何适合的工艺，并且可具有介于约0.5μm和约5μm之间(诸如，约)的厚度。
一旦已在第一衬底105的第二面的上方形成第二再分布层603和第五钝化层605，可形成第四外部接触件607以提供介于第二再分布层603和例如位于第二衬底701(在图6中未示出，而是在下文中参照图7进一步示出和进行描述)上的第五外部接触件703之间的接触件的导电区以帮助形成中介层600。在实施例中，第四外部接触件607可以是诸如可控塌陷芯片连接(C4)凸块的接触凸块，并且可包括诸如锡的材料或诸如银或铜的其他适合的材料。在第四外部接触件607是焊锡凸块的实施例中，可通过任何适合的方法(诸如，蒸发、电镀、印刷、焊料转印、植球等)最初形成锡层来形成第四外部接触件607。一旦锡层已形成在结构上，执行回流以将材料成形为直径为例如约80μm的期望的凸块形状。
然而，本领域的技术人员将意识到，尽管上文中将第四外部接触件607描述为C4凸块，但这些只意欲说明而不意欲限制实施例。相反，可以可选地使用任何适合类型的外部接触件，诸如，微凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb层或它们的组合等。任何适合的外部连接件以及用于形成外部连接件的任何适合的工艺可用于第四外部接触件607，并且所有这些外部连接件完全意欲包括在各实施例的范围内。
图7示出了第二衬底701，其中，第二衬底701具有位于第二衬底701的第一面上的第五外部接触件703(图7中将其示出为已接合至第四外部接触件607)以及位于第二衬底701的第二面上的第六外部接触件705。在实施例中，第二衬底701例如可以是为例如印刷电路板(未示出)或其他外部器件提供电连接的封装衬底。例如，第二衬底701可包括多个导电层(没有单独示出)，其中的一些层是第二衬底701内的中间层。可将这些层蚀刻为具有不同宽度和长度的导线，并且通过层间通孔来连接。线和通孔可共同形成电网络以将DC电源、接地电位和信号从第二衬底701的一面发送至另一面。本领域的技术人员将意识到，第二衬底701可由有机(层压)材料(诸如，双马来酰亚胺三嗪(BT)、诸如液晶聚合物(LCP)的聚合物基材料、诸如低温共烧陶瓷(LTCC)的陶瓷材料或者硅或玻璃中间层等)制造。本领域的技术人员也应该意识到，导电层和通孔可由任何适合的导电材料(诸如，铜、铝、银、金、其他金属、合金和/或它们的组合等)形成，并且可通过任何适合的技术(诸如，电化学镀(ECP)、化学镀、诸如溅射、印刷以及化学汽相沉积(CVD)方法的其他沉积方法等)来形成。
在一些实施例中，第二衬底701可包括电元件(诸如，电阻器、电容器、信号分配电路或它们的组合等)。这些电元件可以是有源的、无源的或它们的组合。在其他实施例中，第二衬底701中没有有源和无源电元件。所有的这些组合完全意欲包括在各实施例的范围内。
第二衬底701可包括位于第二衬底701的第一面上的第五外部接触件703。在实施例中，第五外部接触件703可类似于位于第一衬底105上的第四外部接触件607(上文中参照图6进行了讨论)，诸如，使用沉积和回流工艺所形成的C4凸块。然而，可以可选地使用不同于第四外部接触件607的材料和方法来形成第五外部接触件703，并且所有适合的方法和材料可用于第四外部接触件607。
在第二衬底701的第二面上，可形成第六外部接触件705以为其他器件(在图7中没有单独示出)提供附加连接。在实施例中，第六外部接触件705可包括具有单个球的球栅阵列(BGA)。在实施例中，单个球可包括诸如锡的材料或诸如银或铜的其他适合的材料。在实施例中，可通过最初溅射沉积导电材料的晶种层(例如，凸块下金属化层)，然后图案化位于导电材料的晶种层上方的光刻材料(未示出)来形成第六外部接触件705。随着光刻材料准备就绪并且露出晶种层的一部分，电化学镀(ECP)工艺可用于在光刻材料的开口内镀晶种层的露出部分。一旦已完成镀的步骤，可去除光刻材料，并且使用例如干蚀刻来去除晶种层的没有被镀的部分(因为它们被光刻材料所覆盖)。一旦准备就绪，执行回流工艺以将材料成形为直径为例如约250μm的期望的凸块形状。
一旦已形成第五外部接触件703，第二衬底701可接合至第一衬底105(同样，接合至第一半导体管芯101和第二半导体管芯103)。在第一衬底105是半导体晶圆的实施例中，诸如，在上文中参照图1所述的CoW方法中，可首先通过将第一半导体管芯101、第二半导体管芯103、保护盖201以及密封剂301与载具501分离(debond)来开始接合工艺。在紫外线胶用作粘合剂503的实施例中，通过紫外线辐射照射粘合剂503，直到它失去一些或全部粘性。因此，在没有粘合剂503的情况下，可容易将第一半导体管芯101、第二半导体管芯103、保护盖201以及密封剂301与载具501分离开。
然而，本领域的技术人员应该意识到，尽管在粘合剂503是紫外线胶时，可使用以上所讨论的紫外线照射技术，但是其他类型的粘合剂503可使用其他方法以将第一半导体管芯101、第二半导体管芯103、保护盖201以及密封剂301与载具501分离。例如，根据所选择的确切的粘合剂503，可使用热脱粘工艺或激光脱粘工艺。任何以及所有适合的脱粘工艺都可用于将第一半导体管芯101、第二半导体管芯103、保护盖201以及密封剂301与载具501分离开，并且所有这些方法都完全意欲包括在各实施例的范围内。
一旦已将第一半导体管芯101、第二半导体管芯103、保护盖201以及密封剂301与载具501分离，接下来可通过将第一衬底105的接合至第一半导体管芯101和第二半导体管芯103的部分与剩余的半导体晶圆进行分割来继续接合工艺。在实施例中，可通过使用锯片(未示出)切割例如划线(例如，没有功能电路的区域)内的第一衬底105来进行分割，划线位于第一衬底105的包括功能电连接件和/或功能电路的各区域之间。这种切割将第一衬底105的接合至第一半导体管芯101和第二半导体管芯103的部分与剩余的半导体晶圆分离开。此外，锯片也切断了位于第一衬底105上方的密封剂301。
然而，本领域的技术人员应该意识到，使用锯片将第一衬底105与半导体晶圆进行分割仅仅是说明性的实施例而并不意欲限制。可以可选地使用将第一衬底105进行分割的可选方法，诸如，使用一次或多次蚀刻以将第一衬底105与半导体晶圆进行分割。可以可选地使用这些方法和其他任何适合的方法以将第一衬底105进行分割。
一旦第一衬底105进行分割，可通过使第四外部接触件607和第五外部接触件703相互对准来继续接合工艺。在实施例中，可使用例如拾取和放置工具来执行对准，从而使第四外部接触件607和第五外部接触件703相互对准。在这种实施例中，机器人工具使用例如真空固定器(vacuum holder)以抓取并且操纵接合后的第一半导体管芯101、第二半导体管芯103以及第一衬底105，然后使第四外部接触件607和第五外部接触件703对准。
然而，尽管上文已描述了拾取和放置工具，但是该描述意欲说明而不意欲对实施例进行限制。相反，可以可选地使用使第四外部接触件607与第五外部接触件703对准的任何适合的方法。所有这些方法完全意欲包括在各实施例的范围内。
一旦对准，第四外部接触件607与第五外部接触件703彼此物理接触。一旦物理接触，可执行回流工艺以使第四外部接触件607和第五外部接触件703回流，使得它们接合在一起，从而将第一衬底105接合至第二衬底701。
一旦接合，可将第二底部填充材料707注入或以其他方式形成在第一衬底105和第二衬底701之间的空间内。例如，第二底部填充材料707可包括液体环氧树脂，该液体环氧树脂分配在第一衬底105和第二衬底701之间，然后使其固化以变硬。这种第二底部填充材料707可用于防止在第四外部接触件607和第五外部接触件703内形成裂纹，其中，裂纹通常由热应力引起。
可选地，可在第一衬底105和第二衬底701之间形成可变形的凝胶或硅橡胶以帮助防止在第四外部接触件607和第五外部接触件703内出现裂纹。可通过注入或以其他方式将凝胶或橡胶布置在第一衬底105和第二衬底701之间来形成这种凝胶或硅橡胶。可变形的凝胶或硅橡胶也可在随后的处理期间提供减轻的应力。
通过对晶圆上芯片结构进行分割并且将晶圆上芯片结构接合至第二衬底701，可形成衬底上晶圆上芯片(Chip on Wafer on Substrate，CoWoS)结构。然而，尽管详细描述中使用了该实施例，但是该实施例意欲说明而不意欲将实施例限于CoWoS结构。相反，可使用任何适合的结构，并且所有这些结构完全意欲包括在各实施例的范围内。
通过提供与第一半导体管芯101、第二半导体管芯103以及中介层600接触的保护盖201，保护盖201可均衡第一半导体管芯101、第二半导体管芯103以及中介层600之间的电荷。这种均衡允许均衡在随后的制造工艺期间可能出现的任何电荷累积，从而减小或消除由于电荷分布不均而可能出现的任何损害。这种减小有助于防止对第一半导体管芯101、第二半导体管芯103以及中介层600造成损害，提高总产量。
图8示出了另一个实施例，其中，在去除密封剂301期间(上文中参照图4进行了描述)，没有从第一半导体管芯101和第二半导体管芯103的顶面去除保护盖201。在这个实施例中，仍然使用CMP工艺来减薄和去除密封剂301，但是在从保护盖201的部分处去除之后密封剂301但在从第一半导体管芯101和第二半导体管芯103去除保护盖201之前，终止或停止该工艺。这样，保护盖201具有位于第一半导体管芯101上方的顶面和位于第二半导体管芯103上方的顶面，这两个顶面都与密封剂301平齐。
图9示出了在将密封剂301减薄之后载具501和粘合剂503的布置。在实施例中，可如上文中参照图5所述来附接载具501和粘合剂503。然而，在该实施例中，因为还没有通过CMP工艺去除保护盖201，所以粘合剂503被布置为与第一半导体管芯101和第二半导体管芯103上方的保护盖201接触，并且也被布置为与密封剂301接触。
图9也示出了一旦载具501和粘合剂503附接至保护盖201和密封剂301，可减薄第一衬底105，并且可在第一衬底105的第二面上形成第四钝化层604、第二再分布层603、第五钝化层605以及第四外部接触件607。可如上文参照图6所述来执行这些工艺。
图10示出了第一衬底105接合至第二衬底701(具有第五外部接触件703和第六外部接触件705)。在实施例中，第一衬底105可以用类似上文中参照图7所述的方式而接合至第二衬底701。例如，第五外部接触件703与第四外部接触件607对准并且布置为与第四外部接触件607物理接触，然后执行回流工艺。然而，可以可选地使用任何适合的接合工艺。
通过将保护盖201保留在第一半导体管芯101和第二半导体管芯103的上方，并且仍与中介层600接触，因为现在保护盖201包括第一半导体管芯101和第二半导体管芯103之上的区域，所以保护盖201内的电荷分布可以是均匀分布的。此外，保护盖201可为第一半导体管芯101和第二半导体管芯103提供额外的物理保护。这样，可减少或消除由于电荷分布不均匀所导致损害以及物理损害，从而允许更高的总产量。
图11示出了形成在此描述的结构的流程图。在实施例中，第一步骤1101包括将第一半导体管芯101和第二半导体管芯103附接至第一衬底105。在第二步骤1103中，将保护盖201施加至第一半导体管芯101、第二半导体管芯103以及第一衬底105。在第三步骤1105中，将密封剂301施加在保护盖201、第一半导体管芯101以及第二半导体管芯103的上方。在第四步骤1107中，将密封剂301的一部分和保护盖201的一部分从第一半导体管芯101和第二半导体管芯103的顶面去除。可选地，可将保护盖201保留在第一半导体管芯101和第二半导体管芯103的上方。
在第五步骤1109中，将载具501附接至保护盖201或者第一半导体管芯101和第二半导体管芯103。在第六步骤1111中，减薄第一衬底105以形成TSV 601。在第七步骤1113中，在第一衬底105的经过减薄的面上形成第四外部接触件607。在第八步骤1115中，将第一衬底105的一部分与剩余的半导体晶圆中进行分割。在第九步骤1117中，将第一衬底105的被分割的部分接合至第二衬底701。
通过形成所述的半导体器件，保护盖201可用于均匀分布在处理期间可能累积的电荷。如果这些电荷未经检查，则可能潜在地损害半导体器件并且有可能致使其无效。然而，通过均匀分布累积的电荷，可减小或消除由这种电荷所引起的损害，导致产量总体提高。
根据一个实施例，提供了一种半导体器件，该半导体器件包括接合至第一衬底的第一面的第一半导体器件，并且该第一半导体器件包括第一侧壁。第二半导体器件接合至第一衬底的第一面，该第二半导体器件包括第二侧壁。导电保护盖与第一侧壁、第二侧壁以及第一衬底物理接触，并且密封剂介于第一半导体器件和第二半导体器件之间，该密封剂位于导电保护盖的至少一部分的上方。
根据另一实施例，提供了一种半导体器件，该半导体器件包括与第二半导体管芯横向分隔开的第一半导体管芯。导电层从第一半导体管芯的侧壁延伸至第二半导体管芯的侧壁，其中，导电层覆盖第一半导体管芯的侧壁和第二半导体管芯的侧壁。密封剂位于导电层的上方并且介于第一半导体管芯和第二半导体管芯之间。第一衬底接合至第一半导体管芯和第二半导体管芯；以及第二衬底，与第一半导体管芯相对地接合至第一衬底。
根据另一实施例，提供了一种制造半导体器件的方法，该方法包括将第一半导体管芯和第二半导体管芯接合至第一衬底。在第一半导体管芯、第二半导体管芯以及第一衬底的上方形成导电覆盖层。将密封剂施加在导电覆盖层的上方，以及去除密封剂的一部分，其中，去除密封剂的一部分使得露出导电覆盖层。
以上概括了几个实施例的特征，使得本领域的技术人员可更好地理解本发明的各方面。本领域的技术人员应该理解，他们可容易将本发明用作基础来设计或修改用于实现与在此所介绍的实施例相同的目的和/或取得相同的有益效果的其他工艺和结构。本领域的技术人员也应该意识到，这种等同构造并没有背离本发明的精神和范围，并且在没有背离本发明的精神和范围的情况下，他们在此可做出各种修改、替换以及变化。

Claims (13)

1.一种半导体器件，包括：
第一半导体器件，接合至第一衬底的第一面，所述第一半导体器件包括第一侧壁；
第二半导体器件，接合至所述第一衬底的第一面，所述第二半导体器件包括第二侧壁；
导电保护盖，与所述第一侧壁、所述第二侧壁以及所述第一衬底物理接触；以及
密封剂，介于所述第一半导体器件和所述第二半导体器件之间，所述密封剂位于所述导电保护盖的至少一部分的上方；
其中，所述第一半导体器件具有背离所述第一衬底的第一表面，所述导电保护盖具有与所述第一表面平齐的顶面，并且所述密封剂的顶面与所述导电保护盖的顶面平齐。
2.根据权利要求1所述的半导体器件，还包括：第二衬底，在与所述第一半导体器件相对的面上接合至所述第一衬底。
3.根据权利要求1所述的半导体器件，其中，所述导电保护盖是钛。
4.根据权利要求1所述的半导体器件，其中，所述导电保护盖是铝。
5.根据权利要求1所述的半导体器件，其中，所述导电保护盖从所述第一侧壁延伸至所述第二侧壁。
6.一种半导体器件，包括：
第一半导体管芯，与第二半导体管芯横向分离开；
导电层，从所述第一半导体管芯的侧壁延伸至所述第二半导体管芯的侧壁，其中，所述导电层覆盖所述第一半导体管芯的侧壁和所述第二半导体管芯的侧壁，其中，所述导电层没有延伸到所述第一半导体管芯的上方；
密封剂，位于所述导电层的上方并且介于所述第一半导体管芯和所述第二半导体管芯之间；
第一衬底，接合至所述第一半导体管芯和所述第二半导体管芯；以及
第二衬底，与所述第一半导体管芯相对地接合至所述第一衬底；
其中，所述导电层具有第一顶面，所述密封剂具有第二顶面，并且所述第一半导体管芯具有第三顶面，其中，所述第一顶面、所述第二顶面和所述第三顶面相互平齐。
7.根据权利要求6所述的半导体器件，其中，所述导电层包括钛。
8.根据权利要求6所述的半导体器件，其中，所述导电层包括铝。
9.根据权利要求6所述的半导体器件，其中，所述导电层包括复合层。
10.一种制造半导体器件的方法，所述方法包括：
将第一半导体管芯和第二半导体管芯接合至第一衬底；
在所述第一半导体管芯、所述第二半导体管芯以及所述第一衬底上方形成导电覆盖层；
将密封剂施加在所述导电覆盖层的上方；以及
去除所述密封剂的一部分，其中，去除所述密封剂的一部分露出所述导电覆盖层；
其中，去除所述密封剂的一部分还去除所述导电覆盖层的一部分，去除所述导电覆盖层的一部分露出所述第一半导体管芯；其中，去除后的导电覆盖层具有第一顶面，去除后的密封剂具有第二顶面，并且所述第一半导体管芯具有第三顶面，所述第一顶面、所述第二顶面和所述第三顶面相互平齐。
11.根据权利要求10所述的方法，还包括：将所述第一衬底接合至第二衬底。
12.根据权利要求10所述的方法，其中，形成所述导电覆盖层形成了第一材料的第一层和不同于所述第一材料的第二材料的第二层。
13.根据权利要求10所述的方法，还包括：减薄所述第一衬底以露出导电通孔。
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