DE102014119308B4 - Zweischritt-Formmasse-Schleifen für Kapselungsanwendungen - Google Patents
Zweischritt-Formmasse-Schleifen für Kapselungsanwendungen Download PDFInfo
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- DE102014119308B4 DE102014119308B4 DE102014119308.3A DE102014119308A DE102014119308B4 DE 102014119308 B4 DE102014119308 B4 DE 102014119308B4 DE 102014119308 A DE102014119308 A DE 102014119308A DE 102014119308 B4 DE102014119308 B4 DE 102014119308B4
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Abstract
Verfahren, das Folgendes umfasst:Anbringen eines Dies (110) an einer oberen Fläche eines Substrats (202), um eine Vorrichtung auszubilden;Kapseln des Dies (110) und der oberen Fläche des Substrats (202) in einer Formmasse (304), wobei die Formmasse (304) eine erste Dicke über dem Die aufweist;Entfernen eines Teils, aber nicht der gesamten Dicke der Formmasse (304) über dem Die (110), um eine die verbleibende Dicke der Formmasse und eine plane obere Oberfläche der Formmasse bereitzustellen; weitere Verarbeitung der Vorrichtung; undEntfernen der verbleibenden Dicke der Formmasse (304) über dem Die (110).
Description
- HINTERGRUND
- Halbleitervorrichtungen werden in einer Vielzahl von elektronischen Anwendungen verwendet, beispielsweise PCs, Mobiltelefonen, Digitalkameras und anderer elektronischer Ausrüstung. Halbleitervorrichtungen werden üblicherweise hergestellt, indem isolierende oder dielektrische Schichten, leitende Schichten und Halbleiterschichten verschiedener Materialien nach einander über einem Halbleitersubstrat abgeschieden werden und die verschiedenen Materialschichten mittels Lithographie strukturiert werden, um Schaltungskomponenten und Elemente darauf auszubilden.
- Die Halbleiterindustrie hat aufgrund von fortlaufenden Verbesserungen bei der Integrationsdichte einer Vielzahl von elektronischen Komponenten (z.B. Transistoren, Dioden, Widerstände, Kondensatoren etc.) ein schnelles Wachstum erlebt. Diese Verbesserung der Integrationsdichte rührte hauptsächlich von einer Verkleinerung des HalbleiterVerfahrensknotens (z.B. Verkleinern des Halbleiterverfahrensknotens hin zu dem Unter-20nm-Knoten) her. Mit der wachsenden Nachfrage nach Miniaturisierung, höherer Geschwindigkeit und höherer Bandbreite sowie niedrigerem Stromverbrauch und niedrigerer Latenz ist auch der Bedarf nach kleineren und kreativeren Kapselungstechniken von Halbleiter-Dies gewachsen.
- Zum Stand der Technik wird auf die
US 2013 / 0 147 054 A1 US 2013 / 0 134 559 A1 US 2016 / 0 284 568 A1 - Figurenliste
- Aspekte der vorliegenden Offenbarung werden am besten aus der folgenden detaillierten Beschreibung verstanden, wenn sie mit den beigefügten Figuren gelesen wird. Man beachte, dass in Übereinstimmung mit dem üblichen Vorgehen in der Branche verschiedene Einrichtungen nicht maßstabsgetreu gezeichnet sind. Tatsächlich können die Abmessungen der verschiedenen Einrichtungen zur Klarheit der Beschreibung beliebig vergrößert oder verkleinert sein.
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1 bis10 zeigen Schnittansichten von Zwischenschritten bei dem Ausbilden eines Packages in Übereinstimmung mit einigen Ausführungsformen. -
11 ist ein Flussdiagramm des Verfahrens zum Ausbilden eines Packages in Übereinstimmung mit einigen Ausführungsformen. - DETAILLIERTE BESCHREIBUNG
- Die folgende Offenbarung sieht viele verschiedene Ausführungsformen oder Beispiele vor, um verschiedene Einrichtungen der Erfindung zu implementieren. Spezielle Beispiele von Komponenten und Anordnungen sind unten beschrieben, um die vorliegende Offenbarung zu vereinfachen. Das Ausbilden einer ersten Einrichtung über oder auf einer zweiten Einrichtung in der folgenden Beschreibung kann beispielsweise Ausführungsformen umfassen, in denen die erste und die zweite Einrichtung in direktem Kontakt ausgebildet sind, und kann auch Ausführungsformen umfassen, in denen zusätzliche Einrichtungen zwischen der ersten und der zweiten Einrichtung ausgebildet sein können, so dass die erste und die zweite Einrichtung nicht in direktem Kontakt sein müssen. Zusätzlich kann die vorliegende Offenbarung Bezugszeichen und/oder Buchstaben in den verschiedenen Beispielen wiederholen. Diese Wiederholung dient der Einfachheit und Klarheit und erzwingt als solche keine Beziehung zwischen den verschiedenen beschriebenen Ausführungsformen und/oder Konfigurationen.
- Weiter können räumlich relative Begriffe, wie „unten“, „unter“, „unterer“, „über“, „oberer“ und ähnliche, hier zur Einfachheit der Beschreibung verwendet werden, um die Beziehung eines Elements oder einer Einrichtung mit einem oder mehreren anderen Elementen oder Einrichtungen zu beschreiben, wie sie in den Figuren gezeigt sind. Die räumlich relativen Begriffe sollen verschiedene Orientierungen der Vorrichtung, die verwendet oder betrieben wird, zusätzlich zu der in den Figuren gezeigten Orientierung umfassen. Die Vorrichtung kann anders orientiert sein (um 90 Grad gedreht oder in einer anderen Orientierung), und die räumlich relativen Begriffe, die hier verwendet werden, können ebenfalls demgemäß interpretiert werden.
- Ausführungsformen werden mit Bezug auf Ausführungsformen in einem speziellen Kontext beschrieben, d.h. ein gestapeltes Die-Interposer-Substrat-Package oder -Gehäuse unter Verwendung von Chip-auf-Wafer-auf-Substrat-(CoWoS)-Verarbeitung. Andere Ausführungsformen können jedoch auf andere Packages angewendet werden, etwa ein gestapeltes Die-Die-Substrat-Package, und andere Verarbeitung kann verwendet werden.
- Allgemein gesprochen können Ausführungsformen der vorliegenden Offenbarung einen verbesserten Ansatz bereitstellen, um Ereignisse von elektrostatischer Entladung (ESD) während eines Herstellungsverfahrens zu verringern oder zu minimieren oder vielleicht gänzlich zu vermeiden, beispielsweise eines Flip-Chip-Herstellungsverfahrens (engl. „controlled collapse chip connection”, C4). Als solche können die Verfahrensfenster zur Herstellung von CoWoS-Vorrichtungen erweitert werden, was die Herstellungskosten und - komplexität verringert, während es den Ertrag steigert.
- Während statische Elektrizität in der Herstellungsumgebung nicht vollständig vermieden werden kann, können ihre Auswirkungen verringert werden. Ein Ansatz, der hier beschrieben ist, liegt darin, eine Isolierschicht auf einem Die (etwa der Rückseite eines Dies) während eines C4-Bondhügel-Verfahrens bereitzustellen. Dies kann den Weg verkleinern oder ausschalten, durch den statische Elektrizität empfindliche Komponenten erreichen und zerstören kann.
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1 bis10 zeigen Schnittansichten von Zwischenschritten beim Ausbilden eines Packages in Übereinstimmung mit einigen Ausführungsformen und11 ist ein Flussdiagramm des Verfahrens, das in1 bis10 gezeigt ist, in Übereinstimmung mit einigen Ausführungsformen. -
1 zeigt das Ausbilden eines oder mehrerer Dies110 (Schritt702 ). Ein Substrat102 umfasst einen oder mehrere Dies110 während der Verarbeitung. Das Substrat102 umfasst eine Verbindungsstruktur106 über einer aktiven Oberfläche102A mit Bondkontaktstellen108 , die in und/oder auf der Verbindungsstruktur106 ausgebildet sind. - Das Substrat
102 kann aus einem Halbleitermaterial hergestellt sein wie Silizium, Germanium, Diamant oder Ähnlichem. Alternativ können Verbindungsmaterialien wie Silizium-Germanium, Siliziumkarbid, Galliumarsenid, Indiumarsenid, Indiumphosphid, Silizium-Germanium-Karbid, Galliumarsenid-Phosphid, Gallium-Indium-Phosphid, Kombinationen daraus und Ähnliches auch verwendet werden. Zusätzlich kann das Substrat102 ein Silizium-auf-Isolator-(SOI)-Substrat sein. Im Allgemeinen umfasst ein SOI-Substrat eine Schicht aus einem Halbleitermaterial wie epitaktischem Silizium, Germanium, Silizium-Germanium, SOI, Silizium-Germanium-auf-Isolator (SGOI) oder Kombinationen daraus. - Das Substrat
102 kann aktive und passive Vorrichtungen umfassen (in1 nicht gezeigt). Wie ein Fachmann erkennen wird, können eine breite Vielfalt von Vorrichtungen wie Transistoren, Kondensatoren, Widerständen, Kombinationen daraus und Ähnlichem verwendet werden, um die strukturellen und funktionalen Anforderungen des Designs für den einen oder die mehreren Dies110 zu erzeugen. Die Vorrichtungen können durch jedes geeignete Verfahren ausgebildet werden. - Eine Verbindungsstruktur
106 , die eine oder mehrere dielektrische Schichten und zugehörige Metallisierungsstrukturen umfasst, wird auf der aktiven Oberfläche202A ausgebildet. Die eine oder mehreren Metallisierungsstrukturen in den dielektrischen Schichten können elektrische Signale zwischen den Vorrichtungen leiten, etwa durch Durchkontaktierungen und/oder Leiterbahnen, und können auch verschiedene elektrische Vorrichtungen aufweisen, etwa Kondensatoren, Widerstände, Induktoren oder Ähnliches. Die verschiedenen Vorrichtungen und Metallisierungsstrukturen können unter einander verbunden sein, um eine oder mehrere Funktionen auszuführen. Die Funktionen können Speicherstrukturen, Verarbeitungsstrukturen, Sensoren, Verstärker, Stromversorgung, Eingabe-/Ausgabeschaltungen oder Ähnliches umfassen. - Eine oder mehrere dielektrische Schichten zwischen den Metallisierungen (IMD), die in der Verbindungsstruktur
208 ausgebildet sind, können beispielsweise aus einem low-k-dielektrischen Material ausgebildet werden, etwa Phosphorsilikatglas (PSG), Borphosphorsilikatglas (BPSG), Fluorsilikatglas (FSG), SiOxCy, Spin-On-Glas, Spin-On-Polymere, Silizium-Kohlenstoff-Material, Verbindungen daraus, Verbundstoffe daraus, Kombinationen daraus oder Ähnlichem, durch jedes geeignete Verfahren, das in der Branche bekannt ist, wie Rotationsbeschichtung, chemische Gasphasenabscheidung (CVD), CVD im Plasma (PECVD), chemische Gasphasenabscheidung im hochdichten Plasma (HDP-CVD) oder Ähnliches. Eine Metallisierungsstruktur kann in der IMD-Schicht ausgebildet werden, beispielsweise indem Fotolithographie-Techniken verwendet werden, um ein Fotoresist-Material auf der IMD-Schicht abzuscheiden und zu strukturieren, um Abschnitte der IMD-Schicht freizulegen, die die Metallisierungsstruktur werden sollen. Ein Ätzverfahren, etwa ein anisotropes Trockenätzverfahren, kann verwendet werden, um Vertiefungen und/oder Öffnungen in der IMD-Schicht auszubilden, die zu den freiliegenden Abschnitten der IMD-Schicht gehören. Die Vertiefungen und/oder Öffnungen können mit einer Diffusionsbarriere-Schicht ausgekleidet sein und mit einem leitenden Material gefüllt sein. Die Diffusionsbarriere-Schicht kann eine oder mehrere Schichten aus TaN, Ta, TiN, Ti, CoW oder Ähnlichem umfassen, die durch Atomlagenabscheidung (ALD) oder Ähnliches abgeschieden werden, und das leitende Material kann Kupfer, Aluminium, Wolfram, Silber und Kombinationen daraus umfassen oder Ähnliches, das durch chemische Gasphasenabscheidung (CVD), physikalische Gasphasenabscheidung (PVD) oder Ähnliches abgeschieden wird. Jedes überschüssige Material der Diffusionsbarriere-Schicht und/oder des leitenden Materials auf der IMD-Schicht kann entfernt werden, etwa indem ein chemischmechanisches Polieren (CMP) verwendet wird. - Die Bondkontaktstellen
108 werden in und/oder auf der Verbindungsstruktur106 ausgebildet. In einigen Ausführungsformen werden die Bondkontaktstellen108 ausgebildet, indem Vertiefungen (nicht gezeigt) in einer oder mehreren der dielektrischen Schichten der Verbindungsstruktur106 ausgebildet werden. Die Vertiefungen können ausgebildet werden, um es zu ermöglichen, dass die Bondkontaktstellen108 in die Verbindungsstruktur106 eingebettet werden. In anderen Ausführungsformen fehlen die Vertiefungen, da die Bondkontaktstellen108 auf der Verbindungsstruktur106 ausgebildet werden. Die Bondkontaktstellen108 verbinden den einen oder die mehreren Dies110 mit dem nachfolgend gebondeten Substrat202 elektrisch und/oder körperlich (siehe4 ). In einigen Ausführungsformen umfassen die Bondkontaktstellen108 eine dünne Keimschicht (nicht gezeigt), die aus Kupfer, Titan, Nickel, Gold, Ähnlichem oder einer Kombination daraus hergestellt ist. Das leitende Material der Bondkontaktstellen108 kann über der dünnen Keimschicht abgeschieden werden. Das leitende Material kann durch ein elektrochemisches Plattierverfahren, CVD, ALD, PVD, Ähnliches oder eine Kombination daraus ausgebildet werden. In einer Ausführungsform besteht das leitende Material der Bondkontaktstellen108 aus Kupfer, Wolfram, Aluminium, Silber, Gold, Ähnlichem oder einer Kombination daraus. - In einer Ausführungsform sind die Bondkontaktstellen
108 Under-Bump-Metallisierungen (UBMs), die drei Schichten aus leitenden Materialien umfassen, etwa einer Schicht aus Titan, einer Schicht aus Kupfer und einer Schicht aus Nickel. Ein Fachmann wird jedoch erkennen, dass es viele geeignete Anordnungen von Materialien und Schichten gibt, etwa eine Anordnung aus Chrom/Chrom-Kupfer-Legierung/Kupfer/Gold, eine Anordnung aus Titan/Titan-Wolfram/Kupfer oder eine Anordnung aus Kupfer/Nickel/Gold, die für das Ausbilden der UBMs108 verwendet werden können. Alle geeigneten Materialien oder Schichten aus Materialien, die für die UBMs108 verwendet werden können, sollen vollständig in dem Schutzumfang der vorliegenden Anmeldung enthalten sein. - In
2 wird das Substrat102 einschließlich der Verbindungsstruktur106 in einzelne Dies110 vereinzelt (Schritt704 ). Üblicherweise enthalten die Dies110 die gleichen Schaltungen, etwa Vorrichtungen und Metallisierungsstrukturen, obwohl die Dies unterschiedliche Schaltungen aufweisen können. In einigen Ausführungsformen wird das Vereinzeln durch Sägen, Laser, Schneiden, Ähnliches oder einer Kombination daraus ausgeführt. -
3 zeigt das Ausbilden einer ersten Seite eines Substrats202 (Schritt706 ). Das Substrat202 kann aus einem Halbleitermaterial hergestellt sein, etwa Silizium, Germanium, Diamant oder Ähnlichem. Alternativ können Verbindungsmaterialien wie Silizium-Germanium, Siliziumkarbid, Galliumarsenid, Indiumarsenid, Indiumphosphid, Silizium-Germanium-Karbid, Galliumarsenid-Phosphid, Gallium-Indium-Phosphid, Kombinationen daraus und Ähnliches auch verwendet werden. Zusätzlich kann das Substrat202 ein SOI-Substrat sein. Im Allgemeinen umfasst ein SOI-Substrat eine Schicht aus einem Halbleitermaterial, etwa epitaktischem Silizium, Germanium, Silizium-Germanium, SOI, SGOI oder Kombinationen daraus. Das Substrat202 basiert in einer alternativen Ausführungsform auf einem isolierenden Kern, etwa einem glasfaserverstärkten Harz-Kern. Ein beispielhaftes Kernmaterial ist Glasfaser-Harz, etwa FR4. Alternativen für das Kernmaterial umfassen Bismaleimid-Triazin-(BT)-Harz oder alternativ andere Platinen-Materialien oder -Filme. Aufbau-Filme wie Ajinomot Build-Up-Film (ABF) oder andere Laminate können für das Substrat202 verwendet werden. - Das Substrat
202 kann aktive und passive Vorrichtungen umfassen (in3 nicht gezeigt), die in und/oder auf einer ersten Oberfläche202A des Substrats202 ausgebildet sind. Wie ein Fachmann erkennen wird, können eine breite Vielfalt von Vorrichtungen wie Transistoren, Kondensatoren, Widerständen, Kombinationen daraus und Ähnliches verwendet werden, um die strukturellen und funktionalen Anforderungen des Designs für das Substrat202 zu erzeugen. Die Vorrichtungen können mittels jedes geeigneten Verfahrens ausgebildet werden. In einigen Ausführungsformen ist das Substrat202 ein Interposer, der im Allgemeinen keine aktiven Vorrichtungen umfasst, obwohl der Interposer passive Vorrichtungen umfassen kann, die in und/oder auf einer ersten Oberfläche202A ausgebildet sind. - Durchkontaktierungen (TVs)
206 werden so ausgebildet, dass sie sich von der ersten Oberfläche202A des Substrats202 in das Substrat202 erstrecken. Die TVs206 werden auch manchmal als Durch-Substrat-Durchkontaktierungen oder Durch-Silizium-Durchkontaktierungen bezeichnet, wenn das Substrat202 ein Siliziumsubstrat ist. Die TVs206 können ausgebildet werden, indem Vertiefungen in dem Substrat202 ausgebildet werden, beispielsweise durch Ätzen, Fräsen, Laser-Techniken, Ähnliches oder eine Kombination daraus. Eine dünne Sperrschicht kann gleichmäßig über der Vorderseite des Substrats202 und in den Öffnungen abgeschieden werden, etwa durch CVD, ALD, PVD, thermische Oxidation, Ähnliches oder eine Kombination daraus. Die Sperrschicht kann ein Nitrid oder ein Oxinitrid umfassen, etwa Titannitrid, Titanoxinitrid, Tantalnitrid, Tantaloxinitrid, Wolframnitrid, Ähnliches oder eine Kombination daraus. Ein leitendes Material kann über der dünnen Sperrschicht und in den Öffnungen abgeschieden werden. Das leitende Material kann durch ein elektrochemisches Plattierverfahren, CVD, ALD, PVD, Ähnliches oder eine Kombination daraus ausgebildet werden. Beispiele von leitenden Materialien sind Kupfer, Wolfram, Aluminium, Silber, Gold, Ähnliches oder eine Kombination daraus. Überschüssiges leitendes Material und überschüssige Anteile der Sperrschicht werden von der Vorderseite des Substrats entfernt, beispielsweise durch ein CMP. Somit können die TVs206 ein leitendes Material und eine dünne Sperrschicht zwischen dem leitenden Material und dem Substrat202 umfassen. - Eine Verbindungsstruktur
208 wird über der ersten Oberfläche202A des Substrats202 ausgebildet und wird verwendet, um die integrierten Schaltungsvorrichtungen, wenn vorhanden, und/oder die TVs206 mit einander und/oder mit externen Vorrichtungen elektrisch zu verbinden. Die Verbindungsstruktur208 kann eine oder mehrere dielektrische Schichten und zugehörige Metallisierungsstrukturen in den dielektrischen Schichten umfassen. Die Metallisierungsstrukturen können Durchkontaktierungen und/oder Leiterbahnen umfassen, um alle Vorrichtungen und/oder TVs206 mit einander und/oder mit einer externen Vorrichtung zu verbinden. Die Metallisierungsstrukturen werden manchmal als Umverteilungsleitungen (RDLs) bezeichnet. Die dielektrischen Schichten können Siliziumoxid, Siliziumnitrid, Siliziumkarbid, Siliziumoxinitrid, ein Low-k-Dielektrikum wie PSG, BPSG, FSG, SiOxCy, Spin-On-Glas, Spin-On-Polymere, Silizium-Kohlenstoff-Material, Verbindungen daraus, Verbundstoffe davon, Kombinationen daraus oder Ähnliches umfassen. Die dielektrischen Schichten können durch jedes geeignete Verfahren abgeschieden werden, das in der Branche bekannt ist, etwa Rotationsbeschichtung, CVD, PECVD, HDP-CVD oder Ähnliches. Eine Metallisierungsstruktur kann in der dielektrischen Schicht ausgebildet werden, beispielsweise indem Fotolithographie-Techniken verwendet werden, um ein Fotoresist-Material auf der dielektrischen Schicht abzuscheiden und zu strukturieren, um Abschnitte der dielektrischen Schicht freizulegen, die die Metallisierungsstruktur werden sollen. Ein Ätzverfahren, etwa ein anisotropes Trockenätzverfahren, kann verwendet werden, um Vertiefungen und/oder Öffnungen in der dielektrischen Schicht zu erzeugen, die zu den freiliegenden Abschnitten der dielektrischen Schicht gehören. Die Vertiefungen und/oder Öffnungen können mit einer Diffusionsbarriere-Schicht ausgekleidet werden und mit einem leitenden Material gefüllt werden. Die Diffusionsbarriere-Schicht kann eine oder mehrere Schichten aus TaN, Ta, TiN, Ti, CoW oder Ähnlichem umfassen, die durch ALD oder Ähnliches abgeschieden werden, und das leitende Material kann Kupfer, Aluminium, Wolfram, Silber und Kombinationen daraus oder Ähnliches umfassen, das durch CVD, PVD oder Ähnliches abgeschieden wird. Alles überschüssige Material der Diffusionsbarriere-Schicht und/oder leitendes Material auf der dielektrischen Schicht kann entfernt werden, etwa indem CMP verwendet wird. - Elektrische Anschlussteile
210 werden an der oberen Fläche und elektrisch verbunden mit der Verbindungsstruktur208 ausgebildet. Die elektrischen Anschlussteile210 können aus Lötkugeln, Metallsäulen, Flip-Chip-(C4 )-Bondhügeln, Mikrobondhügeln, Bondhügeln, die durch stromloses Nickel-stromloses Palladium-Gold-Immersions-Techniken (engl. „electroless nickel-electroless palladium-immersion gold“, ENEPIG) ausgebildet werden, oder Ähnlichem bestehen. Die elektrischen Anschlussteile können ein leitendes Material umfassen wie Lot, Kupfer, Aluminium, Gold, Nickel, Silber, Palladium, Zinn, Ähnliches oder eine Kombination daraus. In einer Ausführungsform, in der die elektrischen Anschlussteile210 Löt-Bondhügel sind, werden die elektrischen Anschlussteile210 ausgebildet, indem anfänglich eine Schicht aus Lot ausgebildet wird, durch so allgemein verwendete Verfahren wie Verdampfung, Elektroplattieren, Drucken, Lot-Transfer, Lötkugel-Platzierung oder Ähnliches. Nachdem die Schicht aus Lot auf der Struktur ausgebildet wurde, kann ein Aufschmelzen (engl. „reflow“) ausgeführt werden, um das Material in die angestrebte Bondhügel-Form zu formen. In einer anderen Ausführungsform sind die elektrischen Anschlussteile210 Metallsäulen (etwa Kupfersäulen), die durch Sputtern, Drucken, Elektroplattieren, stromloses Plattieren, CVD oder Ähnliches ausgebildet werden. Die Metallsäulen können frei von Lot sein und im Wesentlichen vertikale Seitenwände haben. In einigen Ausführungsformen wird eine Metall-Deckschicht (nicht gezeigt) auf den Metallsäulen-Anschlussteilen210 ausgebildet. Die Metall-Deckschicht kann Nicke, Zinn, Zinn-Blei, Gold, Silber, Palladium, Indium, Nickel-Palladium-Gold, Nickel-Gold, Ähnliches oder eine Kombination daraus umfassen und kann durch ein Plattierverfahren ausgebildet werden. -
4 zeigt das Anbringen der Dies110 an der ersten Seite des ersten Substrats (Schritt708 ), beispielsweise durch Flip-Chip-Bonden, um ein Die-Package auszubilden. Die elektrischen Anschlussteile210 verbinden die Schaltungen in den Dies110 elektrisch mit der Verbindungsstruktur208 und den TVs206 . - Die Dies
110 können einen Logik-Die umfassen, etwa eine zentrale Recheneinheit (CPU), einen Grafikprozessor (GPU), Ähnliches oder eine Kombination daraus. In einigen Ausführungsformen umfassen die Dies110 einen Die-Stapel (nicht gezeigt), der sowohl Logik-Dies als auch Speicher-Dies umfassen kann. Die Dies110 können einen Eingabe-/Ausgabe-(I/O)-Die umfassen, etwa einen breiten I/O-Die. - Das Bonden zwischen den Dies
110 und der Verbindungsstruktur208 kann ein Lot-Bonden oder ein direktes Metall-Metall-Bonden (etwa Kupfer-Kupfer oder Zinn-Zinn) sein. In einer Ausführungsform werden die Dies110 mit der Verbindungsstruktur208 durch ein Aufschmelzverfahren gebondet. Während des Aufschmelzverfahrens sind die elektrischen Anschlussteile210 in Kontakt mit den Bondkontaktstellen108 und der Verbindungsstruktur208 , um die Dies110 körperlich und elektrisch mit der Verbindungsstruktur208 zu verbinden. - Ein Unterfüllungsmaterial
302 kann in dem Zwischenraum zwischen den Dies110 und der Verbindungsstruktur208 und die elektrischen Anschlussteile210 umgebend eingespritzt oder anderweitig ausgebildet werden. Das Unterfüllungsmaterial302 kann beispielsweise ein flüssiges Epoxid, ein verformbares Gel, Silizium-Kautschuk oder Ähnliches sein, das zwischen die Strukturen eingebracht wird und dann ausgehärtet wird, um hart zu werden. Dieses Unterfüllungsmaterial wird unter anderem verwendet, um Schäden an den elektrischen Anschlussteilen210 zu verringern und sie zu schützen. - Nachdem die Dies
110 an dem Substrat202 befestigt wurden, werden die Dies110 gekapselt (Schritt710 ). In einigen Ausführungsformen werden die Dies110 durch eine Formmasse304 gekapselt. Die Formmasse304 kann auf den Dies110 abgeformt werden, beispielsweise durch Formpressen. In einigen Ausführungsformen besteht die Formmasse304 aus einer Formverbindung, einem Polymer, einem Epoxid, einem Siliziumoxid-Füllmaterial, Ähnlichem oder einer Kombination daraus. Ein Aushärteschritt kann ausgeführt werden, um die Formmasse304 auszuhärten, wobei das Aushärten ein thermisches Aushärten, ein Ultraviolett-(UV)-Aushärten, Ähnliches oder eine Kombination daraus sein kann. - In einigen Ausführungsformen werden die Dies
110 in der Formmasse304 vergraben und nach dem Aushärten der Formmasse304 wird ein erstes Planarisierungsverfahren auf die Formmasse304 angewendet (Schritt712 ), wie in5 gezeigt ist. In einer Ausführungsform ist das erste Planarisierungsverfahren ein Schleifverfahren, obwohl andere Techniken einschließlich Ätzen, Laser-Ablation, Polieren und Ähnliches angewendet werden können. Das erste Planarisierungsverfahren wird verwendet, um die Formmasse304 zu planarisieren, um eine im Wesentlichen planare obere Fläche304A der Formmasse304 bereitzustellen. Das erste Planarisierungsverfahren entfernt einige, aber nicht alle, Formmasse304 über den Dies110 , so dass rückseitige Oberflächen110A der Dies immer noch in Formmasse304 vergraben sind. In einer Ausführungsform hat die verbleibende Menge an Formmasse304 über den rückseitigen Oberflächen110A der Dies110 eine Dicke T1 von mehr als etwa 30 µm, z.B. zwischen etwa 30 µm und etwa 50 µm. - Die Dicke T1 ist eine Dicke der Formmasse
304 , die ausreicht, um den elektrostatischen Entladungsweg zwischen den Dies110 und dem Träger-Substrat402 zu blockieren und es auch zu ermöglichen, dass die Formmasse304 überarbeitet wird, ohne die Dies100 freizulegen. Nach dem ersten Planarisierungsverfahren könnte beispielsweise ein Fehler auf der Formmasse304 gefunden werden und ein Überarbeitungsverfahren, z.B. ein Schleifverfahren, kann ausgeführt werden müssen, um den Fehler zu beseitigen. Indem mindestens 30 µm an Formmasse304 über den rückseitigen Oberflächen110A der Dies bleibt, werden die rückseitigen Oberflächen110A der Dies während des Überarbeitungsverfahrens nicht freigelegt, und daher bleiben sie durch die Formmasse304 geschützt. -
6 zeigt das Umdrehen des Die-Packages und das Anbringen der Oberfläche304A der Formmasse304 an einem Träger-Substrat402 , um es zu ermöglichen, dass eine zweite Seite des Substrats202 bearbeitet wird. Das Träger-Substrat402 kann jedes geeignete Substrat sein, das (während zwischengeschalteter Vorgänge des Herstellungsverfahrens) mechanischen Halt für die Komponenten und Strukturen über dem Träger-Substrat402 bereitstellt. Das Träger-Substrat402 kann ein Wafer sein, der Glas, Quarz, Silizium (z.B. ein Siliziumwafer), Siliziumoxid, eine Metallplatte, ein Keramikmaterial oder Ähnliches umfasst. - Beim Ausbilden der zweiten Seite wird ein Verdünnungsverfahren auf die zweite Seite des Substrats
202 angewendet, um das Substrat auf eine zweite Oberfläche202B zu verdünnen, bis die TVs206 freigelegt wurden. In einer Ausführungsform ist das Verdünnungsverfahren ein Schleifverfahren, obwohl andere Techniken einschließlich Ätzen, Laser-Ablation, Polieren und Ähnliches angewendet werden können. Eine oder mehrere dielektrische Schichten406 können auf der zweiten Oberfläche202B des Substrats202 ausgebildet werden. Eine oder mehrere Metallisierungsstrukturen406 können auf der zweiten Oberfläche202B und in den dielektrischen Schichten404 mittels ähnlicher Verfahren wie oben beschrieben ausgebildet werden. - Es werden auch elektrische Anschlussteile
408 auf der zweiten Seite des Substrats202 ausgebildet und mit den TVs206 elektrisch verbunden. In einigen Ausführungsformen sind die elektrischen Anschlussteile408 Lötkugeln, Metallsäulen, C4-Bondhügel, Mikrobondhügel, ENEPIG-ausgebildete Bondhügel oder Ähnliches. Die elektrischen Anschlussteile408 können ein leitendes Material umfassen, etwa Lot, Kupfer, Aluminium, Gold, Nickel, Silber, Palladium, Zinn, Ähnliches oder eine Kombination daraus. In einer anderen Ausführungsform sind die elektrischen Anschlussteile408 Metallsäulen (etwa Kupfersäulen), die durch Sputtern, Drucken, Elektroplattieren, stromloses Plattieren, CVD oder Ähnliches ausgebildet werden. Die Metallsäulen können frei von Lot sein und im Wesentlichen vertikale Seitenwände haben. In einigen Ausführungsformen wird eine Metall-Deckschicht (nicht gezeigt) auf den Metallsäulen-Anschlussteilen408 ausgebildet. Die Metall-Deckschicht kann Nickel, Zinn, Zinn-Blei, Gold, Silber, Palladium, Indium, Nickel-Palladium-Gold, Nickel-Gold, Ähnliches oder eine Kombination daraus umfassen und kann durch ein Plattierverfahren ausgebildet werden. Die elektrischen Anschlussteile408 können verwendet werden, um mit einer zusätzlichen elektrischen Komponente gebondet zu werden, die ein Halbleitersubstrat, ein Package-Substrat, eine Leiterplatte (PCB) oder Ähnliches sein kann. - Während dem Ausbilden der zweiten Seite des Substrats
202 (z.B. dem Ausbilden der dielektrischen Schichten404 , der Metallisierungsstrukturen406 und/oder der elektrischen Anschlussteile408 ) können die Dies110 , das Substrat202 und die elektrischen Anschlussteile408 positiv aufgeladen werden, während das Träger-Substrat402 negativ geladen werden kann, oder umgekehrt. Daher kann die Grenzfläche zwischen den Dies110 und dem Träger-Substrat402 ein elektrostatischer Entladungsweg sein. Die Entladung dieser elektrostatischen Ladung kann Vorrichtungen in und/oder auf den Dies110 und dem Substrat202 beschädigen. Indem eine Menge an Formmasse304 belassen wird, die die rückseitigen Oberflächen110A der Dies110 bedeckt, bildet die Formmasse304 eine Isolierschicht, die den elektrostatischen Entladungsweg zwischen den Dies110 und dem Träger-Substrat402 blockiert. Das Träger-Substrat402 und die rückseitigen Oberflächen110A der Dies100 sind durch Formmasse304 getrennt, die die Dicke T1 hat, die eine Dicke der Formmasse304 ist, die ausreicht, um den elektrostatischen Entladungsweg zwischen den Dies110 und dem Träger-Substrat402 zu blockieren. -
7 zeigt das Aufbringen eines Schutzfilms420 auf die zweite Seite des Substrats202 (Schritt714 ) und das Entfernen des Träger-Substrats402 . Der Schutzfilm420 kann ein Band sein, etwa ein Backgrinding-(BG)-Band (vom UV- oder Nicht-UV-Typ), das verwendet werden kann, um die zweite Seite des Substrats202 vor Schleifrückständen während eines nachfolgenden Planarisierungsverfahrens der Formmasse (siehe8 ) zu schützen. Der Schutzfilm420 kann über der zweiten Seite des Substrats202 beispielsweise mittels einer Rolle (nicht gezeigt) aufgebracht werden. Der Schutzfilm420 kann eine Dicke haben, die ausreicht, um die elektrischen Anschlussteile408 vollständig zu bedecken, wie in7 gezeigt ist. -
8 zeigt das Anwenden eines zweiten Planarisierungsverfahrens auf die Formmasse304 (Schritt716 ). In einer Ausführungsform ist das zweite Planarisierungsverfahren ein Schleifverfahren, obwohl andere Techniken einschließlich Ätzen, Laser-Ablation, Polieren und Ähnliches angewendet werden können. Das zweite Planarisierungsverfahren wird verwendet, um überschüssige Anteile der Formmasse304 zu entfernen, wobei die überschüssigen Anteile über rückseitigen Oberflächen110A der Dies110 liegen. In einigen Ausführungsformen werden die rückseitigen Oberflächen110A der Dies110 freigelegt und sind plan mit der Oberfläche304A der Formmasse304 . - In einigen Ausführungsformen können nach dem Planarisierungsverfahren die Dies
110 eine Dicke von der aktiven Oberfläche102A zu der rückseitigen Oberfläche110A von etwa 2,2 µm haben, verglichen mit einem Die, der das oben beschriebene Zweischritt-Formmasse-Planarisierungsverfahren nicht nutzt und der üblicherweise eine Dicke von etwa 1,05 µm hat. Ein weiterer Aspekt der Ausführungsformen der vorliegenden Offenbarung liegt in einem Unterschied in der Rauheit der Oberfläche304A der Formmasse304 , wenn die oben beschriebenen Verfahren angewendet werden. In einigen Ausführungsformen wurde beispielsweise eine Rauheit von etwa 1 bis 3 µm beobachtet, verglichen mit einer Rauheit von etwa 0 bis etwa 1 µm, wenn das Verfahren nicht angewendet wird. Der Unterschied in der Dicke der Dies110 und der Oberflächen-Rauheit der Formmasse304 können zumindest teilweise darauf zurückgeführt werden, dass das Planarisierungsverfahren der zweiten Formmasse ausgeführt wird (siehe Schritt716 oben), während der Schutzfilm420 auf der gegenüberliegenden Seite des Die-Packages (z.B. über der zweiten Seite des Substrats202 ) liegt, da der Schutzfilm420 weicher als das Substrat202 ist, das auf der gegenüberliegenden Seite des Die-Packages während des ersten Planarisierungsverfahrens der Formmasse ist (siehe Schritt712 oben). Daher kann der weichere Schutzfilm420 komprimiert werden und einen Teil des Drucks aufnehmen, der während des zweiten Planarisierungsverfahrens der Formmasse ausgeübt wird, was dazu führen kann, dass das zweite Planarisierungsverfahren der Formmasse weniger der rückseitigen Oberfläche110A der Dies110 verbraucht, und auch die Rauheit der Oberfläche304A der Formmasse304 erhöhen kann. -
9 zeigt das Entfernen des Schutzfilms420 und das Anbringen einer optionalen Wärmesenke502 auf den rückseitigen Oberflächen110A der Dies110 und der Oberfläche304A der Formmasse304 . Die Wärmesenke502 kann an den Dies110 und der Formmasse304 durch einen Haftfilm (nicht gezeigt) befestigt werden. Der Haftfilm kann auf der Wärmesenke502 oder auf die rückseitigen Oberflächen110A der Dies110 und der Oberfläche304A der Formmasse aufgebracht werden, so dass er eine Dicke hat, die nicht so dick ist, dass sie Wärmeabfuhr unterdrückt. Der Haftfilm kann ein Epoxid, ein Harz, Ähnliches oder eine Kombination daraus sein. Die Wärmesenke502 kann eine Metallplatte sein. Beispielhafte Materialien für die Metallplatte sind Kupfer, nickelplattiertes Kupfer, Aluminium, Ähnliches oder eine Kombination daraus. Die Wärmesenke502 kann im Allgemeinen eine gute Wärmeleitfähigkeit und/oder einen Wärmeausdehnungskoeffizienten (CTE) haben der mit dem CTE der Dies110 vergleichbar ist. Die Wärmesenke502 führt üblicherweise Wärme ab, wenn sie in dem fertiggestellten Package ist. -
10 zeigt das Anbringen des Die-Packages an einem Substrat602 (Schritt718 ). Das Substrat602 kann aus einem Halbleitermaterial hergestellt sein wie Silizium, Germanium, Diamant oder Ähnlichem. Alternativ können Verbindungsmaterialien wie Silizium-Germanium, Siliziumkarbid, Galliumarsenid, Indiumarsenid, Indiumphosphid, Silizium-Germanium-Karbid, Galliumarsenid-Phosphid, Gallium-Indium-Phosphid, Kombinationen daraus und Ähnliches auch verwendet werden. Zusätzlich kann das Substrat102 ein SOI-Substrat sein. Im Allgemeinen umfasst ein SOI-Substrat eine Schicht aus einem Halbleitermaterial wie epitaktischem Silizium, Germanium, Silizium-Germanium, SOI, SGOI oder Kombinationen daraus. Das Substrat602 basiert in einer alternativen Ausführungsform auf einem isolierenden Kern, etwa einem glasfaserverstärkten Harz-Kern. Ein beispielhaftes Kernmaterial ist Glasfaser-Harz, etwa FR4. Alternativen für das Kernmaterial umfassen BT-Harz oder alternativ andere Platinen-Materialien oder -Filme. Aufbau-Filme wie ABF oder andere Laminate können für das Substrat602 verwendet werden. - Das Substrat
602 kann aktive und passive Vorrichtungen umfassen (in10 nicht gezeigt). Wie ein Fachmann erkennen wird, können eine breite Vielfalt von Vorrichtungen wie Transistoren, Kondensatoren, Widerständen, Kombinationen daraus und Ähnlichem verwendet werden, um die strukturellen und funktionalen Anforderungen des Designs für das Substrat602 zu erzeugen. Die Vorrichtungen können durch jedes geeignete Verfahren ausgebildet werden. In einigen Ausführungsformen ist das Substrat602 ein Package-Substrat. - Das Substrat
602 umfasst Bondkontaktstellen606 auf einer ersten Seite des Substrats602 und elektrische Anschlussteile604 auf einer zweiten Seite des Substrats, wobei die zweite Seite der ersten Seite gegenüberliegt. Die Bondkontaktstellen606 und die elektrischen Anschlussteile604 können den Bondkontaktstellen108 bzw. den elektrischen Anschlussteilen408 ähneln, die oben beschrieben sind, und die Beschreibungen werden hier nicht wiederholt, obwohl die Bondkontaktstellen108 und606 und die elektrischen Anschlussteile408 und604 nicht identisch sein müssen. - Das Bonden zwischen dem Die-Package und dem Substrat
602 kann ein Lot-Bonden oder ein direktes Metall-Metall-Bonding (etwa Kupfer-Kupfer oder Zinn-Zinn) sein. In einer Ausführungsform wird das Die-Package mit dem Substrat602 durch ein Aufschmelzverfahren gebondet. Während dieses Aufschmelzverfahrens sind die elektrischen Anschlussteile408 in Kontakt mit den Metallisierungsstrukturen406 und den Bondkontaktstellen606 , um das Die-Package mit dem Substrat602 körperlich und elektrisch zu verbinden. - Ein Unterfüllungsmaterial
608 kann in den Zwischenraum zwischen dem Die-Package und dem Substrat602 und die elektrischen Anschlussteile408 umgebend eingespritzt oder anderweitig in ihm ausgebildet werden. Das Unterfüllungsmaterial608 kann beispielsweise ein flüssiges Epoxid, ein verformbares Gel, Silizium-Kautschuk oder Ähnliches sein, das zwischen die Strukturen eingebracht wird und dann ausgehärtet wird, um hart zu werden. Dieses Unterfüllungsmaterial wird unter anderem verwendet, um Schäden an den elektrischen Anschlussteilen408 zu verringern und sie zu schützen. - Indem eine Isolierschicht auf einem Die (etwa der Rückseite eines Dies) während eines Bondhügel-Ausbildungsverfahrens bereitgestellt wird, kann der Weg, durch den statische Elektrizität empfindliche Komponenten erreichen und beschädigen kann, wesentlich verringert werden oder vollständig fehlen. Als solches kann das Verfahrensfenster zur Herstellung von CoWoS-Vorrichtungen erweitert werden, was Herstellungskosten und - Komplexität senkt, während es den Ertrag des Verfahrens erhöht.
- Während dem Ausbilden einer zweiten Seite eines Substrats (z.B. dem Ausbilden der dielektrischen Schichten, Metallisierungsstrukturen und/oder elektrischen Anschlussteile) können die Dies, die an dem Substrat befestigt sind, das Substrat selbst und die elektrischen Anschlussteile beispielsweise positiv aufgeladen werden, während ein Träger-Substrat (an der Rückseite der Dies befestigt) negativ geladen werden kann oder umgekehrt. Daher kann die Grenzfläche zwischen den Dies
110 und dem Träger-Substrat ein elektrostatischer Entladungsweg sein. Indem eine Menge an Formmasse belassen wird, die die rückseitigen Oberflächen der Dies bedeckt, bildet die Formmasse eine Isolierschicht, die den elektrostatischen Entladungsweg zwischen den Dies und dem Träger-Substrat blockiert. - Eine Ausführungsform besteht aus einem Verfahren, das das Anbringen eines Dies an einer oberen Fläche eines Substrats umfasst, um eine Vorrichtung auszubilden, das Kapseln des Dies und der oberen Fläche des Substrats in einer Formmasse, wobei die Formmasse eine erste Dicke über dem Die aufweist, und das Entfernen eines Teils, aber nicht der gesamten Dicke der Formmasse über dem Die. Das Verfahren umfasst die weitere Verarbeitung der Vorrichtung und das Entfernen der verbleibenden Dicke der Formmasse über dem Die.
- Eine weitere Ausführungsform besteht aus einem Verfahren, das das Anbringen einer aktiven Oberfläche eines ersten Dies an einer ersten Seite eines ersten Substrats umfasst, um ein Die-Package auszubilden, das Kapseln des ersten Dies und der ersten Seite des Substrats mit einer Formmasse, wobei die Formmasse eine erste Dicke von einer ersten Oberfläche der Formmasse zu einer rückseitigen Oberfläche des ersten Dies hat, wobei die rückseitige Oberfläche der aktiven Oberfläche gegenüberliegt, und das Anwenden eines ersten Planarisierungsschritts auf die erste Oberfläche der Formmasse, so dass sie eine zweite Dicke von der ersten Oberfläche der Formmasse zu der rückseitigen Oberfläche des ersten Dies hat, wobei die zweite Dicke kleiner als die erste Dicke ist. Das Verfahren umfasst weiter das Anbringen der ersten Oberfläche der Formmasse an einem Träger-Substrat, das Ausbilden eines elektrischen Anschlussteils über einer zweiten Seite des ersten Substrats, das Entfernen des Träger-Substrats und das Anwenden eines zweiten Planarisierungsschritts auf die erste Oberfläche der Formmasse, um die verbleibende Formmasse über der rückseitigen Oberfläche des ersten Dies zu entfernen.
- Eine weitere Ausführungsform besteht aus einem Verfahren, das das Anbringen eines Dies an einer ersten Oberfläche eines ersten Substrats umfasst, um ein Vorrichtungs-Package auszubilden, das Kapseln des Dies und der ersten Oberfläche des ersten Substrats mit einer Formmasse, wobei die Formmasse sich über den Die erstreckt, und das Entfernen eines Teils der Formmasse, der sich über den Die erstreckt. Das Verfahren umfasst die weitere Verarbeitung des Vorrichtungs-Packages und das Entfernen des verbleibenden Teils der Formmasse über dem Die, um eine Oberfläche des Dies freizulegen.
Claims (20)
- Verfahren, das Folgendes umfasst: Anbringen eines Dies (110) an einer oberen Fläche eines Substrats (202), um eine Vorrichtung auszubilden; Kapseln des Dies (110) und der oberen Fläche des Substrats (202) in einer Formmasse (304), wobei die Formmasse (304) eine erste Dicke über dem Die aufweist; Entfernen eines Teils, aber nicht der gesamten Dicke der Formmasse (304) über dem Die (110), um eine die verbleibende Dicke der Formmasse und eine plane obere Oberfläche der Formmasse bereitzustellen; weitere Verarbeitung der Vorrichtung; und Entfernen der verbleibenden Dicke der Formmasse (304) über dem Die (110).
- Verfahren nach
Anspruch 1 , wobei die weitere Verarbeitung das Ausbilden eines elektrischen Anschlussteils auf einer unteren Fläche des Substrats (202) umfasst. - Verfahren nach
Anspruch 2 , wobei das elektrische Anschlussteil eine Flip-Chip-Verbindung ist. - Verfahren nach einem der vorhergehenden Ansprüche, wobei die weitere Verarbeitung das Zurückschleifen einer unteren Fläche des Substrats (202) und das Ausbilden eines elektrischen Anschlussteils (408) auf der zurückgeschliffenen Oberfläche umfasst.
- Verfahren nach einem der vorhergehenden Ansprüche, das weiter das Anbringen der Vorrichtung an einem zweiten Substrat (402) umfasst.
- Verfahren nach
Anspruch 5 , wobei das zweite Substrat (402) eine Leiterplatte ist. - Verfahren nach einem der vorhergehenden Ansprüche, wobei nach dem Entfernen des Teils, aber nicht der gesamten Dicke der Formmasse (304) über dem Die (110) die verbleibende Dicke der Formmasse (304) größer als 30 µm ist.
- Verfahren nach einem der vorhergehenden Ansprüche, das weiter Folgendes umfasst: Nach dem Entfernen der verbleibenden Dicke der Formmasse (304) über dem Die (110), Verbinden einer Wärmesenke mit dem Die (110) und der Formmasse (304).
- Verfahren nach einem der vorhergehenden Ansprüche, wobei nach dem Entfernen der verbleibenden Dicke der Formmasse (304) über dem Die (110), der Die (110) und die Formmasse (304) Oberflächen aufweisen, die koplanar sind, die Oberflächen gegenüber dem Substrat distal sind.
- Verfahren, das Folgendes umfasst: Anbringen einer aktiven Oberfläche eines ersten Dies (110) an einer ersten Seite eines ersten Substrats (202), um ein Die-Package auszubilden; Kapseln des ersten Dies (110) und der ersten Seite des ersten Substrats (202) mit einer Formmasse (304), wobei die Formmasse (304) eine erste Dicke von einer ersten Oberfläche der Formmasse (304) zu einer rückseitigen Fläche des ersten Dies (110) aufweist, wobei die rückseitige Fläche der aktiven Oberfläche gegenüberliegt; Anwenden eines ersten Planarisierungsschritts auf die erste Oberfläche der Formmasse (304), so dass sie eine zweite Dicke von der ersten Oberfläche der Formmasse (304) zu der rückseitigen Fläche des ersten Dies (110) aufweist, wobei die zweite Dicke kleiner als die erste Dicke ist; Anbringen der ersten Oberfläche der Formmasse (304) an einem Träger-Substrat (402); Ausbilden eines elektrischen Anschlussteils (408) über einer zweiten Seite des ersten Substrats (202); Entfernen des Träger-Substrats (402); und Anwenden eines zweiten Planarisierungsschritts auf die erste Oberfläche der Formmasse (304), um die verbleibende Formmasse über der rückseitigen Fläche des ersten Dies (110) zu entfernen.
- Verfahren nach
Anspruch 10 , das weiter Folgendes umfasst: Ausbilden einer ersten Durchkontaktierung (206), die sich von der ersten Seite des ersten Substrats (202) in das erste Substrat erstreckt, wobei der erste Die (110) mit einem ersten Ende der ersten Durchkontaktierung (206) elektrisch verbunden ist und das elektrische Anschlussteil mit einem zweiten Ende der Durchkontaktierung (206) verbunden ist. - Verfahren nach
Anspruch 10 , das weiter Folgendes umfasst: vor dem Anwenden des zweiten Planarisierungsschritts auf die erste Oberfläche der Formmasse (304), Ausbilden eines Schutzfilms (420) über dem elektrischen Anschlussteil (408) und über der zweiten Seite des ersten Substrats (202). - Verfahren nach
Anspruch 12 , wobei der Schutzfilm (420) ein Backgrinding-Band ist. - Verfahren nach einem der
Ansprüche 10 bis13 , das weiter Folgendes umfasst: Anbringen des Die-Packages an einem zweiten Substrat (402) mittels des elektrischen Anschlussteils (408). - Verfahren nach einem der
Ansprüche 10 bis14 , das weiter Folgendes umfasst: Ausbilden einer Unterfüllung (302) zwischen der aktiven Oberfläche des ersten Dies (110) und der ersten Seite des ersten Substrats (202), wobei eine Seitenwand der Unterfüllung (302) direkt an die Formmasse (304) angrenzt. - Verfahren nach einem der
Ansprüche 10 bis15 , wobei nach dem Anwenden des zweiten Planarisierungsschritts auf die erste Oberfläche der Formmasse (304) die erste Oberfläche der Formmasse (304) und die rückseitige Fläche des ersten Dies (110) koplanar sind. - Verfahren nach einem der
Ansprüche 10 bis16 , das weiter das Anbringen einer aktiven Oberfläche eines zweiten Dies (110) an der ersten Seite des ersten Substrats (202) umfasst, um das Die-Package auszubilden, wobei der zweite Die seitlich an den ersten Die angrenzt, wobei nach dem Anwenden des zweiten Planarisierungsschritts auf die erste Oberfläche der Formmasse (304) ein Teil der Formmasse (304) zwischen dem ersten Die (110) und dem zweiten Die (110) verbleibt. - Verfahren, das Folgendes umfasst: Anbringen eines Dies (110) an einer ersten Oberfläche eines ersten Substrats (202), um ein Vorrichtungs-Package auszubilden; Kapseln des Dies (110) und der ersten Oberfläche des ersten Substrats (202) mit einer Formmasse (304), wobei die Formmasse (304) sich über den Die erstreckt; Entfernen eines Teils der Formmasse (304), der sich über den Die (110) erstreckt, um eine die verbleibende Dicke der Formmasse (304) und eine plane obere Oberfläche der Formmasse bereitzustellen; weitere Verarbeitung des Vorrichtungs-Packages; und Entfernen des verbleibenden Teils der Formmasse (304) über dem Die (110), um eine Oberfläche des Dies (110) freizulegen.
- Verfahren nach
Anspruch 18 , wobei die weitere Verarbeitung Folgendes umfasst: Anbringen des Vorrichtungs-Packages an einem Träger-Substrat (402), wobei die Formmasse (304) das Träger-Substrat (402) von dem Die (110) trennt; Ausbilden eines leitenden Bondhügels (408) auf einer zweiten Oberfläche des ersten Substrats (202), wobei die zweite Oberfläche der ersten Oberfläche gegenüberliegt; Entfernen des Träger-Substrats (402); und Aufbringen eines Backgrinding-Bands (420) über dem leitenden Bondhügel (408) und der zweiten Oberfläche des ersten Substrats (202), wobei das Backgrinding-Band (420) über dem leitenden Bondhügel (408) liegt, während der verbleibende Teil der Formmasse (304) über dem Die (110) entfernt wird, um die Oberfläche des Dies (110) freizulegen. - Verfahren nach
Anspruch 19 , das weiter das Anbringen des Vorrichtungs-Packages an einem zweiten Substrat (602) mittels des leitenden Bondhügels (408) umfasst.
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US14/276,832 US9209048B2 (en) | 2013-12-30 | 2014-05-13 | Two step molding grinding for packaging applications |
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US20130134559A1 (en) | 2011-11-30 | 2013-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-Wafer Structures and Methods for Forming the Same |
US20130147054A1 (en) | 2011-12-08 | 2013-06-13 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP |
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