CN107342232A - 晶片封装体的形成方法 - Google Patents
晶片封装体的形成方法 Download PDFInfo
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- CN107342232A CN107342232A CN201710170781.2A CN201710170781A CN107342232A CN 107342232 A CN107342232 A CN 107342232A CN 201710170781 A CN201710170781 A CN 201710170781A CN 107342232 A CN107342232 A CN 107342232A
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Abstract
本揭露提供了一种晶片封装体的形成方法。方法包括于承载基底之上形成数个导电结构,及于承载基底之上设置半导体晶片。方法还包括于承载基底之上设置模子。方法更包括于模子与承载基底之间形成保护层来围绕半导体晶片及导电结构。此外,方法包括移除模子。
Description
技术领域
本揭露书系有关于半导体技术,且特别是有关于晶片封装技术。
背景技术
半导体积体电路工业已经历快速成长。半导体制备工艺的持续进步以促使半导体元件具有更精细的结构及/或更高程度的集成密度。随着特征尺寸(feature size)(即,使用工艺所能制造的最小构件)的缩减,使得功能性密度(即,单位晶片面积中彼此相连的元件的数量)已随之增加。此尺寸缩小化的工艺借着增进生产效率与降低相关成本而提供好处。
晶片封装体除了保护半导体元件免受环境污染外,还对封装其内的半导体元件提供连接界面(connection interface)。一种用于封装半导体元件的较小型式的封装体为晶片尺度封装体(chip-scale package,CSP),其中于基底上设置有半导体晶片(或称半导体晶粒,semiconductor die)。
已发展新的封装技术来进一步增进半导体晶片的密度与功能。这些用于半导体晶片的相对新颖的封装技术面临着制作上的挑战。
发明内容
本揭露书的实施例提供一种形成晶片封装体的方法,包括:于一承载基底之上形成多个导电结构;于该承载基底之上设置一半导体晶片;于该承载基底之上设置一模子;于该模子与该承载基底之间形成一保护层,以围绕该半导体晶片与该些导电结构;以及移除该模子。
本揭露书的实施例提供一种晶片封装体的形成方法,包括:于一承载基底之上形成多个导电结构;切除该些导电结构的较上部分,使得该些导电结构的顶表面大抵彼此共平面;于该承载基底之上设置一半导体晶片;以及该承载基底之上形成一保护层以围绕该些导电结构与该半导体晶片,
本揭露书的实施例提供一种晶片封装体,包括:一半导体晶片;一保护层,其包覆该半导体晶片;以及一导电结构,位于该保护层之中,且借着该保护层而与该半导体晶片隔离,其中保护层具有一凹陷,其介于该半导体晶片与该导电结构之间。
附图说明
图1A-1L显示根据一些实施例的晶片封装体的数阶段制备工艺剖面图。
图2A-1、2B-1、及2C-1显示根据一些实施例的晶片封装体的数阶段制备工艺剖面图。
图2A-2、2B-2、及2C-2显示根据一些实施例的晶片封装体的数阶段制备工艺上视图。
图3A-3B显示根据一些实施例的晶片封装体的数阶段制备工艺剖面图。
其中,附图标记说明如下:
100~承载基底;
102~黏着层;
104~基层;
106~晶种层;
108~遮罩层;
110~开口;
112A、112B、112C、112D~导电结构;
114~半导体基底;
115~切割工具;
116~介电层;
118~导电垫;
120~黏着膜;
122、122A、122B~半导体晶片;
124~保护层;
126~凹陷;
128~内连线结构;
130~导电凸块;
132~构件;
134~连接构件;
200~模子;
201~密封构件;
202~离型膜;
204~模塑化合物材料;
206~开口;
230~空间;
D~深度;
H1、H2、H3、H4、H5、H6、H7~高度;
ΔH~高度差;
L~假想线。
具体实施方式
以下的揭露内容提供许多不同的实施例或范例,以实施本案的不同特征。而本揭露书以下的揭露内容是叙述各个构件及其排列方式的特定范例,以求简化说明。当然,这些特定的范例并非用以限定。例如,若是本揭露书以下的内容叙述了将一第一特征形成于一第二特征之上或上方,即表示其包含了所形成的上述第一特征与上述第二特征是直接接触的实施例,亦包含了尚可将附加的特征形成于上述第一特征与上述第二特征之间,而使上述第一特征与上述第二特征可能未直接接触的实施例。再者,在以下叙述提及在第二工艺前进行第一工艺,可包括第二工艺于第一工艺之后立刻进行的实施例,且亦可包括附加工艺于第一工艺与第二工艺之间进行的实施例。另外,本揭露书中不同范例可能使用重复的参考符号及/或标记。这些重复系为了简化与清晰的目的,并非用以限定各个实施例及/或所述外观结构之间的关系。
再者,为了方便描述图式中一元件或特征部件与另一(多)元件或(多)特征部件的关系,可使用空间相关用语,例如“在…之下”、“下方”、“较下部”、“上方”、“较上部”及类似的用语等。除了图式所绘示的方位之外,空间相关用语用以涵盖使用或操作中的装置的不同方位。所述装置也可被另外定位(例如,旋转90度或者位于其他方位),并对应地解读所使用的空间相关用语的描述。
本揭露书的一些实施例叙述如下。可于这些实施例中所述的步骤之前、期间、及/或之后进行其他附加的处理。所叙述的一些步骤可在不同的实施例中被置换或排除。可于半导体元件结构中增加附加的构件。以下所述的一些构件,可于不同的实施例中被置换或排除。虽然,所叙述的一些实施例系具有特定的处理顺序,然而这些处理亦可改以其他符合逻辑的顺序进行。
图1A-1L显示根据一些实施例的晶片封装体的数个阶段制备工艺剖面图。如图1A所示,根据一些实施例,于承载基底100之上沉积或贴合黏着层102及基层104。在一些实施例中,承载基底100系用作暂时性支撑基底(temporary support substrate)。承载基底100可由半导体材料、陶瓷材料、高分子材料、金属材料、其他适合的材料、或前述的组合所制成。在一些实施例中,承载基底100为玻璃基底。在一些其他实施例中,承载基底100为半导体基底,例如是硅晶圆(silicon wafer)。
黏着层102可由黏胶(glue)所制成,或可由贴合材料(lamination material)所制成,例如是箔(foil)。在一些实施例中,黏着层102具光敏性(photosensitive),且可借着照光而轻易地自承载基底100分离。例如,于承载基底100照射紫外光或雷射光可用以脱除黏着层102。在一些实施例中,黏着层102为光热转换层(light-to-heat-conversion(LTHC)coating)。在一些其他实施例中,黏着层102为热敏性(heat-sensitive)。可借着使用热处理来脱除黏着层102。
在一些实施例中,基层104为高分子层或含高分子的材料层。基层104可为聚苯恶唑(polybenzobisthiazole,PBO)层、聚亚酰胺(polyimide,PI)层、防焊(solder resist,SR)层、增层绝缘膜(ABF)、晶粒黏贴膜(die attach film,DAF)、其他适合的材料层、或前述的组合。在一些实施例中,基层104包括数个子层(sub-layers)。在一些其他实施例中,未形成基层104。
之后,如图1A所示,根据一些实施例,于基层104之上沉积晶种层(seed layer)106。在一些实施例中,晶种层106系由金属材料(例如是铜)所制成。在一些实施例中,晶种层106借着使用物理气相沉积(physical vapor deposition,PVD)工艺、化学气相沉积(chemical vapor deposition,CVD)工艺、旋涂工艺(spin-on process)、其他可应用的工艺、或前述的组合而沉积。然而,本揭露书的实施例不限于此。亦可使用其他的导电膜作为晶种层106。例如,晶种层106可由钛(Ti)、钛合金(Ti alloy)、铜(Cu)、铜合金(Cu alloy)、其他适合的材料、或前述的组合所制成。钛合金或铜合金可包括银(silver)、铬(chromium)、镍(nickel)、锡(tin)、金(gold)、钨(tungsten)、其他适合的元素、或前述的组合。在一些实施例中,晶种层106包括数个子层。
可对本揭露书的实施例做出许多的改变及/或修饰。在一些其他实施例中,未形成晶种层106。
如图1B所示,根据一些实施例,于晶种层106a之上形成遮罩层(mask layer)108。遮罩层108数个开口110,其露出部分的晶种层106。遮罩层108的开口110定义出所将形成的导电结构(例如,穿封装导电结构,through package vias)的位置。在一些实施例中,遮罩层108系由光阻材料所制成。遮罩层108的开口110可借着微影工艺(photolithographyprocess)而形成。微影工艺可包括曝光及显影处理(exposure and developmentoperations)。
如图1C所示,根据一些实施例,于遮罩层108的开口110中形成导电结构,其包括导电结构112A、112B、112C、及112D。在一些实施例中,每一导电结构112A、112B、112C、及112D具有线形的侧壁(linear sidewall)。在一些实施例中,导电结构112A、112B、112C、及112D的侧壁大抵垂直于晶种层106的表面。在一些实施例中,每一导电结构112A、112B、112C、及112D的上视图为大抵圆形。在一些实施例中,导电结构112A、112B、112C、及112D的宽度大抵相同。在一些其他实施例中,一些导电结构112A、112B、112C、及112D的宽度系彼此不同。
在一些实施例中,导电结构112A、112B、112C、及112D系由金属材料所制成。金属材料可包括铜(Cu)、钛(Ti)、金(Au)、钴(Co)、铝(Al)、钨(W)、其他适合的材料、或前述的组合。在一些实施例中,导电结构112A、112B、112C、及112D系由包含锡(Sn)的焊料材料(soldermaterial)所制成。在一些其他实施例中,导电结构112A、112B、112C、及112D系由不包含锡的金属材料所制成。
在一些实施例中,导电结构112A、112B、112C、及112D系使用镀工艺(platingprocess)而形成。镀工艺可包括电镀工艺(electroplating process)、无电镀工艺(electroless plating process)、其他可应用的工艺、或前述的组合。然而,可对本揭露书的实施例做出许多的改变及/或修饰。在一些其他实施例中,导电结构112A、112B、112C、及112D系使用化学气相沉积(CVD)工艺、物理气相沉积(PVD)工艺、旋涂工艺(spin-onprocess)、其他可应用的工艺、或前述的组合而形成。
如图1C所示,导电结构112A、112B、112C、及112D分别具有高度H1、H2、H3、及H4。在一些实施例中,高度H1、H2、H3、及H4系大抵相同。在一些实施例中,高度H1、H2、H3、及H4中的一些系彼此不同,如图1C所示。
如图1D所示,根据一些实施例,使用切割工具(cutting too)115来切除导电结构112A、112B、112C、及112D的较上部分。将以切割工具115来切除导电结构112A、112B、112C、及112D的位于假想线(imaginary line)L上的较上部分。可将假想线L设置在使得每一导电结构112A、112B、112C、及112D在被切割后能够具有高度H5的位置。在一些实施例中,将遮罩层108的位于假想线L上的较上部分及导电结构112A、112B、112C、及112D的较上部分一起借着使用切割工具115而切除。
如图1E所示,根据一些实施例,在切割处理(cutting operation)之后,导电结构112A、112B、112C、及112D的顶表面系大抵彼此共平面。每一导电结构112A、112B、112C、及112D具有高度H5。在一些实施例中,由于切割处理,原本具有不同高度的导电结构112A、112B、112C、及112D具有大抵相同的高度。
即使导电结构112A、112B、112C、及112D不具有相同的高度,切割处理允许导电结构112A、112B、112C、及112D具有大抵相同的高度。导电结构112A、112B、112C、及112D的顶表面大抵共平面,其有助于后续的工艺。在一些情形中,用以形成导电结构112A、112B、112C、及112D的镀工艺可不需非常完美地控制。在一些实施例中,以相对快的速度进行镀工艺。在一些实施例中,镀工艺使用不非常昂贵的镀液(plating solution)。因此,显著地减少了工艺成本与时间。
如图1F所示,根据一些实施例,移除遮罩层108。之后,如图1F所示,根据一些实施例,将未被导电结构(包括112A、112B、112C、及112D)覆盖的晶种层106移除。可使用蚀刻工艺以部分移除晶种层106。包括112A、112B、112C、及112D的导电结构在蚀刻晶种层106期间,可用作蚀刻遮罩。
如图1G所示,根据一些实施例,将半导体晶片(semiconductor dies)(包括半导体晶片122A及122B)贴合至基层104之上。在一些实施例中,半导体晶片122A及122B的背侧(back sides)面向基层104,而半导体晶片122A及122B的前侧(front sides)系面朝上。可使用黏着膜(adhesive film)120而将半导体晶片122A及122B固定在基层104之上。黏着膜120可包括晶片贴合膜(DAF)、黏胶、或其他适合的薄膜。
每一半导体晶片122A及122B可包括半导体基底114、介电层116、及位于半导体晶片的前侧上的导电垫118。在一些实施例中,半导体基底114中形成有数种元件构件(deviceelements)。数种元件构件例如包括电晶体(例如,金氧半场效电晶体(MOSFET)、互补式金氧半场效电晶体(CMOS)、双极性接面电晶体(BJT)、高电压电晶体、高频率电晶体、P通道及/或N通道场效电晶体(PFETs/NFETs)等等)、二极体、其他可应用元件、或前述的组合。
元件构件通过形成在介电层116中的导电部件(conductive features)而彼此内连形成积体电路元件(integrated circuit devices)。介电层116可包括多个子层。导电部件可包括多个导电线路(conductive lines)、导电接触(conductive contacts)、及导电通孔塞(conductive vias)。体电路元件例如包括逻辑元件、记忆体元件(例如,静态随机存取记忆体(SRAM)及/或动态随机存取记忆体(DRAM))、射频(RF)元件、输入/输出(I/O)元件、单晶片系统(system-on-chip,SoC)元件、其他可应用元件、或前述的组合。在一些实施例中,半导体晶片122A或122B为单晶片系统(SoC)晶片,其包括多重功能。
导电垫118可为形成在介电层116之上或镶嵌在介电层116中的一些导电线路的较宽部分。因此,半导体基底114中的元件构件可通过导电垫118与其他导电部件而电性连接至其他构件。
如图1G所示,晶种层106与每一导电结构112A、112B、112C、及112D共同具有总高度H6。黏着膜120与每一半导体晶片122A及122B共同具有总高度H7。在一些实施例中,高度H6及H7大抵相同。
然而,可对本揭露书的实施例做出许多的改变及/或修饰。在一些实施例中,高度H6及H7系彼此不同。在一些实施例中,高度H6大于高度H7。在一些实施例中,其中一导电结构112A、112B、112C、及112D与其中一半导体晶片122A及122B之间的高度差大抵相同于高度H6及H7之间的差异。在一些实施例中,高度差介于约2微米至约3微米之间。
如图1H所示,根据一些实施例,于承载基底100之上形成保护层(protectionlayer)124以围绕导电结构112A、112B、112C、及112D和半导体晶片122A及122B。在一些实施例中,保护层124覆盖导电结构112A、112B、112C、及112D的侧壁和半导体晶片122A及122B的侧壁。在一些实施例中,保护层124未覆盖导电结构112A、112B、112C、及112D的顶表面和半导体晶片122A及122B的顶表面。在一些实施例中,导电结构112A、112B、112C、及112D穿过保护层124。导电结构112A、112B、112C、及112D系用作穿封装导电结构。在一些实施例中,保护层124包括高分子材料。在一些实施例中,保护层124包括模塑化合物材料(moldingcompound material)。
在一些实施例中,保护层124系借着于承载基底100上注入模塑化合物材料而形成。在一些实施例中,在注入模塑化合物材料之后或期间,模塑化合物材料未覆盖导电结构112A、112B、112C、及112D的顶表面及/或半导体晶片122A及122B的顶表面。
在一些实施例中,将液态模塑化合物材料设置于承载基底100之上以包覆导电结构112A、112B、112C、及112D和半导体晶片122A及122B。在一些实施例中,接着采取热工艺(thermal process)以硬化液态模塑化合物材料,并将之转化为保护层124。在一些实施例中,热工艺系于温度介于约摄氏200度至约摄氏230度下进行。热工艺的进行时间可介于约0.5小时至约3小时。
在一些实施例中,使用模子(mold)来辅助形成保护层124。图2A-1、2B-1、及2C-1显示根据一些实施例形成晶片封装体的保护层124的数个阶段工艺剖面图。图2A-2、2B-2、及2C-2显示根据一些实施例形成晶片封装体的保护层124的数个阶段工艺上视图。
如图2A-1所示,根据一些实施例,于承载基底100之上设置模子(mold)200。在一些实施例中,空间(space)230系形成在模子200与承载基底100之间,如图2A-1所示。在一些实施例中,模子200包括密封构件(sealing element)201。密封构件201可用以覆盖承载基底100的周边区域(peripheral region)。在一些实施例中,密封构件201为密封环(sealingring)。密封构件201亦可用作固定构件(settle element),其将承载基底100固定在模子200之下。
然而,可对本揭露书的实施例做出许多的改变及/或修饰。在一些其他实施例中,未形成密封构件201。
在一些实施例中,模子200包括离型膜(release film)202。空间230系由承载基底100、密封构件201、及离型膜202所围绕。在一些实施例中,离型膜202的材质对用以形成保护层124的模塑化合物材料具有低黏着性。在一些实施例中,在将模子200设置在承载基底100之上后,离型膜202直接接触导电结构112A、112B、112C、及112D。在一些实施例中,离型膜202还直接接触半导体晶片122A及122B。
然而,可对本揭露书的实施例做出许多的改变及/或修饰。在一些其他实施例中,未形成离型膜202。
在一些实施例中,模子200具有一或更多个开口206。每一开口206可用以允许模塑化合物材料204的流体注入模子200之中。在一些实施例中,一或更多个开口206系用以允许模塑化合物材料204被导出模子200。在一些实施例中,每一开口206系用以使模塑化合物材料204导入模子200之中。在一些其他实施例中,模子200仅具有一开口206,其允许模塑化合物材料204的流体进入空间230之中。
如图2A-2所示,根据一些实施例,将数个半导体晶片122设置在承载基底100之上。如图2A-1及2A-2所示,根据一些实施例,在此阶段,尚无模塑化合物材料被注射在承载基底100之上。
之后,如图2B-1及2B-2所示,根据一些实施例,于模子200与承载基底100之间的空间230注入模塑化合物材料204。如图2B-1所示,根据一些实施例,一些导电结构(包括导电结构112A及112D被模塑化合物材料204所围绕。如图2B-1及图2B-2所示,根据一些实施例,一些半导体晶片122(包括半导体晶片122A及122B)被模塑化合物材料204部分围绕或完全围绕。在一些实施例中,在注入模塑化合物材料204期间,离型膜202直接接触导电结构112A、112B、112C、及112D。在一些实施例中,在注入模塑化合物材料204期间,离型膜202亦直接接触半导体晶片122(包括半导体晶片122A及122B)。
之后,如图2C-1及图2C-2所示,根据一些实施例,所注入的模塑化合物材料204完全填充模子200与承载基底100之间的空间230。在一些实施例中,移除模子200,并将模塑化合物材料204固化而成为保护层124,如图1H所示。在一些实施例中,模塑化合物材料204系在移除模子200之后才固化。在一些其他实施例中,模塑化合物材料204系在移除模子200之前固化。
在一些实施例中,由于有模子200在,在注入模塑化合物材料204以形成保护层124期间,模塑化合物材料204不覆盖导电结构112A、112B、112C、及112D的顶表面及/或半导体晶片122A及122B的顶表面。因此,导电结构112A、112B、112C、及112D的顶表面和半导体晶片122A及122B的顶表面不被保护层124覆盖,如图1H所示。在一些实施例中,由于导电结构112A、112B、112C、及112D和半导体晶片122A及122B的导电垫118系露出而未被保护层124所覆盖,因此不需将保护层124薄化。
在一些其他情形中,未使用模子200。在这些情形中,导电结构及半导体晶片受到模塑化合物材料的覆盖。之后,可能需要进行薄化工艺来薄化保护层,从而露出导电结构及半导体晶片。可能需于每一半导体晶片上预先另外形成足以承受薄化工艺的钝化层(例如,PBO层)及导电柱(conductive pillars),以确保连至半导体晶片的导电路径。因此,制作成本及工艺时间皆高。
在使用模子的一些实施例中,由于不需对保护层124进行薄化工艺,制作成本及工艺时间皆可减少。亦可避免由薄化工艺所造成的损伤。在一些实施例中,不需于半导体晶片上另外形成钝化层及导电柱,使得制作成本及工艺时间更进一步地缩减。
在一些实施例中,离型膜202与模塑化合物材料204之间的黏着性是弱的。在移除模子200之后,可能在模塑化合物材料204的表面形成出凹陷。因此,亦有一些凹陷126形成在保护层124的表面。如图1H所示,根据一些实施例,保护层124具有凹陷126。一些凹陷126系介于半导体晶片122A或122B与其中一导电结构112A、112B、112C、及112D之间。一些凹陷126系介于两导电结构之间,例如介于导电结构112B与112C之间。如图1H所示,其中一凹陷126具有深度D。在一些实施例中,深度D介于约3微米至约10微米之间。例如,深度D可为约7微米。
如图1I所示,根据一些实施例,于显示于图1H的形成内连线结构(interconnection structure)128。内连线结构128可包括数层介电层及数个导电部件(未显示)。数层介电层可包括高分子层、氧化硅层、其他适合的材料层、或前述的组合。数个导电部件可包括导电线路及导电通孔塞。一些导电部件电性连接至导电结构112A、112B、112C、或112D或半导体晶片122A或122B的导电垫118。内连线结构128的形成可涉及数道沉积工艺、数道图案化工艺、及数道平坦化工艺。
之后,如图1I所示,根据一些实施例,于内连线结构128之上形成导电凸块(conductive bumps)130。可于导电凸块130之下形成凸块下金属化(under bumpmetallurgy,UBM)层(未显示)。每一导电凸块130可通过内连线结构128中的一些导电部件而电性连接至导电结构112A、112B、112C、112D或半导体晶片122A或122B的导电垫118。在一些实施例中,导电凸块130包括焊料凸块(solder bumps)、金属柱(metal pillars)、具有线型的侧壁(linear sidewalls)的金属柱、不包含锡的金属柱、其他适合的导电结构、或前述的组合。
在一些实施例中,在移除模子200之后及形成内连线结构128之前,保护层124和导电结构112A、112B、112C、及112D未经平坦化。在一些实施例中,在形成内连线结构128之前,保护层124未经薄化。因此,可避免平坦化工艺或薄化工艺所造成的损伤。增进了晶片封装体的可靠度及效能。可减少制作成本及工艺时间。
之后,如图1J所示,根据一些实施例,移除承载基底100及黏着层102。在一些实施例中,使用照光处理来将承载基底100及黏着层102自基层104移除。
如图1K所示,根据一些实施例,于图1J所示的结构之上堆迭其他构件(elements)132。构件132可包括晶片封装体、半导体晶片、被动元件、其他适合的结构、或前述的组合。在一些实施例中,于构件132与导电结构(例如,导电结构112A、112B、112C、及112D)之间形成连接构件(connectors)134。可因此建立构件132与半导体晶片122A及/或122B之间的电性连接。
如图1L所示,根据一些实施例,进行切割工艺以将如图1K所示的结构分离成数个晶片封装体(图1L显示其中之一)。因此,形成了具有扇出型结构(fan-out structure)的晶片封装体。在一些其他实施例中,如图1K所示,在切割工艺之前,可于结构上堆迭或接合更多的构件。
可对本揭露书的实施例做出许多的改变及/或修饰。图3A-3B显示根据一些实施例的晶片封装体的数个阶段制备工艺剖面图。
如图3A所示,根据一些实施例,形成类似于图1H所示的结构。如图3A所示,导电结构112A、112B、112C、及112D的顶表面系高于半导体晶片122A及122B的顶表面。在一些实施例中,若导电结构112A、112B、112C、及112D高于半导体晶片122A及122B,保护层124的形成可更容易进行。一些模塑化合物形成在导电结构112A、112B、112C、及112D或半导体晶片122A及122B上的风险可获显著地降低。在一些实施例中,导电结构112A与半导体晶片122A之间具有高度差(height difference)ΔH,其介于约2微米至约3微米之间。
在一些情形中,若高度差ΔH小于约2微米(例如,1微米或更小),在移除模子200之后,可能会有一些模塑化合物材料形成在导电结构112A、112B、112C、及112D的顶表面之上。因此,连至导电结构112A、112B、112C、及112D的电性连接可能受到不利的影响。或者,可能需要进行附加的清理处理以移除形成在导电结构112A、112B、112C、及112D的顶表面上的模塑化合物材料。可能会增加制作成本及工艺时间。
在一些其他情形中,若高度差ΔH大于约3微米(例如,4微米或更大),在移除模子200之后,可能会有一些模塑化合物材料形成在半导体晶片122A及122B的导电垫118的顶表面之上。因此,连至半导体晶片122A及122B的电性连接能受到不利的影响。或者,可能需要进行附加的清理处理以移除形成在导电垫118的顶表面上的模塑化合物材料。可能会增加制作成本及工艺时间。
然而,应注意的是,本揭露书的实施例不限于此。可对本揭露书的实施例做出许多的改变及/或修饰。在一些其他实施例中,高度差ΔH具有不同的范围。在一些实施例中,高度差ΔH系介于约1微米至约5微米之间。在一些其他实施例中,高度差ΔH系介于约0.1微米至约10微米之间。
之后,如图3B所示,根据一些实施例,进行类似于或相同于图1I-1L、图2A-1至2C-1、及图2A-2至2C-2所述的制备工艺以形成晶片封装体。
本揭露的实施例形成晶片封装体,其具有半导体晶片及数个导电结构。导电结构穿过围绕半导体晶片及导电结构的保护层(或模塑化合物层)。使用模子来辅助形成保护层。可不需薄化保护层来露出导电结构及/或半导体晶片的导电垫。可显著地减少制作成本及工艺时间。亦可避免因薄化工艺所造成的损伤。使用切割工艺来辅助形成导电结构。可更进一步地减少制作成本及工艺时间。
根据一些实施例,提供一种晶片封装体的形成方法。方法包括于承载基底之上形成数个导电结构,及于承载基底之上设置半导体晶片。方法还包括于承载基底之上设置模子。方法更包括于模子与承载基底之间形成保护层来围绕半导体晶片及导电结构。此外,方法包括移除模子。
根据一些实施例,提供一种晶片封装体的形成方法。方法包括于承载基底之上形成多个导电结构。方法还包括切除导电部分的较上部分,使得导电结构的表面大抵彼此共平面。方法更包括于承载基底之上设置半导体晶片。此外,方法包括于承载基底之上形成保护层以围绕导电结构及半导体晶片。
根据一些实施例,提供一种晶片封装体。晶片封装体包括半导体晶片及包覆半导体晶片的保护层。晶片封装体还包括导电结构,其位于保护层之中,且借着保护层而与半导体晶片隔开。保护层具有凹陷,其介于半导体晶片与导电结构之间。
在一些实施例中,一种形成晶片封装体的方法包括:于一承载基底之上形成多个导电结构;于该承载基底之上设置一半导体晶片;于该承载基底之上设置一模子;于该模子与该承载基底之间形成一保护层,以围绕该半导体晶片与该些导电结构;以及移除该模子。
在一些实施例中,方法更包括透过该模子的一开口而于该模子中注入一模塑化合物材料以形成该保护层。
在一些实施例中,其中该模子包括一离型膜,且在注入该模塑化合物材料期间,该离型膜直接接触该些导电结构。
在一些实施例中,其中在注入该模塑化合物材料期间,该离型膜直接接触该半导体晶片。
在一些实施例中,方法更包括:于该保护层、该些导电结构、及该半导体晶片之上形成一内连线结构;以及移除该承载基底。
在一些实施例中,其中在移除该模子之后与形成该内连线结构之前,不将该保护层及该些导电结构平坦化。
在一些实施例中,方法更包括切除该些导电结构的较上部分,使得该些导电结构的顶表面大抵彼此共平面。
在一些实施例中,方法更包括:于该承载基底之上形成一遮罩层,其中该遮罩层具有多个开口,其露出承载基底之上的一晶种层;以镀工艺于该些开口中形成该些导电结构;切除该遮罩层与该些导电结构的较上部分,使得该些导电结构的顶表面大抵彼此共平面;以及移除该遮罩层。
在一些实施例中,其中该半导体晶片与该些导电结构其中之一间的高度差介于约2微米与约3微米之间。
在一些实施例中,一种晶片封装体的形成方法包括:于一承载基底之上形成多个导电结构;切除该些导电结构的较上部分,使得该些导电结构的顶表面大抵彼此共平面;于该承载基底之上设置一半导体晶片;以及该承载基底之上形成一保护层以围绕该些导电结构与该半导体晶片。
在一些实施例中,方法更包括:于该保护层、该些导电结构、及该半导体晶片之上形成一内连线结构;于该内连线结构之上形成多个导电凸块;以及移除该承载基底。
在一些实施例中,其中在形成该内连线结构之前,不将该保护层薄化。
在一些实施例中,其中借着使用一镀工艺来形成该些导电结构。
在一些实施例中,方法更包括于该承载基底之上注入一模塑化合物材料以形成该保护层,其中在注入该模塑化合物材料期间,该模塑化合物材料没有覆盖该些导电结构的该些顶表面。
在一些实施例中,方法更包括于该承载基底之上设置一模子以于该承载基底与该模子之间形成一空间;透过该模子的一开口而于该空间之中注入该模塑化合物材料;以及移除该模子。
在一些实施例中,其中该模子包括一离型模,且该离型模直接接触该些导电结构。
在一些实施例中,其中该些导电结构的该些顶表面高于该半导体晶片的一顶表面。
在一些实施例中,一种晶片封装体包括:一半导体晶片;一保护层,其包覆该半导体晶片;以及一导电结构,位于该保护层之中,且借着该保护层而与该半导体晶片隔离,其中该保护层具有一凹陷,其介于该半导体晶片与该导电结构之间。
在一些实施例中,其中该导电结构具有一线形的侧壁。
在一些实施例中,其中该凹陷具有一深度,介于约3微米至约10微米之间。
前述内文概述了许多实施例的特征,以使本技术领域中具有通常知识者可以从各个方面更佳地了解本揭露。本技术领域中具有通常知识者应可理解,且可轻易地以本揭露为基础来设计或修饰其他工艺及结构,并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未背离本揭露的发明精神与范围。在不背离本揭露的发明精神与范围的前提下,可对本揭露进行各种改变、置换或修改。
虽然本揭露已以数个较佳实施例揭露如上,然其并非用以限定本揭露,任何所属技术领域中具有通常知识者,在不脱离本揭露的精神和范围内,当可作任意的更动与润饰,因此本揭露的保护范围当视后附的申请专利范围所界定者为准。
Claims (1)
1.一种形成晶片封装体的方法,包括:
于一承载基底之上形成多个导电结构;
于所述承载基底之上设置一半导体晶片;
于所述承载基底之上设置一模子;
于所述模子与所述承载基底之间形成一保护层,以围绕所述半导体晶片与所述多个导电结构;以及
移除所述模子。
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