CN109786354A - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN109786354A
CN109786354A CN201810378674.3A CN201810378674A CN109786354A CN 109786354 A CN109786354 A CN 109786354A CN 201810378674 A CN201810378674 A CN 201810378674A CN 109786354 A CN109786354 A CN 109786354A
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CN
China
Prior art keywords
layer
mentioned
prominent
substrate
underbump metallization
Prior art date
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Pending
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CN201810378674.3A
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English (en)
Inventor
曹佩华
陈承先
朱立寰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109786354A publication Critical patent/CN109786354A/zh
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Abstract

本公开实施例提供一种封装结构。此封装结构包括介电层形成于第一基板之上，以及导电层形成于介电层之中。此封装结构包括凸块下金属层形成于介电层之上，且凸块下金属层电性连接至导电层。此封装结构亦包括第一突出结构形成于凸块下金属层之上，且第一突出结构延伸向上远离凸块下金属层。此封装结构包括第二突出结构形成于凸块下金属层之上，且第二突出结构延伸向上远离凸块下金属层。此封装结构包括第一电性连接器形成于第一突出结构之上；以及第二电性连接器形成于第二突出结构之上。气隙形成于第一突出结构与第二突出结构之间。

Description

封装结构
技术领域
本公开实施例是关于一种半导体结构，且特别是关于一种封装结构及其形成方法。
背景技术
半导体装置使用于各种电子应用中，例如个人电脑、手机、数码相机和其他电子设备。半导体装置通常通过以下方式而制造，包括在半导体基板上依序沉积绝缘或介电层、导电层及半导体层，使用光刻工艺图案化上述各材料层，借以在此半导体基板上形成电路组件及元件。通常在单一半导体晶片上制造许多集成电路，并且通过沿着切割线在集成电路之间进行切割，以将各个管芯单一化。上述各个管芯通常分别地封装于，例如，多芯片模块中或其他类型的封装中。
已经开始发展新的封装技术，例如，堆叠式封装(package on package,PoP)，其中具有装置管芯的顶部封装接合至具有另一个装置管芯的底部封装。通过采用新的封装技术，将具有不同或相似功能的各种封装整合在一起。
虽然现有的封装结构与制造封装结构的方法一般已足以胜任其预期目的，但其尚未全面满足所有的面向。
发明内容
根据一些实施例，本公开提供一种封装结构，包括︰介电层，形成于第一基板之上；导电层，形成于介电层之中；凸块下金属层，形成于介电层之上，其中凸块下金属层电性连接至导电层；第一突出结构，形成于凸块下金属层之上，其中第一突出结构延伸向上远离凸块下金属层；第二突出结构，形成于凸块下金属层之上，其中第二突出结构延伸向上远离凸块下金属层；第一电性连接器，形成于第一突出结构之上；以及第二电性连接器，形成于第二突出结构之上，其中气隙形成于第一突出结构与第二突出结构之间。
根据一些实施例，本公开提供一种封装结构，包括︰装置管芯，形成于第一基板之上；导电垫，形成于装置管芯之上；介电层，形成于导电垫之上；导电层，形成于介电层之中且位于导电垫之上，其中导电垫电性连接至导电层；第一凸块下金属层，形成于介电层之上，其中凸块下金属层电性连接至导电层；第一突出结构，形成于第一凸块下金属层之上；第一电性连接器，形成于第一突出结构之上；贯孔结构，相邻于装置管芯而形成；第二凸块下金属层，形成于贯孔结构之下；第二突出结构，形成于第二凸块下金属层之上；以及第二电性连接器，形成于第二突出结构之上。
根据一些实施例，本公开提供一种封装结构，包括︰第一装置管芯，形成于第一基板之上；封装结构，围绕第一装置管芯；导电层，形成于第一装置管芯与封装层之上；多个第一电性连接器，形成于第一装置管芯之上，其中第一电性连接器具有第一高度；多个第二电性连接器，形成于封装层之上，其中第二电性连接器具有第二高度，且第二高度大于第一高度；第二装置管芯，形成于第一电性连接器之上；以及多个突出结构，埋设于第二电性连接器之中，其中突出结构延伸向上远离导电层。
附图说明
根据以下的详细说明并配合所附附图做完整公开。应注意的是，根据本产业的一般作业，图示并未必按照比例绘制。事实上，可能任意的放大或缩小元件的尺寸，以做清楚的说明。
图1A到图1L示出依据本公开的一些实施例的形成第一封装结构的各个工艺阶段的剖面图。
图2A示出依据本公开的一些实施例的第一突出结构、第二突出结构及凸块下金属层的沿着图1L的I-I’剖线的俯视图。
图2B示出依据本公开的一些实施例的图1L的第一突出结构、第二突出结构、凸块下金属层及第一基板的俯视图。
图3A示出依据本公开的一些实施例的封装结构的剖面图。
图3B示出依据本公开的一些实施例的第一突出结构、第二突出结构及凸块下金属层的沿着图3A的II-II’剖线的俯视图。
图3C示出依据本公开的一些实施例的图3A的第一突出结构、第二突出结构、凸块下金属层及第一基板的俯视图。
图4A示出依据本公开的一些实施例的封装结构的剖面图。
图4B示出依据本公开的一些实施例的第一突出结构、第二突出结构及凸块下金属层的沿着图4A的III-III’剖线的俯视图。
图4C示出依据本公开的一些实施例的图4A的第一突出结构、第二突出结构、凸块下金属层及第一基板的俯视图。
图5A到图5C示出依据本公开的一些实施例的形成第一封装结构的各个工艺阶段的剖面图。
图6A到图6H示出依据本公开的一些实施例的形成第一封装结构的各个工艺阶段的剖面图。
附图标记说明：
100a、100b、100c、100d、100e～封装结构
102～基板
104～装置元件
106～粘着层
108～装置管芯
110～层间介电层
120～金属层间介电层
122～贯孔结构
122a～第一表面
122b～第二表面
123～绝缘层
124～钝化层
130～第一介电层
132～导电垫
134～后钝化内连线垫
137～开口
140～第二介电层
142～导电层
150～保护层
150a～第一次层
150b～第二次层
152～导电层
157～开口
160～凸块下金属层
162～籽晶层
164～光致抗蚀剂层
165～开口
166～突出结构
166a～第一突出结构
166a1～第一部分
166a2～第二部分
166b～第二突出结构
166b1～第一部分
166b2～第二部分
167a1～第一部分
167a2～第二部分
167b1～第一部分
167b2～第二部分
168～电性连接器
180～凸块下金属层
182～籽晶层
186～突出结构
188～电性连接器
190～气隙
200～第二封装结构
202～第二基板
204～导电垫
300～第三封装结构
302～第三基板
304～导电垫
402～承载基板
404～粘着层
406～基础层
410～内连线结构
412～导电层
414～钝化层
415～间隙
416～贯孔结构
418～粘着层
420～封装层
425～沟槽
427～开口
430～凸块下金属层
432～籽晶层
436～突出结构
438～电性连接器
440～凸块下金属层
442～电性连接器
444～底部填充物
450～元件
500～装置管芯
502～半导体基板
504～钝化层
506～导电垫
508～钝化层
510～导电层
512～保护层
514～保护基板
516～承载体
600～第二封装结构
602～第二基板
604～导电垫
C～中心点
D～中心点
d1～第一距离
H1～第一高度
H2～第二高度
P1P2～第一虚设中心线
P3P4～第二虚设中心线
P5P6～第三虚设中心线
P7P8～第四虚设中心线
W1～第一宽度
W2～第二宽度
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本案的不同部件(feature)。以下的公开内容叙述各个构件及其排列方式的特定范例，以简化说明。当然，这些特定的范例并非用以限定。例如，若是本说明书叙述了一第一部件形成于一第二部件之上或上方，即表示其可能包括上述第一部件与上述第二部件是直接接触的实施例，亦可能包括了有附加部件形成于上述第一部件与上述第二部件之间，而使上述第一部件与第二部件可能未直接接触的实施例。另外，以下公开的不同范例可能重复使用相同的参照符号和/或标记。这些重复系为了简化与清晰的目的，并非用以限定所讨论的不同实施例和/或结构之间有特定的关系。
下文描述实施例的各种变化。通过各种视图与所示出的实施例，类似的元件标号用于标示类似的元件。应可理解的是，可在进行所述的方法之前、之间或之后，提供额外的操作步骤，并且在所述的方法的其他实施例中，所述的部分步骤可被变更顺序、置换或省略。
以下提供封装结构及其制造方法的实施例。图1A到图1L示出依据本公开的一些实施例的形成第一封装结构100a的各个工艺阶段的剖面图。
请参照图1A，提供基板102。基板102可由硅或其他半导体材料所形成，例如锗(Ge)。在一些实施例中，基板102为装置管芯的基板。在一些实施例中，基板102由化合物半导体所形成，例如，碳化硅(silicon carbide)、砷化镓(gallium arsenic)、砷化铟(indiumarsenide)或磷化铟(or indium phosphide)。在一些实施例中，基板102由半导体材料、陶瓷材料、聚合物材料、金属材料、其他合适的材料或上述的组合所形成。在一些实施例中，基板102为玻璃基板。在一些实施例中，基板102为半导体基板，例如，硅晶片。
形成装置元件(device element)104于基板102之上。装置元件104包括晶体管(例如，金属氧化物半导体场效晶体管(MOSFET)、互补式金属氧化物半导体(CMOS)晶体管、双极接面晶体管(bipolar junction transistors,BJT)、高压晶体管、高频晶体管、p-沟道和/或n-沟道场效应晶体管(PFET/NFET)等)、二极管和/或其他合适的元件。进行各种不同的工艺(例如，沉积、蚀刻、注入、光刻、退火和/或其他合适的工艺)，以形成各种不同的装置元件104。在一些实施例中，装置元件104于前段工艺(front-end-of-line,FEOL)中形成于基板102中。
基板102可包括各种不同的掺杂区，例如，p型井区或n型井区。掺杂区可掺杂p型掺杂物(例如，硼或二氟化硼离子(BF2))和/或n型掺杂物(例如，磷或砷)。掺杂区可直接形成基板102之中或之上，而位于p型井区结构、n型井区结构或双井区结构之中。
基板102可进一步包括隔离部件(未示出)，例如，浅沟槽隔离(STI)部件或硅局部氧化(local oxidation of silicon,LOCOS)部件。隔离部件可定义及隔离各种不同的装置元件。
形成金属层间介电(inter-metal dielectric,IMD)层120于层间介电(ILD)层110之上。金属层间介电层120由氧化硅(SiOx)、氮化硅(SixNy)、氮氧化硅(SiON)、具有低介电常数(low-k)的介电材料或上述的组合所形成。在一些实施例中，金属层间介电层120由极低介电常数(extreme low-k,ELK)介电材料所形成，其中极低介电常数介电材料具有低于约2.5的介电常数。在一些实施例中，极低介电常数介电材料包括掺杂碳的氧化硅(carbondoped silicon oxide)、非晶氟化碳(amorphous fluorinated carbon)、聚对二甲苯(parylen)、双苯并环丁烯(bis-benzocyclobutenes,BCB)、聚四氟乙烯(polytetrafluoroethylene,PTFE)(铁氟龙)或碳氧化硅聚合物(silicon oxycarbidepolymers,SiOC)。在一些实施例中，极低介电常数介电材料包括多孔形式的现有介电材料，例如，氢倍半硅氧烷(hydrogen silsesquioxane,HSQ)、多孔甲基倍半硅氧烷(porousmethyl silsesquioxane,MSQ)、多孔聚芳醚(porous polyarylether,PAE)、多孔SiLK(porous SiLK)或多孔二氧化硅(SiO2)。在一些实施例中，通过等离子体增强化学气相沉积(plasma enhanced CVD,PECVD)工艺或旋转涂布(spin coating)工艺，以沉积金属层间介电层120。
形成导电垫132于金属层间介电层120之上。导电垫132经由金属层间介电层120之中的各种不同金属导线及介层窗(via)而电性连接至装置元件104。
在后段工艺(back-end-of-line,BEOL)中形成金属层间介电层120及导电垫132。导电垫132由铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)或钽合金所形成。在一些实施例中，通过电镀法(plating)形成导电垫132。
形成钝化层124于金属层间介电层120之上，且覆盖导电垫132的边缘部分。另外，露出导电垫132的中心部分。在一些实施例中，钝化层124由非有机材料(non-organicmaterials)所形成，例如，氧化硅、未掺杂硅玻璃(un-doped silicate glass)、氮氧化硅、阻焊剂(solder resist,SR)、氮化硅或六甲基二硅氮烷(hexamethyldisilazane,HMDS)。在一些实施例中，钝化层124由聚合物材料所形成，例如，聚酰亚胺(polyimide,PI)、环氧化物或含氟聚合物材料。
之后，根据本公开一些实施例，如图1B所示出，在形成钝化层124之后，形成第一介电层130于钝化层124之上。
之后，通过图案化工艺将第一介电层130图案化，而露出一部分的导电垫132。图案化工艺包括光刻工艺与蚀刻工艺。光刻工艺的范例包括光致抗蚀剂涂布、软烘烤(softbaking)、光掩模对准(mask aligning)、曝光(exposure)、曝光后烘烤(post-exposurebaking)、显影(developing)光致抗蚀剂、润洗(rising)、干燥(例如，硬烘烤(hardbaking))。蚀刻工艺包括干式蚀刻工艺或湿式蚀刻工艺。
在一些实施例中，第一介电层130由氧化硅、氮化硅、氮氧化硅或其他合适的材料所形成。形成后钝化内连线(post-passivation interconnect,PPI)垫134于第一介电层130内，且电性连接至导电垫132。后钝化内连线垫134在形成钝化层124之后形成。在一些实施例中，后钝化内连线垫134称为重分布(redistribution layer,RDL)垫。
后钝化内连线垫134由导电材料所形成，例如，铜、铜合金、铝、铝合金、钨、钨合金、钛、钛合金、钽或钽合金。通过电镀、无电电镀(electroless plating)、溅镀(sputtering)或化学气相沉积，以形成后钝化内连线垫134。
通过将导电材料(例如，金属材料)填入开口之中且沉积于第一介电层130之上，以形成后钝化内连线垫134。之后，通过化学机械研磨(chemical mechanical polishing,CMP)工艺移除多余的导电材料。
之后，根据本公开一些实施例，如图1C所示出，在形成后钝化内连线垫134之后，形成第二介电层140于第一介电层130及后钝化内连线垫134之上。第二介电层140由聚苯并恶唑(polybenzoxazole,PBO)、双-苯并环丁烯(BCB)、硅胶(silicone)、丙烯酸酯(acrylates)、硅氧烷(siloxane)或上述的组合所形成。
在形成第二保护层140之后，通过图案化工艺将第二保护层140图案化，以形成开口137。因此，露出至少一部分的后钝化内连线垫134。
之后，根据本公开一些实施例，如图1D所示出，形成导电层142于开口137之中及第二介电层140之上。导电层142电性连接至后钝化内连线垫134。导电层142是用以电性连接至基板102的不同区域。
导电层142由导电材料所形成，例如，铜、铜合金、铝、铝合金、钨、钨合金、钛、钛合金、钽)或钽合金。通过电镀、无电电镀、溅镀或化学气相沉积，以形成导电层142。
之后，根据本公开一些实施例，如图1E所示出，在形成导电层142之后，形成保护层150。之后，将保护层150图案化，以形成开口157。通过开口157露出一部分的导电层142。
形成保护层150于装置元件104之上，以防止水气穿透，进而导致下方的保护层及后钝化内连线结构发生剥离。所形成的保护层150有助于封装结构100a能够经过严苛环境(例如，各种不同的可靠度测试)而没有任何水气能够透入。
在一些实施例中，保护层150包括无机材料，例如，氮化硅、氧化硅、氮氧化硅、六甲基二硅氮烷或上述的组合。另外，保护层150包括聚合物材料，例如，聚酰亚胺、环氧化物、阻焊剂、含氟聚合物材料或上述的组合。
之后，根据本公开一些实施例，如图1F所示出，在形成开口157之后，形成凸块下金属(under bump metallurgy,UBM)层160于保护层150之中。
凸块下金属层160由导电材料所形成，例如，铜、铜合金、铝、铝合金、钨、钨合金、钛、钛合金、钽或钽合金。另外，凸块下金属层160可包括粘着层和/或润湿层(wettinglayer)。在一些实施例中，凸块下金属层160还包括铜籽晶层(seed layer)。在一些实施例中，凸块下金属层160包括由钛/铜所形成的粘着层，以及由铜所形成的润湿层。
之后，根据本公开一些实施例，如图1G所示出，顺应性地形成籽晶层162于保护层150与凸块下金属层160之上。籽晶层162由金属材料所形成，例如，铜、钛、铜合金、钛合金或上述的组合。在一些实施例中，通过沉积工艺形成籽晶层162，例如，化学气相沉积工艺、物理气相沉积工艺、其他合适的工艺或上述的组合。
之后，根据本公开一些实施例，如图1H所示出，形成光致抗蚀剂层164于籽晶层162之上，并且将光致抗蚀剂层164图案化，以形成多个开口165。如此一来，暴露一部分的籽晶层162。
之后，根据本公开一些实施例，如图1I所示出，形成导电材料于开口165之中且位于籽晶层162之上，以形成多个突出结构(protrusion structure)166。突出结构166向上延伸远离凸块下金属层160。更具体而言，突出结构166从籽晶层162的顶表面向上延伸至高于凸块下金属层160的位置。
使用突出结构166作为裂缝停止结构(crack-stop structure)，以抑制在电性连接器168(示出于图1K中)之中的裂缝的传播。此外，突出结构166用以避免裂缝的形成。
之后，根据本公开一些实施例，如图1J所示出，移除光致抗蚀剂层164，并且移除一部分的籽晶层162。如此一来，突出结构166包括第一突出结构166a与第二突出结构166b。
第一突出结构166a包括第一部分166a1与第二部分166a2，且第二突出结构166b包括第一部分166b1与第二部分166b2。每一个第一突出结构166a与第二突出结构166b各自的外侧表面对准于凸块下金属层160的外侧表面。
在一些实施例中，突出结构166a、166b的每一者各自由铜、铜合金、铝、铝合金、钨、钨合金、钛、钛合金、钽或钽合金所形成。在一些实施例中，使用电镀法形成突出结构166。
突出结构166沿着垂直方向具有第一高度H1，且沿着水平方向具有第一宽度W1。在一些实施例中，第一高度H1为约10μm至约50μm的范围。在一些实施例中，第一宽度W1为约20μm至约40μm的范围。
之后，根据本公开一些实施例，如图1K所示出，形成多个电性连接器168于突出结构166之上。电性连接器168直接形成于凸块下金属层160与突出结构166之上。第一突出结构166a与第二突出结构166b各自独立地埋设于电性连接器168之中。每一个第一突出结构166a的外侧表面与每一个第二突出结构166b的外侧表面实质上对准于电性连接器168的外侧表面。
每一个第一突出结构166a与每一个第二突出结构166b的熔点高于每一个电性连接器168的熔点。每一个电性连接器168由具有低电阻值的导电材料所形成，例如，焊料或焊料合金。包括于焊料合金中的范例元素可包括锡(Sn)、铅(Pb)、银(Ag)、铜、镍(Ni)、铋(Bi)或上述的组合。
每一个电性连接器168具有第二高度H2，其中第二高度H2是量测从保护层150的顶表面到电性连接器168的顶表面而得。在一些实施例中，第二高度H2为约150μm至约200μm的范围。在一些实施例中，第一高度H1对第二高度H2的高度比率(H1/H2)为约1/20至约1/3的范围。如果高度比率太小，则突出结构166a、166b不够高而无法使裂缝停止。如果高度比率太大，则可能很难形成电性连接器168于凸块下金属层160之上。电性连接器168沿着水平方向具有第二宽度W2。在一些实施例中，第二宽度W2为约180μm至约200μm的范围。
之后，根据本公开一些实施例，如图1L所示出，形成第二封装结构200于第一封装结构100a之上。第二封装结构200包括形成于第二基板202之上的导电垫204。一些装置元件(未示出)形成于第二基板202之中。通过电性连接器168与导电垫204，以接合第一封装结构100a与第二封装结构200。
形成气隙(air gap)190于第一突出结构166a与第二突出结构166b之间。需注意的是，并无底部填充物(underfill)位于第一突出结构166a与第二突出结构166b之间。因为第一突出结构166a与第二突出结构166b能够抑制裂缝或避免裂缝形成，所以不需要使用功能为降低裂缝的底部填充物。因此，能够降低工艺时间与成本。
需注意的是，当管芯(die)(例如，基板102)的尺寸变大时，集中在电性连接器的应力将变大。如此一来，会有一些裂缝形成于电性连接器之中。使用突出结构166作为应力停止结构，以抑制在电性连接器168之中的裂缝的传播。由于抑制电性连接器168中的裂缝，因而能够提升封装结构100a的效能与可靠度。
图2A示出依据本公开的一些实施例的第一突出结构166a、第二突出结构及凸块下金属层160的沿着图1L的I-I’剖线的俯视图。
当从俯视图观察时，第一突出结构166a具有不连续形状(non-continuousshape)，且具有第一部分166a1与第二部分166a2。每一个第一部分166a1与第二部分166a2各自具有弓形结构(bow-shaped structure)。当从俯视图观察时，电性连接器168具有圆形形状。需注意的是，如果第一突出结构166a包括连续的环，则可能会在电性连接器168中形成空孔(void)。因此，第一突出结构166a并不包括连续的环状部分(continuous ringportion)。
在凸块下金属层160之中有中心点C。相对于凸块下金属层160的中心点C，第一部分166a1与第二部分166a2是对称的。第一虚设中心线P1P2穿越第一突出结构166a的第一部分166a1。第二虚设中心线P3P4穿越第一突出结构166a的第二部分166a2。第一虚设中心线P1P2与第二虚设中心线P3P4两者是对称轴。第一虚设中心线P1P2与第二虚设中心线P3P4两者穿越凸块下金属层160的中心点C。
需注意的是，第一虚设中心线P1P2与第二虚设中心线P3P4两者是用以定义第一部分166a1与第二部分166a2的形状，且两者并非真实存在的线。
同样的，第二突出结构166b具有第一部分166b1与第二部分166b2。相对于凸块下金属层160的中心点C，第二突出结构166b的第一部分166b1与第二部分166b2是对称的。第一部分166b1的第三虚设中心线P5P6与第二部分166a2的第四虚设中心线P7P8两者穿越凸块下金属层160的中心点C。
如图2A所示出，第一突出结构166a的第一部分166a1与第二部分166a2的长度总和，相对于电性连接器168的圆周长的长度比率为约1/3至约1/2的范围。若比率不在上述范围内，则第一突出结构166a可能无法抑制在电性连接器168之中的裂缝的传播。
图2B示出依据本公开的一些实施例的图1L的第一突出结构166a、第二突出结构166b、凸块下金属层160及第一基板102的俯视图。示出于图2A中的a1a1’线可以是图2B中的a1a1’线、a2a2’线、a3a3’线或a4a4’线。
当从俯视图观察时，基板102具有矩形形状。在一些实施例中，基板102是管芯的基板。基板102具有中心点D。有多个电性连接器168形成于基板102之上。虽然图2B示出8个电性连接器168，但是，依据实际应用，电性连接器168的数量可大于8个。在一些实施例中，基板102是管芯，其面积为约5*5mm2至约7*7mm2的范围。
a1a1’线、a2a2’线、a3a3’线及a4a4’线穿过基板102(或管芯)的中心点D。换言之，a1a1’线、a2a2’线、a3a3’线及a4a4’线从基板102的中心点辐射散出。应力可能集中于电性连接器168上，特别是，位于对角位置的应力。因此，第一突出结构166a与第二突出结构166b设置在相会于基板102的中心点D的水平线、垂直线或对角线上。
示出于图2A的电性连接器168可以是示出于图2B的沿着a1a1’线的编号1与编号8的两个电性连接器168。再者，第一突出结构166a的第一部分166a1的第一虚设中心线P1P2，以及第一突出结构166a的第二部分166a2的第二虚设中心线P3P4穿过基板102的中心点D。
在一些实施例中，示出于图2A的电性连接器168可以是示出于图2B的沿着a4a4’线的编号2与编号7的两个电性连接器168。在一些其他实施例中，示出于图2A的电性连接器168可以是示出于图2B的沿着a2a2’线的编号4与编号5的两个电性连接器168。在一些其他实施例中，示出于图2A的电性连接器168可以是示出于图2B沿着a3a3’线的编号6与编号3的两个电性连接器168。
图3A示出依据本公开的一些实施例的封装结构100b的剖面图。图3A类似于图1L，在图3A中，每一个第一突出结构166a与第二突出结构166b的外侧表面并未对准于凸块下金属层160的外侧表面。介于凸块下金属层160的外侧表面与第一突出结构166a的外侧表面之间的距离为第一距离d1。在一些实施例中，第一距离d1为约0.1μm至约50μm的范围。
图3B示出依据本公开的一些实施例的第一突出结构166a、第二突出结构166b及凸块下金属层160的沿着图3A的II-II’剖线的俯视图。第一突出结构166a包括第一部分166a1与第二部分166a2。相对于凸块下金属层160的中心点C，第一突出结构166a的第一部分166a1与第二部分166a2是对称的。第一部分166a1的第一虚设中心线P1P2与第二部分166a2第二虚设中心线P3P4两者穿过凸块下金属层160的中心点C。
图3C示出依据本公开的一些实施例的图3A的第一突出结构166a、第二突出结构166b、凸块下金属层160及第一基板102的俯视图。示出于图3B的a1a1’线可以是示出于图3B的a1a1’线、a2a2’线、a3a3’线或a4a4’线。当从俯视图观察时，基板102具有矩形形状。在一些实施例中，基板102是管芯的基板。有多个电性连接器168形成于基板102之上。a1a1’线、a2a2’线、a3a3’线及a4a4’线穿过基板102的中心点D。
图4A示出依据本公开的一些实施例的封装结构100c的剖面图。图4B示出依据本公开的一些实施例的第一突出结构166a、第二突出结构166b及凸块下金属层160的沿着图4A的III-III’剖线的俯视图。图4C示出依据本公开的一些实施例的图4A的第一突出结构166a、第二突出结构166b、凸块下金属层160及第一基板102的俯视图。
如图4A与图4B所示出，第一突出结构166a包括第一不连续同心环(non-continuous concentric ring)与第二不连续同心环。第一不连续同心环包括第一部分166a1与第二部分166a2，第二不连续同心环包括第一部分167a1与第二部分167a2。第二不连续同心环比第一不连续同心环更靠近凸块下金属层160的中心点C。第一不连续同心环的第一部分166a1的外侧表面对准于凸块下金属层160的外侧表面，但是第二不连续同心环的第一部分167a1的外侧表面并未对准于凸块下金属层160的外侧表面。在电性连接器168之中的裂缝可以有效地被这两个不连续环所抑制。
如图4C所示出，示出于图4B中的a1a1’线可以是示出于图4C中的a1a1’线、a2a2’线、a3a3’线或a4a4’线。在一些实施例中，基板102是管芯的基板。有多个电性连接器168形成于基板102之上。a1a1’线、a2a2’线、a3a3’线及a4a4’线穿过基板102的中心点D。
图5A到图5C示出依据本公开的一些实施例的形成第一封装结构100d的各个工艺阶段的剖面图。
如图5A所示出，形成粘着层106于基板102之上，且形成装置管芯108于粘着层106之上。形成贯孔结构(through via structure)122相邻于装置管芯108。绝缘层123围绕贯孔结构122的侧壁，且分隔贯孔结构122与装置管芯108。在一些实施例中，绝缘层123包括氧化硅、氮化硅、贯孔结构122的氧化物、模制化合物(molding compound)或上述的组合。
贯孔结构122用以连结至其他封装结构。贯孔结构122由铜、金、银或其他合适的材料所形成。
保护层150包括第一次层(first sub-layer)150a与第二次层(second sub-layer)150b，用于使多于一层的导电层能够形成于保护层150之中。在一些实施例中，第一次层150a与第二次层150b由不同材料所形成。
导电层152形成于保护层150之中且电性连结至导电层142。凸块下金属层160形成于导电层152之上。籽晶层162形成于凸块下金属层160之上，且突出结构166形成于籽晶层162之上。
之后，根据本公开一些实施例，如图5B所示出，形成电性连接器168于突出结构166之上。形成第二封装结构200于第一封装结构100d之上。第二封装结构200包括形成于第二基板202之上的导电垫204。一些装置元件(未示出)形成于第二基板202之中。通过电性连接器168与导电垫204，以接合第一封装结构100d与第二封装结构200。形成气隙190于第一突出结构166a与第二突出结构166b之间。并无底部填充物位于第一突出结构166a与第二突出结构166b之间。
之后，根据本公开一些实施例，如图5C所示出，沟槽(未示出)形成于基板102之中，且接着形成凸块下金属层180于沟槽之中。贯孔结构122具有第一表面122a，以及相对于第一表面122a的第二表面122b。第一表面122a直接接触导电层142，且第二表面122b直接接触凸块下金属层180。形成籽晶层182于凸块下金属层180之上，并且形成突出结构186于籽晶层182之上。形成电性连接器188于凸块下金属层180与突出结构186之上。
形成第三封装结构300于第一封装结构100d之上。第三封装结构300包括形成于第三基板302之上的导电垫304。通过电性连接器188与导电垫304，以接合第一封装结构100d与第三封装结构300。第二封装结构200与第三封装结构300位于基板102的相对两侧上。
图6A到图6H示出依据本公开的一些实施例的形成第一封装结构100e的各个工艺阶段的剖面图。
如图6A所示出，形成粘着层404于承载基板402之上。在一些实施例中，使用承载基板402作为暂时基板。此暂时基板在后续的工艺步骤期间提供机械性和结构性的支撑，其将在后续更加详细描述。承载基板402由半导体材料、陶瓷材料、聚合物材料、金属材料、其他合适的材料或上述的组合所形成。在一些实施例中，承载基板402为半导体基板，例如，硅晶片。
设置粘着层404于承载基板402之上。粘着层404可由粘胶所形成，或者可为积层材料(lamination material)，例如，金属箔(foil)。在一些实施例中，粘着层404为感光性的(photosensitive)，且容易通过光照射而从承载基板402脱离。举例而言，将紫外光或激光照射至承载基板402上，可分离粘着层404。在一些其他实施例中，粘着层404为感热性的(heat-sensitive)，且当暴露于热时，粘着层404容易从承载基板402脱离。
之后，依据本公开一些实施例，将基础层(base layer)406沉积或贴合至粘着层404之上。基础层406提供用于接合集成电路管芯的结构性的支撑，其将在后续更加详细描述，且基础层406有助减少管芯偏移(die shifting)的问题。在一些实施例中，基础层406为聚合物层或含聚合物层。基础层406可为聚对伸苯基苯并双噻唑(poly-p-phenylenebenzobisthiazole,PBO)层、聚酰亚胺层、阻焊剂层、味之素增层膜(Ajinomotobuildup film,ABF)、管芯贴附膜(die attach film,DAF)、其他合适的膜层或上述的组合。
形成内连线结构410于基础层406之上。内连线结构410包括一或多个导电层位于一或多个钝化层之中。举例而言，内连线结构410包括导电层412形成于钝化层414之中。
之后，根据本公开一些实施例，多个贯孔结构416形成内连线结构410之上。贯孔结构416包括导电柱(conductive pillar)或其他合适的结构。贯孔结构416可被称为中介层贯孔(through interposer vias,TIVs)。贯孔结构416物理性且电性连接至内连线结构410的其中一个导电层。
在一些实施例中，贯孔结构416由一材料所形成，此材料可包括铜、铝、镍、铂、无铅焊料(例如，锡银(SnAg)、锡铜(SnCu)、锡银铜(SnAgCu))、其他合适的导电材料或上述的组合。在一些实施例中，使用电镀工艺、物理气相沉积工艺、化学气相沉积工艺、电化学沉积(electrochemical deposition,ECD)工艺、分子束外延(molecular beam epitaxy,MBE)工艺、原子层沉积工艺或其他合适的工艺，以形成贯孔结构416。
之后，根据本公开一些实施例，如图6B所示出，通过粘着层418将装置管芯500设置于内连线结构410之上。在一些实施例中，装置管芯500的前侧(主动表面(activesurface))面向远离内连线结构410的方向。装置管芯500的背侧(非主动表面(non-activesurface))面向内连线结构410。装置管芯500可为包括晶体管、二极管或其他合适的集成电路元件的装置管芯。装置管芯也可包括电容、电感、电阻、其他集成电路元件或上述的组合。
在一些实施例中，装置管芯500包括半导体基板502、钝化层504及导电垫506。装置管芯500也可包括位于导电垫506上的连接器，以及围绕连接器的保护层。各种装置元件可形成于半导体基板502之中或之上。
粘着层418用以将装置管芯500接合或贴附到内连线结构410。粘着层418包括管芯贴附膜、其他合适的膜层或上述的组合。
之后，沉积封装层420于内连线结构410之上。因此，可通过封装层240封装贯孔结构416及装置管芯500。在一些实施例中，封装层420包括聚合物材料。在一些实施例中，封装层420包括模制化合物。
在一些实施例中，涂布模制化合物于贯孔结构416、装置管芯500及内连线结构410之上，且进行热处理工艺以将模制化合物硬化。在平坦化工艺之后，装置管芯500的顶表面实质上与贯孔结构416的顶表面等高。在一些实施例中，平坦化工艺包括研磨(grinding)工艺、化学机械研磨工艺、蚀刻工艺、其他合适的工艺或上述的组合
之后，根据本公开一些实施例，如图6C所示出，形成钝化层508于封装层420之上，并且形成导电层510于钝化层508之中。形成保护层512于钝化层508之上，并且形成保护基板514于保护层512之上。
在一些实施例中，保护基板514用作指纹辨识(fingerprint recognition)装置的面板。保护基板514由非有机材料或其他合适的材料所形成。在一些实施例中，保护基板514为玻璃基板、蓝宝石基板或其他合适的基板。
之后，根据本公开一些实施例，如图6D所示出，将图6C示出的结构翻转并且贴附至承载体(carrier)516。载板516包括感光性或感热性的胶带，且其容易从保护基板514脱离。
将承载基板402移除。在一些实施例中，移除承载基板402及粘着层404两者。可提供合适的光源，以移除粘着层404，并且移除承载基板402。
之后，移除基础层406的多个部分，以形成多个沟槽425与多个开口427。沟槽425与开口427暴露出部分的内连线结构410，例如，部分的导电层412。沟槽425位于贯孔结构416之上，且开口427位于装置管芯500之上。沟槽425的尺寸大于开口427的尺寸。举例而言，沟槽425的宽度大于开口427的宽度。
之后，根据本公开一些实施例，如图6E所示出，形成凸块下金属层430于沟槽425之中，并且形成凸块下金属层440于开口427之中。形成籽晶层432于凸块下金属层430之中，并且形成突出结构436于籽晶层432之上。
之后，根据本公开一些实施例，如图6F所示出，形成电性连接器438于凸块下金属层430与突出结构436之上。电性连接器438通过凸块下金属层430而电性连接至导电层412。
之后，根据本公开一些实施例，如图6G所示出，将元件450堆叠于内连线结构410之上。元件450与装置管芯500位于基础层406的相对两侧。元件450的尺寸小于装置管芯500的尺寸。更具体而言，元件450的宽度小于装置管芯500的宽度。形成凸块下金属层440于开口427之中，并且形成多个电性连接器442于凸块下金属层440之上。形成元件450于电性连接器442之上。间隙(space)415位于相邻的两个电性连接器442之间。每一个电性连接器438的尺寸大于每一个电性连接器442的尺寸。更具体而言，每一个电性连接器438的高度大于每一个电性连接器442的高度。
在一些实施例中，元件450为装置管芯。举例而言，此装置管芯为高电压管芯(high-voltage die)或其他合适的管芯。在一些其他实施例中，元件450包括封装结构，此封装结构含有一个或多个集成电路管芯。
之后，根据本公开一些实施例，如图6H所示出，形成第二封装结构600于第一封装结构100e之上。第二封装结构600包括导电垫604形成于第二基板602上。一些装置元件(未示出)形成于第二基板602之上。第一封装结构100e与第二封装结构600通过电性连接器438与导电垫604接合在一起。在一些实施例中，移除承载体516，以暴露出保护基板514。
如图6H所示出，底部填充物444填满间隙415。因此，底部填充物444位于相邻的两个电性连接器442之间。需注意的是，并无底部填充物位于相邻的两个电性连接器436之间。气隙190形成于底部填充物444与电性连接器438之间。
需注意的是，当管芯的尺寸变大时，集中在电性连接器的应力将变大。因此，集中在电性连接器438的应力大于集中在电性连接器442的应力。高应力可能造成裂缝形成于电性连接器之中。为了降低或避免裂缝的形成，埋设突出结构436于电性连接器438之中。在一些实施例中，每一个突出结构436的外侧表面对准于凸块下金属层440与电性连接器438的外侧表面，以适当地抑制在电性连接器438中裂缝的传播。
本公开提供封装结构及其形成方法的实施例。第一封装结构包括导电层形成于基板或是管芯上，以及凸块下金属层形成于上述导电层之上。籽晶层形成于上述凸块下金属层之上，且多个突出结构形成于上述籽晶层之上。多个电性连接器形成于上述突出结构之上。上述突出结构延伸远离于上述凸块下金属层。上述突出结构包括第一突出结构与第二突出结构。气隙位于上述第一突出结构与上述第二突出结构之间。并无底部填充物位于上述第一突出结构与上述第二突出结构之间。上述突出结构作为裂缝停止结构，以避免在上述电性连接器中形成裂缝。因此，能够减少电性连接器裂缝的问题，并且提升封装结构的效能与可靠度。
在一些实施例中，提供一种封装结构。上述封装结构包括介电层形成于第一基板之上，以及导电层形成于上述介电层之中。上述封装结构包括凸块下金属层形成于上述介电层之上，且上述凸块下金属层电性连接至上述导电层。上述封装结构亦包括第一突出结构形成于上述凸块下金属层之上，且上述第一突出结构延伸向上远离上述凸块下金属层。上述封装结构还包括第二突出结构形成于上述凸块下金属层之上，且上述第二突出结构延伸向上远离上述凸块下金属层。上述封装结构包括第一电性连接器形成于上述第一突出结构之上；以及第二电性连接器形成于上述第二突出结构之上。气隙形成于上述第一突出结构与上述第二突出结构之间。
如本公开的一些实施例所述的封装装置结构，其中上述第一突出结构具有外侧表面，且上述外侧表面对准于上述凸块下金属层的外侧表面。
如本公开的一些实施例所述的封装装置结构，其中当从俯视图观察时，上述第一突出结构具有不连续形状，且上述不连续形状包括第一部分及第二部分，且相对于上述凸块下金属层的中心，上述第一部分与上述第二部分是对称的。
如本公开的一些实施例所述的封装装置结构，其中当从俯视图观察时，上述第一突出结构具有不连续形状，且上述不连续形状包括第一不连续环及第二不连续环。
如本公开的一些实施例所述的封装装置结构，上述第一突出结构的熔点高于上述第一电性连接器的熔点。
如本公开的一些实施例所述的封装装置结构，还包括第二基板形成于上述第一电性连接器与上述第二电性连接器之上，且上述第一电性连接器电性连接至上述第二基板的一导电垫。
如本公开的一些实施例所述的封装装置结构，还包括装置管芯形成于上述第一基板之上；贯孔结构相邻于上述装置管芯而形成；以及第三基板位于上述贯孔结构之下，其中上述贯孔结构电性连接至上述第三基板的一导电垫。
如本公开的一些实施例所述的封装装置结构，其中并无底部填充物位于上述第一电性连接器与上述第二电性连接器之间。
在另一些实施例中，提供一种封装结构。上述封装结构包括装置管芯形成于第一基板之上，以及导电垫形成于上述装置管芯之上。上述封装结构包括介电层形成于上述导电垫之上，以及一导电层，形成于上述介电层之中且位于上述导电垫之上。上述导电垫电性连接至上述导电层。上述封装结构亦包括第一凸块下金属层形成于上述介电层之上，且上述凸块下金属层电性连接至上述导电层。上述封装结构还包括第一突出结构形成于上述第一凸块下金属层之上，以及第一电性连接器形成于上述第一突出结构之上。上述封装结构包括贯孔结构相邻于该装置管芯而形成，以及第二凸块下金属层形成于上述贯孔结构之下。上述封装结构亦包括第二突出结构形成于上述第二凸块下金属层之上，以及第二电性连接器形成于上述第二突出结构之上。
如本公开的另一些实施例所述的封装装置结构，其中当从俯视图观察时，上述第一突出结构与上述第二突出结构两者皆具有不连续形状，且上述不连续形状包括第一部分与第二部分，且相对于上述凸块下金属层的中心，上述第一部分与上述第二部分是对称的。
如本公开的另一些实施例所述的封装装置结构，其中当从俯视图观察时，上述第一突出结构与上述第二突出结构的每一者各自具有不连续同心环形状，且上述不连续同心环形状包括第一不连续环与第二不连续环。
如本公开的另一些实施例所述的封装装置结构，其中当从俯视图观察时，上述第一突出结构与上述第二突出结构两者皆位于上述第一基板的对角线上。
如本公开的另一些实施例所述的封装装置结构，其中上述第一突出结构的熔点高于上述第一电性连接器的熔点。
如本公开的另一些实施例所述的封装装置结构，还包括第二基板形成于上述第一电性连接器之上，以及第三基板形成于上述第二电性连接器之下。
在又一些实施例中，提供一种封装结构。上述封装结构包括第一装置管芯形成于第一基板之上，以及封装结构围绕上述第一装置管芯。上述封装结构亦包括导电层形成于上述第一装置管芯与上述封装层之上，以及多个第一电性连接器形成于上述第一装置管芯之上。上述第一电性连接器具有第一高度。上述封装结构包括多个第二电性连接器形成于上述封装层之上，且上述第二电性连接器具有大于上述第一高度的第二高度。上述封装结构亦包括第二装置管芯形成于上述第一电性连接器之上，以及多个突出结构埋设于上述第二电性连接器之中，其中上述突出结构延伸向上远离上述导电层。
如本公开的又一些实施例所述的封装装置结构，还包括第一凸块下金属层形成于上述第二电性连接器之下，其中上述突出结构的每一者各自具有外侧表面，且上述外侧表面对准于上述第一凸块下金属层的外侧表面。
如本公开的又一些实施例所述的封装装置结构，还包括贯孔结构相邻于上述第一装置管芯而形成，其中上述贯孔结构电性连接至上述导电层。
如本公开的又一些实施例所述的封装装置结构，还包括底部填充物，位于两个相邻的上述第一电性连接器之间。
如本公开的又一些实施例所述的封装装置结构，还包括气隙位于上述底部填充物与上述突出结构之间。
如本公开的又一些实施例所述的封装装置结构，还包括第二基板，形成于上述第二电性连接器之上，其中上述第二电性连接器电性连接至上述第二基板的导电垫。
以上概略说明了本公开数个实施例的特征，使本领域技术人员对于本公开的型态可更为容易理解。任何本领域技术人员应了解到可轻易利用本公开作为其它工艺或结构的设计或变更基础，以进行相同于此处所述实施例的目的和/或获得相同的优点。任何本领域技术人员也可理解与上述等同的结构并未脱离本公开的构思和保护范围内，且可在不脱离本公开的构思和范围内，当可作更动、替代与润饰。

Claims (1)

1.一种封装结构，包括︰
一介电层，形成于一第一基板之上；
一导电层，形成于该介电层之中；
一凸块下金属层，形成于该介电层之上，其中该凸块下金属层电性连接至该导电层；
一第一突出结构，形成于该凸块下金属层之上，其中该第一突出结构延伸向上远离该凸块下金属层；
一第二突出结构，形成于该凸块下金属层之上，其中该第二突出结构延伸向上远离该凸块下金属层；
一第一电性连接器，形成于该第一突出结构之上；以及
一第二电性连接器，形成于该第二突出结构之上，其中一气隙形成于该第一突出结构与该第二突出结构之间。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11166381B2 (en) * 2018-09-25 2021-11-02 International Business Machines Corporation Solder-pinning metal pads for electronic components
TWI725452B (zh) * 2019-06-20 2021-04-21 矽品精密工業股份有限公司 電子封裝件及其製法
KR20210058454A (ko) 2019-11-14 2021-05-24 삼성전자주식회사 반도체 패키지
CN112885800A (zh) * 2019-11-29 2021-06-01 长鑫存储技术有限公司 半导体结构及其制造方法
US11721642B2 (en) 2021-06-17 2023-08-08 Nxp Usa, Inc. Semiconductor device package connector structure and method therefor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6959856B2 (en) * 2003-01-10 2005-11-01 Samsung Electronics Co., Ltd. Solder bump structure and method for forming a solder bump
US7015590B2 (en) * 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
US7989356B2 (en) * 2009-03-24 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9583470B2 (en) * 2013-12-19 2017-02-28 Intel Corporation Electronic device with solder pads including projections
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same

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