TW201919194A - 封裝結構 - Google Patents

封裝結構 Download PDF

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Publication number
TW201919194A
TW201919194A TW107117735A TW107117735A TW201919194A TW 201919194 A TW201919194 A TW 201919194A TW 107117735 A TW107117735 A TW 107117735A TW 107117735 A TW107117735 A TW 107117735A TW 201919194 A TW201919194 A TW 201919194A
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TW
Taiwan
Prior art keywords
layer
protruding structure
substrate
metal layer
electrical connector
Prior art date
Application number
TW107117735A
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English (en)
Inventor
曹佩華
陳承先
朱立寰
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201919194A publication Critical patent/TW201919194A/zh

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Abstract

本發明實施例提供一種封裝結構。此封裝結構包括介電層形成於第一基板之上，以及導電層形成於介電層之中。此封裝結構包括凸塊下金屬層形成於介電層之上，且凸塊下金屬層電性連接至導電層。此封裝結構亦包括第一突出結構形成於凸塊下金屬層之上，且第一突出結構延伸向上遠離凸塊下金屬層。此封裝結構包括第二突出結構形成於凸塊下金屬層之上，且第二突出結構延伸向上遠離凸塊下金屬層。此封裝結構包括第一電性連接器形成於第一突出結構之上；以及第二電性連接器形成於第二突出結構之上。氣隙形成於第一突出結構與第二突出結構之間。

Description

封裝結構
本發明實施例是關於一種半導體結構，且特別是關於一種封裝結構及其形成方法。
半導體裝置使用於各種電子應用中，例如個人電腦、行動電話、數位相機和其他電子設備。半導體裝置通常藉由以下方式而製造，包括在半導體基板上依序沉積絕緣或介電層、導電層及半導體層，使用微影製程圖案化上述各材料層，藉以在此半導體基板上形成電路組件及元件。通常在單一半導體晶圓上製造許多積體電路，並且藉由沿著切割線在積體電路之間進行切割，以將各個晶粒單一化。上述各個晶粒通常分別地封裝於，例如，多晶片模組中或其他類型的封裝中。
已經開始發展新的封裝技術，例如，堆疊式封裝(package on package,PoP)，其中具有裝置晶粒的頂部封裝接合至具有另一個裝置晶粒的底部封裝。藉由採用新的封裝技術，將具有不同或相似功能的各種封裝整合在一起。
雖然現有的封裝結構與製造封裝結構的方法一般已足以勝任其預期目的，但其尚未全面滿足所有的面向。
根據一些實施例，本發明提供一種封裝結構，包括：介電層，形成於第一基板之上；導電層，形成於介電層之 中；凸塊下金屬層，形成於介電層之上，其中凸塊下金屬層電性連接至導電層；第一突出結構，形成於凸塊下金屬層之上，其中第一突出結構延伸向上遠離凸塊下金屬層；第二突出結構，形成於凸塊下金屬層之上，其中第二突出結構延伸向上遠離凸塊下金屬層；第一電性連接器，形成於第一突出結構之上；以及第二電性連接器，形成於第二突出結構之上，其中氣隙形成於第一突出結構與第二突出結構之間。
根據一些實施例，本發明提供一種封裝結構，包括：裝置晶粒，形成於第一基板之上；導電墊，形成於裝置晶粒之上；介電層，形成於導電墊之上；導電層，形成於介電層之中且位於導電墊之上，其中導電墊電性連接至導電層；第一凸塊下金屬層，形成於介電層之上，其中凸塊下金屬層電性連接至導電層；第一突出結構，形成於第一凸塊下金屬層之上；第一電性連接器，形成於第一突出結構之上；貫孔結構，相鄰於裝置晶粒而形成；第二凸塊下金屬層，形成於貫孔結構之下；第二突出結構，形成於第二凸塊下金屬層之上；以及第二電性連接器，形成於第二突出結構之上。
根據一些實施例，本發明提供一種封裝結構，包括：第一裝置晶粒，形成於第一基板之上；封裝結構，圍繞第一裝置晶粒；導電層，形成於第一裝置晶粒與封裝層之上；複數個第一電性連接器，形成於第一裝置晶粒之上，其中第一電性連接器具有第一高度；複數個第二電性連接器，形成於封裝層之上，其中第二電性連接器具有第二高度，且第二高度大於第一高度；第二裝置晶粒，形成於第一電性連接器之上；以及 複數個突出結構，埋設於第二電性連接器之中，其中突出結構延伸向上遠離導電層。
100a、100b、100c、100d、100e‧‧‧封裝結構
102‧‧‧基板
104‧‧‧裝置元件
106‧‧‧黏著層
108‧‧‧裝置晶粒
110‧‧‧層間介電層
120‧‧‧金屬層間介電層
122‧‧‧貫孔結構
122a‧‧‧第一表面
122b‧‧‧第二表面
123‧‧‧絕緣層
124‧‧‧鈍化層
130‧‧‧第一介電層
132‧‧‧導電墊
134‧‧‧後鈍化內連線墊
137‧‧‧開口
140‧‧‧第二介電層
142‧‧‧導電層
150‧‧‧保護層
150a‧‧‧第一次層
150b‧‧‧第二次層
152‧‧‧導電層
157‧‧‧開口
160‧‧‧凸塊下金屬層
162‧‧‧晶種層
164‧‧‧光阻層
165‧‧‧開口
166‧‧‧突出結構
166a‧‧‧第一突出結構
166a1‧‧‧第一部分
166a2‧‧‧第二部分
166b‧‧‧第二突出結構
166b1‧‧‧第一部分
166b2‧‧‧第二部分
167a1‧‧‧第一部分
167a2‧‧‧第二部分
167b1‧‧‧第一部分
167b2‧‧‧第二部分
168‧‧‧電性連接器
180‧‧‧凸塊下金屬層
182‧‧‧晶種層
186‧‧‧突出結構
188‧‧‧電性連接器
190‧‧‧氣隙
200‧‧‧第二封裝結構
202‧‧‧第二基板
204‧‧‧導電墊
300‧‧‧第三封裝結構
302‧‧‧第三基板
304‧‧‧導電墊
402‧‧‧承載基板
404‧‧‧黏著層
406‧‧‧基礎層
410‧‧‧內連線結構
412‧‧‧導電層
414‧‧‧鈍化層
415‧‧‧間隙
416‧‧‧貫孔結構
418‧‧‧黏著層
420‧‧‧封裝層
425‧‧‧溝槽
427‧‧‧開口
430‧‧‧凸塊下金屬層
432‧‧‧晶種層
436‧‧‧突出結構
438‧‧‧電性連接器
440‧‧‧凸塊下金屬層
442‧‧‧電性連接器
444‧‧‧底部填充物
450‧‧‧元件
500‧‧‧裝置晶粒
502‧‧‧半導體基板
504‧‧‧鈍化層
506‧‧‧導電墊
508‧‧‧鈍化層
510‧‧‧導電層
512‧‧‧保護層
514‧‧‧保護基板
516‧‧‧承載體
600‧‧‧第二封裝結構
602‧‧‧第二基板
604‧‧‧導電墊
C‧‧‧中心點
D‧‧‧中心點
d1‧‧‧第一距離
H1‧‧‧第一高度
H2‧‧‧第二高度
P1P2‧‧‧第一虛設中心線
P3P4‧‧‧第二虛設中心線
P5P6‧‧‧第三虛設中心線
P7P8‧‧‧第四虛設中心線
W1‧‧‧第一寬度
W2‧‧‧第二寬度
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1A圖到第1L圖繪示依據本發明之一些實施例之形成第一封裝結構之各個製程階段之剖面圖。
第2A圖繪示依據本發明之一些實施例之第一突出結構、第二突出結構及凸塊下金屬層之沿著第1L圖之I-I’剖線之俯視圖。
第2B圖繪示依據本發明之一些實施例之第1L圖之第一突出結構、第二突出結構、凸塊下金屬層及第一基板之俯視圖。
第3A圖繪示依據本發明之一些實施例之封裝結構之剖面圖。
第3B圖繪示依據本發明之一些實施例之第一突出結構、第二突出結構及凸塊下金屬層之沿著第3A圖之II-II’剖線之俯視圖。
第3C圖繪示依據本發明之一些實施例之第3A圖之第一突出結構、第二突出結構、凸塊下金屬層及第一基板之俯視圖。
第4A圖繪示依據本發明之一些實施例之封裝結構之剖面圖。
第4B圖繪示依據本發明之一些實施例之第一突出結構、第 二突出結構及凸塊下金屬層之沿著第4A圖之III-III’剖線之俯視圖。
第4C圖繪示依據本發明之一些實施例之第4A圖之第一突出結構、第二突出結構、凸塊下金屬層及第一基板之俯視圖。
第5A圖到第5C圖繪示依據本發明之一些實施例之形成第一封裝結構之各個製程階段之剖面圖。
第6A圖到第6H圖繪示依據本發明之一些實施例之形成第一封裝結構之各個製程階段之剖面圖。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同部件(feature)。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本說明書敘述了一第一部件形成於一第二部件之上或上方，即表示其可能包括上述第一部件與上述第二部件是直接接觸的實施例，亦可能包括了有附加部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與第二部件可能未直接接觸的實施例。另外，以下揭露的不同範例可能重複使用相同的參照符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
下文描述實施例的各種變化。藉由各種視圖與所繪示之實施例，類似的元件標號用於標示類似的元件。應可理解的是，可在進行所述的方法之前、之間或之後，提供額外的操作步驟，並且在所述的方法的其他實施例中，所述的部分步 驟可被變更順序、置換或省略。
以下提供封裝結構及其製造方法的實施例。第1A圖到第1L圖繪示依據本發明之一些實施例之形成第一封裝結構100a之各個製程階段之剖面圖。
請參照第1A圖，提供基板102。基板102可由矽或其他半導體材料所形成，例如鍺(Ge)。在一些實施例中，基板102為裝置晶粒的基板。在一些實施例中，基板102由化合物半導體所形成，例如，碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、砷化銦(indium arsenide)或磷化銦(or indium phosphide)。在一些實施例中，基板102由半導體材料、陶瓷材料、聚合物材料、金屬材料、其他合適的材料或上述之組合所形成。在一些實施例中，基板102為玻璃基板。在一些實施例中，基板102為半導體基板，例如，矽晶圓。
形成裝置元件(device element)104於基板102之上。裝置元件104包括電晶體(例如，金屬氧化物半導體場效電晶體(MOSFET)、互補式金屬氧化物半導體(CMOS)電晶體、雙極接面電晶體(bipolar junction transistors,BJT)、高壓電晶體、高頻電晶體、p-通道及/或n-通道場效應電晶體(PFET/NFET)等)、二極體及/或其他合適的元件。進行各種不同的製程(例如，沉積、蝕刻、佈植、光學微影、退火及/或其他合適的製程)，以形成各種不同的裝置元件104。在一些實施例中，裝置元件104於前段製程(front-end-of-line,FEOL)中形成於基板102中。
基板102可包括各種不同的摻雜區，例如，p型井 區或n型井區。摻雜區可摻雜p型摻雜物(例如，硼或二氟化硼離子(BF2))及/或n型摻雜物(例如，磷或砷)。摻雜區可直接形成基板102之中或之上，而位於p型井區結構、n型井區結構或雙井區結構之中。
基板102可進一步包括隔離部件(未繪示)，例如，淺溝槽隔離(STI)部件或矽局部氧化(local oxidation of silicon,LOCOS)部件。隔離部件可定義及隔離各種不同的裝置元件。
形成金屬層間介電(inter-metal dielectric,IMD)層120於層間介電(ILD)層110之上。金屬層間介電層120由氧化矽(SiOx)、氮化矽(SixNy)、氮氧化矽(SiON)、具有低介電常數(low-k)的介電材料或上述之組合所形成。在一些實施例中，金屬層間介電層120由極低介電常數(extreme low-k,ELK)介電材料所形成，其中極低介電常數介電材料具有低於約2.5的介電常數。在一些實施例中，極低介電常數介電材料包括摻雜碳的氧化矽(carbon doped silicon oxide)、非晶氟化碳(amorphous fluorinated carbon)、聚對二甲苯(parylen)、雙苯並環丁烯(bis-benzocyclobutenes,BCB)、聚四氟乙烯(polytetrafluoroethylene,PTFE)(鐵氟龍)或碳氧化矽聚合物(silicon oxycarbide polymers,SiOC)。在一些實施例中，極低介電常數介電材料包括多孔形式的現有介電材料，例如，氫倍半矽氧烷(hydrogen silsesquioxane,HSQ)、多孔甲基倍半矽氧烷(porous methyl silsesquioxane,MSQ)、多孔聚芳醚(porous polyarylether,PAE)、多孔SiLK(porous SiLK)或多孔二氧化矽(SiO2)。在一些實施例中，藉由電漿增強化學氣相沉積(plasma enhanced CVD,PECVD)製程或旋轉塗佈(spin coating)製程，以沉積金屬層間介電層120。
形成導電墊132於金屬層間介電層120之上。導電墊132經由金屬層間介電層120之中的各種不同金屬導線及介層窗(via)而電性連接至裝置元件104。
在後段製程(back-end-of-line,BEOL)中形成金屬層間介電層120及導電墊132。導電墊132由銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金所形成。在一些實施例中，藉由電鍍法(plating)形成導電墊132。
形成鈍化層124於金屬層間介電層120之上，且覆蓋導電墊132的邊緣部分。另外，露出導電墊132的中心部分。在一些實施例中，鈍化層124由非有機材料(non-organic materials)所形成，例如，氧化矽、未摻雜矽玻璃(un-doped silicate glass)、氮氧化矽、阻焊劑(solder resist,SR)、氮化矽或六甲基二矽氮烷(hexamethyldisilazane,HMDS)。在一些實施例中，鈍化層124由聚合物材料所形成，例如，聚醯亞胺(polyimide,PI)、環氧化物或含氟聚合物材料。
之後，根據本發明一些實施例，如第1B圖所繪示，在形成鈍化層124之後，形成第一介電層130於鈍化層124之上。
之後，藉由圖案化製程將第一介電層130圖案化，而露出一部分的導電墊132。圖案化製程包括微影製程與蝕刻製程。微影製程的範例包括光阻塗佈、軟烘烤(soft baking)、光罩對準(mask aligning)、曝光(exposure)、曝光後烘烤 (post-exposure baking)、顯影(developing)光阻、潤洗(rising)、乾燥(例如，硬烘烤(hard baking))。蝕刻製程包括乾式蝕刻製程或濕式蝕刻製程。
在一些實施例中，第一介電層130由氧化矽、氮化矽、氮氧化矽或其他合適的材料所形成。形成後鈍化內連線(post-passivation interconnect,PPI)墊134於第一介電層130內，且電性連接至導電墊132。後鈍化內連線墊134在形成鈍化層124之後形成。在一些實施例中，後鈍化內連線墊134稱為重分佈(redistribution layer,RDL)墊。
後鈍化內連線墊134由導電材料所形成，例如，銅、銅合金、鋁、鋁合金、鎢、鎢合金、鈦、鈦合金、鉭或鉭合金。藉由電鍍、無電電鍍(electroless plating)、濺鍍(sputtering)或化學氣相沉積，以形成後鈍化內連線墊134。
藉由將導電材料(例如，金屬材料)填入開口之中且沉積於第一介電層130之上，以形成後鈍化內連線墊134。之後，藉由化學機械研磨(chemical mechanical polishing,CMP)製程移除多餘的導電材料。
之後，根據本發明一些實施例，如第1C圖所繪示，在形成後鈍化內連線墊134之後，形成第二介電層140於第一介電層130及後鈍化內連線墊134之上。第二介電層140由聚苯並噁唑(polybenzoxazole,PBO)、雙-苯並環丁烯(BCB)、矽膠(silicone)、丙烯酸酯(acrylates)、矽氧烷(siloxane)或上述之組合所形成。
在形成第二保護層140之後，藉由圖案化製程將第 二保護層140圖案化，以形成開口137。因此，露出至少一部分的後鈍化內連線墊134。
之後，根據本發明一些實施例，如第1D圖所繪示，形成導電層142於開口137之中及第二介電層140之上。導電層142電性連接至後鈍化內連線墊134。導電層142是用以電性連接至基板102的不同區域。
導電層142由導電材料所形成，例如，銅、銅合金、鋁、鋁合金、鎢、鎢合金、鈦、鈦合金、鉭)或鉭合金。藉由電鍍、無電電鍍、濺鍍或化學氣相沉積，以形成導電層142。
之後，根據本發明一些實施例，如第1E圖所繪示，在形成導電層142之後，形成保護層150。之後，將保護層150圖案化，以形成開口157。藉由開口157露出一部分的導電層142。
形成保護層150於裝置元件104之上，以防止水氣穿透，進而導致下方的保護層及後鈍化內連線結構發生剝離。所形成的保護層150有助於封裝結構100a能夠經過嚴苛環境(例如，各種不同的可靠度測試)而沒有任何水氣能夠透入。
在一些實施例中，保護層150包括無機材料，例如，氮化矽、氧化矽、氮氧化矽、六甲基二矽氮烷或上述之組合。另外，保護層150包括聚合物材料，例如，聚醯亞胺、環氧化物、阻焊劑、含氟聚合物材料或上述之組合。
之後，根據本發明一些實施例，如第1F圖所繪示，在形成開口157之後，形成凸塊下金屬(under bump metallurgy,UBM)層160於保護層150之中。
凸塊下金屬層160由導電材料所形成，例如，銅、銅合金、鋁、鋁合金、鎢、鎢合金、鈦、鈦合金、鉭或鉭合金。另外，凸塊下金屬層160可包括黏著層及/或潤濕層(wetting layer)。在一些實施例中，凸塊下金屬層160更包括銅晶種層(seed layer)。在一些實施例中，凸塊下金屬層160包括由鈦/銅所形成之黏著層，以及由銅所形成之潤濕層。
之後，根據本發明一些實施例，如第1G圖所繪示，順應性地形成晶種層162於保護層150與凸塊下金屬層160之上。晶種層162由金屬材料所形成，例如，銅、鈦、銅合金、鈦合金或上述之組合。在一些實施例中，藉由沉積製程形成晶種層162，例如，化學氣相沉積製程、物理氣相沉積製程、其他合適的製程或上述之組合。
之後，根據本發明一些實施例，如第1H圖所繪示，形成光阻層164於晶種層162之上，並且將光阻層164圖案化，以形成複數個開口165。如此一來，暴露一部分的晶種層162。
之後，根據本發明一些實施例，如第1I圖所繪示，形成導電材料於開口165之中且位於晶種層162之上，以形成複數個突出結構(protrusion structure)166。突出結構166向上延伸遠離凸塊下金屬層160。更具體而言，突出結構166從晶種層162的頂表面向上延伸至高於凸塊下金屬層160的位置。
使用突出結構166作為裂縫停止結構(crack-stop structure)，以抑制在電性連接器168(繪示於第1K圖中)之中的裂縫之傳播。此外，突出結構166用以避免裂縫的形成。
之後，根據本發明一些實施例，如第1J圖所繪示， 移除光阻層164，並且移除一部分的晶種層162。如此一來，突出結構166包括第一突出結構166a與第二突出結構166b。
第一突出結構166a包括第一部分166a1與第二部分166a2，且第二突出結構166b包括第一部分166b1與第二部分166b2。每一個第一突出結構166a與第二突出結構166b各自的外側表面對準於凸塊下金屬層160的外側表面。
在一些實施例中，突出結構166a、166b的每一者各自由銅、銅合金、鋁、鋁合金、鎢、鎢合金、鈦、鈦合金、鉭或鉭合金所形成。在一些實施例中，使用電鍍法形成突出結構166。
突出結構166沿著垂直方向具有第一高度H1，且沿著水平方向具有第一寬度W1。在一些實施例中，第一高度H1為約10μm至約50μm的範圍。在一些實施例中，第一寬度W1為約20μm至約40μm的範圍。
之後，根據本發明一些實施例，如第1K圖所繪示，形成複數個電性連接器168於突出結構166之上。電性連接器168直接形成於凸塊下金屬層160與突出結構166之上。第一突出結構166a與第二突出結構166b各自獨立地埋設於電性連接器168之中。每一個第一突出結構166a的外側表面與每一個第二突出結構166b的外側表面實質上對準於電性連接器168的外側表面。
每一個第一突出結構166a與每一個第二突出結構166b的熔點高於每一個電性連接器168的熔點。每一個電性連接器168由具有低電阻值的導電材料所形成，例如，焊料或焊 料合金。包括於焊料合金中的之範例元素可包括錫(Sn)、鉛(Pb)、銀(Ag)、銅、鎳(Ni)、鉍(Bi)或上述之組合。
每一個電性連接器168具有第二高度H2，其中第二高度H2是量測從保護層150的頂表面到電性連接器168的頂表面而得。在一些實施例中，第二高度H2為約150μm至約200μm的範圍。在一些實施例中，第一高度H1對第二高度H2的高度比率(H1/H2)為約1/20至約1/3的範圍。如果高度比率太小，則突出結構166a、166b不夠高而無法使裂縫停止。如果高度比率太大，則可能很難形成電性連接器168於凸塊下金屬層160之上。電性連接器168沿著水平方向具有第二寬度W2。在一些實施例中，第二寬度W2為約180μm至約200μm的範圍。
之後，根據本發明一些實施例，如第1L圖所繪示，形成第二封裝結構200於第一封裝結構100a之上。第二封裝結構200包括形成於第二基板202之上的導電墊204。一些裝置元件(未繪示)形成於第二基板202之中。藉由電性連接器168與導電墊204，以接合第一封裝結構100a與第二封裝結構200。
形成氣隙(air gap)190於第一突出結構166a與第二突出結構166b之間。需注意的是，並無底部填充物(underfill)位於第一突出結構166a與第二突出結構166b之間。因為第一突出結構166a與第二突出結構166b能夠抑制裂縫或避免裂縫形成，所以不需要使用功能為降低裂縫的底部填充物。因此，能夠降低製程時間與成本。
需注意的是，當晶粒(例如，基板102)的尺寸變大時，集中在電性連接器的應力將變大。如此一來，會有一些裂 縫形成於電性連接器之中。使用突出結構166作為應力停止結構，以抑制在電性連接器168之中的裂縫之傳播。由於抑制電性連接器168中的裂縫，因而能夠提升封裝結構100a之效能與可靠度。
第2A圖繪示依據本發明之一些實施例之第一突出結構166a、第二突出結構及凸塊下金屬層160之沿著第1L圖之I-I’剖線之俯視圖。
當從俯視圖觀察時，第一突出結構166a具有不連續形狀(non-continuous shape)，且具有第一部分166a1與第二部分166a2。每一個第一部分166a1與第二部分166a2各自具有弓形結構(bow-shaped structure)。當從俯視圖觀察時，電性連接器168具有圓形形狀。需注意的是，如果第一突出結構166a包括連續的環，則可能會在電性連接器168中形成空孔(void)。因此，第一突出結構166a並不包括連續的環狀部分(continuous ring portion)。
在凸塊下金屬層160之中有中心點C。相對於凸塊下金屬層160的中心點C，第一部分166a1與第二部分166a2是對稱的。第一虛設中心線P1P2穿越第一突出結構166a的第一部分166a1。第二虛設中心線P3P4穿越第一突出結構166a的第二部分166a2。第一虛設中心線P1P2與第二虛設中心線P3P4兩者是對稱軸。第一虛設中心線P1P2與第二虛設中心線P3P4兩者穿越凸塊下金屬層160的中心點C。
需注意的是，第一虛設中心線P1P2與第二虛設中心線P3P4兩者是用以定義第一部分166a1與第二部分166a2之形 狀，且兩者並非真實存在的線。
同樣的，第二突出結構166b具有第一部分166b1與第二部分166b2。相對於凸塊下金屬層160的中心點C，第二突出結構166b的第一部分166b1與第二部分166b2是對稱的。第一部分166b1的第三虛設中心線P5P6與第二部分166a2的第四虛設中心線P7P8兩者穿越凸塊下金屬層160的中心點C。
如第2A圖所繪示，第一突出結構166a的第一部分166a1與第二部分166a2的長度總和，相對於電性連接器168的圓周長的長度比率為約1/3至約1/2的範圍。若比率不在上述範圍內，則第一突出結構166a可能無法抑制在電性連接器168之中的裂縫之傳播。
第2B圖繪示依據本發明之一些實施例之第1L圖之第一突出結構166a、第二突出結構166b、凸塊下金屬層160及第一基板102之俯視圖。繪示於第2A圖中的a1a1’線可以是第2B圖中的a1a1’線、a2a2’線、a3a3’線或a4a4’線。
當從俯視圖觀察時，基板102具有矩形形狀。在一些實施例中，基板102是晶粒的基板。基板102具有中心點D。有複數個電性連接器168形成於基板102之上。雖然第2B圖繪示8個電性連接器168，但是，依據實際應用，電性連接器168的數量可大於8個。在一些實施例中，基板102是晶粒，其面積為約5*5mm2至約7*7mm2的範圍。
a1a1’線、a2a2’線、a3a3’線及a4a4’線穿過基板102(或晶粒)的中心點D。換言之，a1a1’線、a2a2’線、a3a3’線及a4a4’線從基板102的中心點輻射散出。應力可能集中於電性連接器 168上，特別是，位於對角位置的應力。因此，第一突出結構166a與第二突出結構166b設置在相會於基板102的中心點D之水平線、垂直線或對角線上。
繪示於第2A圖的電性連接器168可以是繪示於第2B圖的沿著a1a1’線之編號1與編號8的兩個電性連接器168。再者，第一突出結構166a的第一部分166a1的第一虛設中心線P1P2，以及第一突出結構166a的第二部分166a2的第二虛設中心線P3P4穿過基板102的中心點D。
在一些實施例中，繪示於第2A圖的電性連接器168可以是繪示於第2B圖的沿著a4a4’線之編號2與編號7的兩個電性連接器168。在一些其他實施例中，繪示於第2A圖的電性連接器168可以是繪示於第2B圖的沿著a2a2’線之編號4與編號5的兩個電性連接器168。在一些其他實施例中，繪示於第2A圖的電性連接器168可以是繪示於第2B圖沿著a3a3’線之編號6與編號3的兩個電性連接器168。
第3A圖繪示依據本發明之一些實施例之封裝結構100b之剖面圖。第3A圖類似於第1L圖，在第3A圖中，每一個第一突出結構166a與第二突出結構166b的外側表面並未對準於凸塊下金屬層160的外側表面。介於凸塊下金屬層160的外側表面與第一突出結構166a的外側表面之間的距離為第一距離d1。在一些實施例中，第一距離d1為約0.1μm至約50μm的範圍。
第3B圖繪示依據本發明之一些實施例之第一突出結構166a、第二突出結構166b及凸塊下金屬層160之沿著第3A 圖之II-II’剖線之俯視圖。第一突出結構166a包括第一部分166a1與第二部分166a2。相對於凸塊下金屬層160的中心點C，第一突出結構166a的第一部分166a1與第二部分166a2是對稱的。第一部分166a1的第一虛設中心線P1P2與第二部分166a2第二虛設中心線P3P4兩者穿過凸塊下金屬層160的中心點C。
第3C圖繪示依據本發明之一些實施例之第3A圖之第一突出結構166a、第二突出結構166b、凸塊下金屬層160及第一基板102之俯視圖。繪示於第3B圖的a1a1’線可以是繪示於第3B圖的a1a1’線、a2a2’線、a3a3’線或a4a4’線。當從俯視圖觀察時，基板102具有矩形形狀。在一些實施例中，基板102是晶粒的基板。有複數個電性連接器168形成於基板102之上。a1a1’線、a2a2’線、a3a3’線及a4a4’線穿過基板102的中心點D。
第4A圖繪示依據本發明之一些實施例之封裝結構100c之剖面圖。第4B圖繪示依據本發明之一些實施例之第一突出結構166a、第二突出結構166b及凸塊下金屬層160之沿著第4A圖之III-III’剖線之俯視圖。第4C圖繪示依據本發明之一些實施例之第4A圖之第一突出結構166a、第二突出結構166b、凸塊下金屬層160及第一基板102之俯視圖。
如第4A圖與第4B圖所繪示，第一突出結構166a包括第一不連續同心環(non-continuous concentric ring)與第二不連續同心環。第一不連續同心環包括第一部分166a1與第二部分166a2，第二不連續同心環包括第一部分167a1與第二部分167a2。第二不連續同心環比第一不連續同心環更靠近凸塊下金屬層160的中心點C。第一不連續同心環的第一部分166a1的 外側表面對準於凸塊下金屬層160的外側表面，但是第二不連續同心環的第一部分167a1的外側表面並未對準於凸塊下金屬層160的外側表面。在電性連接器168之中的裂縫可以有效地被這兩個不連續環所抑制。
如第4C圖所繪示，繪示於第4B圖中的a1a1’線可以是繪示於第4C圖中的a1a1’線、a2a2’線、a3a3’線或a4a4’線。在一些實施例中，基板102是晶粒的基板。有複數個電性連接器168形成於基板102之上。a1a1’線、a2a2’線、a3a3’線及a4a4’線穿過基板102的中心點D。
第5A圖到第5C圖繪示依據本發明之一些實施例之形成第一封裝結構100d之各個製程階段之剖面圖。
如第5A圖所繪示，形成黏著層106於基板102之上，且形成裝置晶粒108於黏著層106之上。形成貫孔結構(through via structure)122相鄰於裝置晶粒108。絕緣層123圍繞貫孔結構122的側壁，且分隔貫孔結構122與裝置晶粒108。在一些實施例中，絕緣層123包括氧化矽、氮化矽、貫孔結構122的氧化物、模製化合物(molding compound)或上述之組合。
貫孔結構122用以連結至其他封裝結構。貫孔結構122由銅、金、銀或其他合適的材料所形成。
保護層150包括第一次層(first sub-layer)150a與第二次層(second sub-layer)150b，用於使多於一層的導電層能夠形成於保護層150之中。在一些實施例中，第一次層150a與第二次層150b由不同材料所形成。
導電層152形成於保護層150之中且電性連結至導 電層142。凸塊下金屬層160形成於導電層152之上。晶種層162形成於凸塊下金屬層160之上，且突出結構166形成於晶種層162之上。
之後，根據本發明一些實施例，如第5B圖所繪示，形成電性連接器168於突出結構166之上。形成第二封裝結構200於第一封裝結構100d之上。第二封裝結構200包括形成於第二基板202之上的導電墊204。一些裝置元件(未繪示)形成於第二基板202之中。藉由電性連接器168與導電墊204，以接合第一封裝結構100d與第二封裝結構200。形成氣隙190於第一突出結構166a與第二突出結構166b之間。並無底部填充物位於第一突出結構166a與第二突出結構166b之間。
之後，根據本發明一些實施例，如第5C圖所繪示，溝槽(未繪示)形成於基板102之中，且接著形成凸塊下金屬層180於溝槽之中。貫孔結構122具有第一表面122a，以及相對於第一表面122a的第二表面122b。第一表面122a直接接觸導電層142，且第二表面122b直接接觸凸塊下金屬層180。形成晶種層182於凸塊下金屬層180之上，並且形成突出結構186於晶種層182之上。形成電性連接器188於凸塊下金屬層180與突出結構186之上。
形成第三封裝結構300於第一封裝結構100d之上。第三封裝結構300包括形成於第三基板302之上的導電墊304。藉由電性連接器188與導電墊304，以接合第一封裝結構100d與第三封裝結構300。第二封裝結構200與第三封裝結構300位於基板102的相對兩側上。
第6A圖到第6H圖繪示依據本發明之一些實施例之形成第一封裝結構100e之各個製程階段之剖面圖。
如第6A圖所繪示，形成黏著層404於承載基板402之上。在一些實施例中，使用承載基板402作為暫時基板。此暫時基板在後續的製程步驟期間提供機械性和結構性的支撐，其將在後續更加詳細描述。承載基板402由半導體材料、陶瓷材料、聚合物材料、金屬材料、其他合適的材料或上述之組合所形成。在一些實施例中，承載基板402為半導體基板，例如，矽晶圓。
設置黏著層404於承載基板402之上。黏著層404可由黏膠所形成，或者可為積層材料(lamination material)，例如，金屬箔(foil)。在一些實施例中，黏著層404為感光性的(photosensitive)，且容易藉由光照射而從承載基板402脫離。舉例而言，將紫外光或雷射光照射至承載基板402上，可分離黏著層404。在一些其他實施例中，黏著層404為感熱性的(heat-sensitive)，且當暴露於熱時，黏著層404容易從承載基板402脫離。
之後，依據本發明一些實施例，將基礎層(base layer)406沉積或貼合至黏著層404之上。基礎層406提供用於接合積體電路晶粒之結構性的支撐，其將在後續更加詳細描述，且基礎層406有助減少晶粒偏移(die shifting)的問題。在一些實施例中，基礎層406為聚合物層或含聚合物層。基礎層406可為聚對伸苯基苯並雙噻唑(poly-p-phenylenebenzobisthiazole,PBO)層、聚醯亞胺層、阻焊劑層、味之素增層膜(Ajinomoto buildup film,ABF)、晶粒貼附膜(die attach film,DAF)、其他合適的膜層或上述之組合。
形成內連線結構410於基礎層406之上。內連線結構410包括一或多個導電層位於一或多個鈍化層之中。舉例而言，內連線結構410包括導電層412形成於鈍化層414之中。
之後，根據本發明一些實施例，複數個貫孔結構416形成內連線結構410之上。貫孔結構416包括導電柱(conductive pillar)或其他合適的結構。貫孔結構416可被稱為中介層貫孔(through interposer vias,TIVs)。貫孔結構416物理性且電性連接至內連線結構410的其中一個導電層。
在一些實施例中，貫孔結構416由一材料所形成，此材料可包括銅、鋁、鎳、鉑、無鉛焊料(例如，錫銀(SnAg)、錫銅(SnCu)、錫銀銅(SnAgCu))、其他合適的導電材料或上述之組合。在一些實施例中，使用電鍍製程、物理氣相沉積製程、化學氣相沉積製程、電化學沉積(electrochemical deposition,ECD)製程、分子束磊晶(molecular beam epitaxy,MBE)製程、原子層沉積製程或其他合適的製程，以形成貫孔結構416。
之後，根據本發明一些實施例，如第6B圖所繪示，藉由黏著層418將裝置晶粒500設置於內連線結構410之上。在一些實施例中，裝置晶粒500的前側(主動表面(active surface))面向遠離內連線結構410的方向。裝置晶粒500的背側(非主動表面(non-active surface))面向內連線結構410。裝置晶粒500可為包括電晶體、二極體或其他合適之積體電路元件的裝置晶粒。裝置晶粒也可包括電容、電感、電阻、其他積體電路元件 或上述之組合。
在一些實施例中，裝置晶粒500包括半導體基板502、鈍化層504及導電墊506。裝置晶粒500也可包括位於導電墊506上的連接器，以及圍繞連接器的保護層。各種裝置元件可形成於半導體基板502之中或之上。
黏著層418用以將裝置晶粒500接合或貼附到內連線結構410。黏著層418包括晶粒貼附膜、其他合適的膜層或上述之組合。
之後，沉積封裝層420於內連線結構410之上。因此，可藉由封裝層240封裝貫孔結構416及裝置晶粒500。在一些實施例中，封裝層420包括聚合物材料。在一些實施例中，封裝層420包括模製化合物。
在一些實施例中，塗佈模製化合物於貫孔結構416、裝置晶粒500及內連線結構410之上，且進行熱處理製程以將模製化合物硬化。在平坦化製程之後，裝置晶粒500的頂表面實質上與貫孔結構416的頂表面等高。在一些實施例中，平坦化製程包括研磨(grinding)製程、化學機械研磨製程、蝕刻製程、其他合適的製程或上述之組合。
之後，根據本發明一些實施例，如第6C圖所繪示，形成鈍化層508於封裝層420之上，並且形成導電層510於鈍化層508之中。形成保護層512於鈍化層508之上，並且形成保護基板514於保護層512之上。
在一些實施例中，保護基板514用作指紋辨識(fingerprint recognition)裝置的面板。保護基板514由非有機材 料或其他合適的材料所形成。在一些實施例中，保護基板514為玻璃基板、藍寶石基板或其他合適的基板。
之後，根據本發明一些實施例，如第6D圖所繪示，將第6C圖繪示的結構翻轉並且貼附至承載體(carrier)516。載板516包括感光性或感熱性的膠帶，且其容易從保護基板514脫離。
將承載基板402移除。在一些實施例中，移除承載基板402及黏著層404兩者。可提供合適的光源，以移除黏著層404，並且移除承載基板402。
之後，移除基礎層406的多個部分，以形成複數個溝槽425與複數個開口427。溝槽425與開口427暴露出部分的內連線結構410，例如，部分的導電層412。溝槽425位於貫孔結構416之上，且開口427位於裝置晶粒500之上。溝槽425的尺寸大於開口427的尺寸。舉例而言，溝槽425的寬度大於開口427的寬度。
之後，根據本發明一些實施例，如第6E圖所繪示，形成凸塊下金屬層430於溝槽425之中，並且形成凸塊下金屬層440於開口427之中。形成晶種層432於凸塊下金屬層430之中，並且形成突出結構436於晶種層432之上。
之後，根據本發明一些實施例，如第6F圖所繪示，形成電性連接器438於凸塊下金屬層430與突出結構436之上。電性連接器438藉由凸塊下金屬層430而電性連接至導電層412。
之後，根據本發明一些實施例，如第6G圖所繪示， 將元件450堆疊於內連線結構410之上。元件450與裝置晶粒500位於基礎層406的相對兩側。元件450的尺寸小於裝置晶粒500的尺寸。更具體而言，元件450的寬度小於裝置晶粒500的寬度。形成凸塊下金屬層440於開口427之中，並且形成複數個電性連接器442於凸塊下金屬層440之上。形成元件450於電性連接器442之上。間隙(space)415位於相鄰的兩個電性連接器442之間。每一個電性連接器438的尺寸大於每一個電性連接器442的尺寸。更具體而言，每一個電性連接器438的高度大於每一個電性連接器442的高度。
在一些實施例中，元件450為裝置晶粒。舉例而言，此裝置晶粒為高電壓晶粒(high-voltage die)或其他合適的晶粒。在一些其他實施例中，元件450包括封裝結構，此封裝結構含有一個或多個積體電路晶粒。
之後，根據本發明一些實施例，如第6H圖所繪示，形成第二封裝結構600於第一封裝結構100e之上。第二封裝結構600包括導電墊604形成於第二基板602上。一些裝置元件(未繪示)形成於第二基板602之上。第一封裝結構100e與第二封裝結構600藉由電性連接器438與導電墊604接合在一起。在一些實施例中，移除承載體516，以暴露出保護基板514。
如第6H圖所繪示，底部填充物444填滿間隙415。因此，底部填充物444位於相鄰的兩個電性連接器442之間。需注意的是，並無底部填充物位於相鄰的兩個電性連接器436之間。氣隙190形成於底部填充物444與電性連接器438之間。
需注意的是，當晶粒的尺寸變大時，集中在電性 連接器的應力將變大。因此，集中在電性連接器438的應力大於集中在電性連接器442的應力。高應力可能造成裂縫形成於電性連接器之中。為了降低或避免裂縫的形成，埋設突出結構436於電性連接器438之中。在一些實施例中，每一個突出結構436的外側表面對準於凸塊下金屬層440與電性連接器438的外側表面，以適當地抑制在電性連接器438中裂縫之傳播。
本發明提供封裝結構及其形成方法的實施例。第一封裝結構包括導電層形成於基板或是晶粒上，以及凸塊下金屬層形成於上述導電層之上。晶種層形成於上述凸塊下金屬層之上，且複數個突出結構形成於上述晶種層之上。複數個電性連接器形成於上述突出結構之上。上述突出結構延伸遠離於上述凸塊下金屬層。上述突出結構包括第一突出結構與第二突出結構。氣隙位於上述第一突出結構與上述第二突出結構之間。並無底部填充物位於上述第一突出結構與上述第二突出結構之間。上述突出結構作為裂縫停止結構，以避免在上述電性連接器中形成裂縫。因此，能夠減少電性連接器裂縫的問題，並且提升封裝結構的效能與可靠度。
在一些實施例中，提供一種封裝結構。上述封裝結構包括介電層形成於第一基板之上，以及導電層形成於上述介電層之中。上述封裝結構包括凸塊下金屬層形成於上述介電層之上，且上述凸塊下金屬層電性連接至上述導電層。上述封裝結構亦包括第一突出結構形成於上述凸塊下金屬層之上，且上述第一突出結構延伸向上遠離上述凸塊下金屬層。上述封裝結構更包括第二突出結構形成於上述凸塊下金屬層之上，且上 述第二突出結構延伸向上遠離上述凸塊下金屬層。上述封裝結構包括第一電性連接器形成於上述第一突出結構之上；以及第二電性連接器形成於上述第二突出結構之上。氣隙形成於上述第一突出結構與上述第二突出結構之間。
如本發明的一些實施例所述之封裝裝置結構，其中上述第一突出結構具有外側表面，且上述外側表面對準於上述凸塊下金屬層的外側表面。
如本發明的一些實施例所述之封裝裝置結構，其中當從俯視圖觀察時，上述第一突出結構具有不連續形狀，且上述不連續形狀包括第一部分及第二部分，且相對於上述凸塊下金屬層的中心，上述第一部分與上述第二部分是對稱的。
如本發明的一些實施例所述之封裝裝置結構，其中當從俯視圖觀察時，上述第一突出結構具有不連續形狀，且上述不連續形狀包括第一不連續環及第二不連續環。
如本發明的一些實施例所述之封裝裝置結構，上述第一突出結構的熔點高於上述第一電性連接器的熔點。
如本發明的一些實施例所述之封裝裝置結構，更包括第二基板形成於上述第一電性連接器與上述第二電性連接器之上，且上述第一電性連接器電性連接至上述第二基板的一導電墊。
如本發明的一些實施例所述之封裝裝置結構，更包括裝置晶粒形成於上述第一基板之上；貫孔結構相鄰於上述裝置晶粒而形成；以及第三基板位於上述貫孔結構之下，其中上述貫孔結構電性連接至上述第三基板的一導電墊。
如本發明的一些實施例所述之封裝裝置結構，其中並無底部填充物位於上述第一電性連接器與上述第二電性連接器之間。
在另一些實施例中，提供一種封裝結構。上述封裝結構包括裝置晶粒形成於第一基板之上，以及導電墊形成於上述裝置晶粒之上。上述封裝結構包括介電層形成於上述導電墊之上，以及一導電層，形成於上述介電層之中且位於上述導電墊之上。上述導電墊電性連接至上述導電層。上述封裝結構亦包括第一凸塊下金屬層形成於上述介電層之上，且上述凸塊下金屬層電性連接至上述導電層。上述封裝結構更包括第一突出結構形成於上述第一凸塊下金屬層之上，以及第一電性連接器形成於上述第一突出結構之上。上述封裝結構包括貫孔結構相鄰於該裝置晶粒而形成，以及第二凸塊下金屬層形成於上述貫孔結構之下。上述封裝結構亦包括第二突出結構形成於上述第二凸塊下金屬層之上，以及第二電性連接器形成於上述第二突出結構之上。
如本發明的另一些實施例所述之封裝裝置結構，其中當從俯視圖觀察時，上述第一突出結構與上述第二突出結構兩者皆具有不連續形狀，且上述不連續形狀包括第一部分與第二部分，且相對於上述凸塊下金屬層的中心，上述第一部分與上述第二部分是對稱的。
如本發明的另一些實施例所述之封裝裝置結構，其中當從俯視圖觀察時，上述第一突出結構與上述第二突出結構的每一者各自具有不連續同心環形狀，且上述不連續同心環 形狀包括第一不連續環與第二不連續環。
如本發明的另一些實施例所述之封裝裝置結構，其中當從俯視圖觀察時，上述第一突出結構與上述第二突出結構兩者皆位於上述第一基板之對角線上。
如本發明的另一些實施例所述之封裝裝置結構，其中上述第一突出結構的熔點高於上述第一電性連接器的熔點。
如本發明的另一些實施例所述之封裝裝置結構，更包括第二基板形成於上述第一電性連接器之上，以及第三基板形成於上述第二電性連接器之下。
在又一些實施例中，提供一種封裝結構。上述封裝結構包括第一裝置晶粒形成於第一基板之上，以及封裝結構圍繞上述第一裝置晶粒。上述封裝結構亦包括導電層形成於上述第一裝置晶粒與上述封裝層之上，以及複數個第一電性連接器形成於上述第一裝置晶粒之上。上述第一電性連接器具有第一高度。上述封裝結構包括複數個第二電性連接器形成於上述封裝層之上，且上述第二電性連接器具有大於上述第一高度的第二高度。上述封裝結構亦包括第二裝置晶粒形成於上述第一電性連接器之上，以及複數個突出結構埋設於上述第二電性連接器之中，其中上述突出結構延伸向上遠離上述導電層。
如本發明的又一些實施例所述之封裝裝置結構，更包括第一凸塊下金屬層形成於上述第二電性連接器之下，其中上述突出結構的每一者各自具有外側表面，且上述外側表面對準於上述第一凸塊下金屬層的外側表面。
如本發明的又一些實施例所述之封裝裝置結構，更包括貫孔結構相鄰於上述第一裝置晶粒而形成，其中上述貫孔結構電性連接至上述導電層。
如本發明的又一些實施例所述之封裝裝置結構，更包括底部填充物，位於兩個相鄰的上述第一電性連接器之間。
如本發明的又一些實施例所述之封裝裝置結構，更包括氣隙位於上述底部填充物與上述突出結構之間。
如本發明的又一些實施例所述之封裝裝置結構，更包括第二基板，形成於上述第二電性連接器之上，其中上述第二電性連接器電性連接至上述第二基板的導電墊。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於本發明的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本發明作為其它製程或結構的設計或變更基礎，以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本發明之精神和保護範圍內，且可在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。

Claims (1)

  1. 一種封裝結構，包括：一介電層，形成於一第一基板之上；一導電層，形成於該介電層之中；一凸塊下金屬層，形成於該介電層之上，其中該凸塊下金屬層電性連接至該導電層；一第一突出結構，形成於該凸塊下金屬層之上，其中該第一突出結構延伸向上遠離該凸塊下金屬層；一第二突出結構，形成於該凸塊下金屬層之上，其中該第二突出結構延伸向上遠離該凸塊下金屬層；一第一電性連接器，形成於該第一突出結構之上；以及一第二電性連接器，形成於該第二突出結構之上，其中一氣隙形成於該第一突出結構與該第二突出結構之間。
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