CN107946277B - 半导体装置以及半导体装置制造方法 - Google Patents

半导体装置以及半导体装置制造方法 Download PDF

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CN107946277B
CN107946277B CN201710664688.7A CN201710664688A CN107946277B CN 107946277 B CN107946277 B CN 107946277B CN 201710664688 A CN201710664688 A CN 201710664688A CN 107946277 B CN107946277 B CN 107946277B
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semiconductor device
molding compound
seed layer
conductor
package
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CN107946277A (zh
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林俊成
施应庆
王卜
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露提供一种半导体装置以及半导体装置制造方法。所述半导体装置包含：底部封装，其中在导体与贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积，且所述底部封装包含：模塑料；贯穿通路，其穿透所述模塑料；裸片，其模制在所述模塑料中；和导体，其在所述贯穿通路上。本揭露还揭示一种制造半导体装置的相关联方法。

Description

半导体装置以及半导体装置制造方法
技术领域
本发明实施例涉及半导体装置以及半导体装置制造方法。
背景技术
随着半导体技术的演变，半导体芯片/裸片逐渐变小。同时，需将更多功能集成到半导体裸片中。相应地，半导体裸片需将更多数目个I/O垫封装到更小区中，且I/O垫的密度随时间而快速上升。因此，半导体裸片的封装变得更加困难，此负面影响封装的良率。如何降低生产复杂性和封装成本已成为所述领域亟待解决的问题。
发明内容
根据本发明的实施例，一种半导体装置包括底部封装，所述底部封装包含：模塑料；贯穿通路，其穿透所述模塑料；裸片，其在所述模塑料中模制；和导体，其在所述贯穿通路上；其中在所述导体与所述贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积。
根据本发明的实施例，一种半导体装置包括：底部封装，其包含模塑料、穿透所述模塑料的贯穿通路和在所述模塑料中模制的裸片；导体，其在所述贯穿通路上；顶部封装，其在所述底部封装上方且通过所述导体接合到所述底部封装；和底胶填充，其在所述顶部封装与所述底部封装之间；其中所述贯穿通路在形成所述导体的一侧处从所述模塑料突出小于约1微米。
根据本发明的实施例，一种制造半导体装置的方法，所述方法包括：提供载体；在所述载体上形成牺牲层；在所述牺牲层上方形成贯穿通路；在所述牺牲层上放置裸片；在所述牺牲层上形成模塑料以填充所述裸片与所述贯穿通路之间的间隙；在所述裸片、所述贯穿通路和所述模塑料上方形成重布层；去除所述载体和所述牺牲层以暴露所述贯穿通路和所述模塑料的一个末端；在所述贯穿通路的所述末端上放置导体；和放置底胶填充以围绕所述导体，其中所述底胶填充与所述模塑料物理接触。
附图说明
在结合附图阅读时，可从以下详细描述最佳理解本揭露的方面。应注意，根据产业中的标准实践，各个构件不按比例绘制。实际上，为了清楚论述，可任意增大或减小各个构件的尺寸。
图1到图13是根据一些示范性实施例的封装结构的制造中的中间阶段的横截面图；
图14是根据本揭露的实施例的图12的区A的放大图；以及
图15是根据本揭露的实施例的图13的区B的放大图。
具体实施方式
下列揭露内容提供用于实施所提供标的物的不同构件的许多不同实施例或实例。下文描述组件和布置的特定实例以简化本揭露。当然，这些仅为实例且不旨在限制。举例来说，在下列描述中的第一构件形成于第二构件上方或上可包括其中所述第一构件和所述第二构件经形成直接接触的实施例，且也可包括其中额外构件可形成在所述第一构件与所述第二构件之间，使得所述第一构件和所述第二构件可不直接接触的实施例。另外，本揭露可在各个实例中重复参考符号和/或字母。此重复是用于简化和清楚的目的且本身并不指示所论述的各种实施例和/或配置之间的关系。
此外，为便于描述，可在本文中使用空间相对术语(例如，“在......下方”、“在......下”、“下”、“在......上”、“上”和类似者)以描述一个元件或构件与另一(若干)元件或构件的关系，如图中所展示。空间相对术语旨在涵盖除在图中描绘的定向以外的在使用或操作中的装置的不同定向。装备可经另外定向(旋转90度或以其它定向)，且因此可同样解释本文中所使用的空间相对描述符。
虽然阐述本揭露的广泛范围的数值范围和参数为近似值，但已尽可能精确地报告特定实例中所阐述的数值。然而，任何数值本就包括由各自试验测量中所得到的标准偏差引起的某些必然误差。又，如本文中使用，术语“大约”一般意味着在给定值或范围的10％、5％、1％或0.5％内。替代地，当由一般技术者考虑时，术语“大约”意味着在可接受平均值标准误差内。除了在操作/工作实例中外，或除非另有明确指定，否则所有数值范围、数量、值和百分比(例如，材料数量、持续时间、温度、操作条件、数量比和本文揭示的这些的类似物的数值范围、数量、值和百分比)应理解为在所有例项中被术语“大约”修饰。因此，除非相反地指示，否则本揭露和随附发明权利要求书中阐述的数值参数是可视需要变化的近似值。最起码，应至少鉴于所报告的有效数字且通过应用普通舍位技术解释各数值参数。本文将范围表达为从一个端点到另一端点或在两端点之间。除非另有指定，否则本文揭示的所有范围包括所述端点。
根据各种示范性实施例，提供无激光钻孔工艺的集成扇出(InFO)封装和其形成方法。描绘形成InFO封装的中间阶段。论述实施例的变动。贯穿各个视图和阐释性实施例，相似的元件符号用来指定相似的元件。
图1到图13是根据一些示范性实施例的封装结构的制造中的中间阶段的横截面图。参考图1，提供载体20。所述载体20可经配置以提供结构刚度或用于沉积后续非刚性层的基底。在一个实施例中，载体20可为玻璃载体、陶瓷载体或类似物。例如，在一些实施例中，载体20可替代地为晶片、半导体、金属、具有合适形貌和结构刚度的合成或其它材料。参考图2，在载体20上形成牺牲层24而不形成介电层(例如：聚合物层)，所述介电层在现有工艺中通常在后续晶种层形成之前形成。举例来说，此处省略的介电层可为聚酰亚胺、聚苯并
Figure BDA0001371008810000031
唑(PBO)、苯并环丁烯(BCB)、味之素增建膜(ABF)、防焊膜(SR)或类似物。实施例的概念是使用牺牲层24以取代现有介电层，且由此达成省去现有工艺中所需的激光钻孔工艺的目的。在以段落中将描述相关联细节。
又，如图2中展示，例如通过物理气相沉积(PVD)或金属箔积层在牺牲层24上形成晶种层26。晶种层26可包含铜、铜合金、铝、钛、钛合金或其组合物。在一些实施例中，晶种层26包含钛层26A和在钛层26A上方的铜层26B。然而，此并非本揭露的限制。在替代实施例中，晶种层26是铜层。
参考图3，在晶种层26上方涂敷光阻剂28且基于电路设计需求图案化光阻剂28。因此，在光阻剂28中形成开口30以暴露晶种层26的一些部分。
如图4中所示，通过镀覆(其可为电镀或无电式电镀)在开口30中形成金属构件32。金属构件32被镀覆在晶种层26的暴露部分上且可大体上填充开口30。金属构件32可包含铜、铝、钨、镍、焊料或其合金。金属构件32的俯视形状可为长方形、正方形、圆形或类似者。金属构件32的高度可根据图7中的随后放置裸片34的厚度而设计，其中在一些实施例中金属构件32的高度可大于裸片34的厚度。在镀覆金属构件32后，去除光阻剂28，且在图5中展示所得结构。在去除光阻剂28后，暴露晶种层26由光阻剂28所覆盖的部分。
参考图6，执行蚀刻步骤以去除晶种层26的暴露部分，其中蚀刻可为各向异性蚀刻。另一方面，晶种层26由金属构件32重叠的部分保持未蚀刻。贯穿描述，金属构件32和晶种层26的剩余底层部分结合称作贯穿InFO通路(TIV)33，这些也称作贯穿通路33。虽然晶种层26被展示为与金属构件32分离的层，但当晶种层26是由类似或相同于各自上覆金属构件32的材料形成时，晶种层26可与金属构件32合并而在这些之间不具有可区分界面。在替代实施例中，可区分界面存在于晶种层26与上覆金属构件32之间。
图7展示将装置裸片34放置在牺牲层24上方。装置裸片34可通过(若干)粘着层36粘着到牺牲层24。在一个实施例中，粘着层36可为胶带或裸片附着膜(DAF)，或替代地可为经由旋涂工艺或类似物涂敷到牺牲层24的胶液或环氧树脂。装置裸片34的应用不限于单裸片的应用，这是因为本揭露可包含一个以上裸片。在一些实施例中，装置裸片34可具有用于将电连接能力提供到装置裸片34内的电路(未展示)的一或多个基座，这些例如可为接点、接脚、安装垫、焊盘或类似物。装置裸片34可包含各种无源和有源微电子装置(未展示)，例如电阻器、电容器、电感器、二极管、金属氧化物半导体场效晶体管(MOSFET)、互补MOS(CMOS)晶体管、双极接面晶体管(BJT)、横向扩散MOS(LDMOS)晶体管、高功率MOS晶体管、FinFET晶体管、其它类型的晶体管和/或其的任一组合。装置裸片34可为其中包含逻辑晶体管的逻辑装置裸片。在一些示范性实施例中，装置裸片34经设计用于移动应用，且可为中央计算装置(CPU)裸片、电力管理集成电路(PMIC)裸片、收发器(TRX)裸片或类似物。装置裸片34的各者包含接触粘着层36的半导体衬底35(例如，硅衬底)，其中半导体衬底35的背表面与粘着层36接触。
在半导体集成电路制造中采用半导体衬底35，且可在半导体衬底35中和/或上形成集成电路。半导体衬底是指包括半导体材料的任何构造，包含(但不限于)块体硅、半导体晶片、绝缘体上硅(SOI)衬底或硅锗衬底。也可使用其它半导体材料，包含III族、IV族和V族元素。半导体衬底可进一步包括多个隔离构件(未展示)，例如浅沟渠隔离(STI)构件或局部硅氧化(LOCOS)构件。隔离构件可界定和隔离各种微电子元件。可形成在半导体衬底中的各种微电子元件的实例(未展示)包含晶体管(例如，金属氧化物半导体场效晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极接面(BJT)、高电压晶体管、高频晶体管、p信道和/或n信道场效晶体管(PFET/NFET)等)；电阻器；二极管；电容器；电感器；熔丝；和其它合适元件。执行各种工艺以形成各种微电子元件，包含沉积、蚀刻、布植、光刻、退火和/或其它合适工艺。微电子元件经互连以形成集成电路装置，例如逻辑装置、存储器装置(例如，SRAM)、RF装置、输入/输出(I/O)装置、系统单芯片(SoC)装置、其的组合和其它合适类型的装置。
在一些示范性实施例中，金属柱40(例如，铜柱)经形成为装置裸片34的顶部且电耦合到例如装置裸片34中的晶体管(未展示)的装置。在一些实施例中，在各自装置裸片34的顶部表面处形成介电层38，其中金属柱40具有在介电层38中的至少下部分。在一些实施例中，金属柱40的顶部表面也可与介电层38的顶部表面齐平。或者，未形成介电层38，且金属柱40突出于各自装置裸片34的顶部介电层上方。
参考图8，在装置裸片34和TIV 33上模制模塑料42。模塑料42填充装置裸片34与TIV 33之间的间隙，且可与牺牲层24接触。在一些实施例中，装置裸片34的金属柱40之间的间隙也可由模塑料42填充。在一些实施例中，可预先填充装置裸片34的金属柱40之间的间隙。作为实例，模塑料42可包含绝缘材料，例如环氧树脂、树脂、填充物材料、应力释放剂(SRA)、粘着促进剂、其它材料或其组合。模塑料42可在大体上液体时涂敷，且接着可通过例如环氧树脂或树脂中的化学反应而固化。在另一实施例中，模塑料42可为紫外线(UV)或热固化聚合物，其作为能够放置于装置裸片34和TIV 33周围的凝胶或可延展固体而涂敷。在采用紫外线或热固化模塑料42的实施例中，模塑料42可使用与成型区的外围接界的模具(例如，晶片或封装)形成在适当位置中。
接着，可部分去除模塑料42。在一些实施例中，模塑料42可经历研磨步骤以从装置裸片34和TIV 33去除过量材料。在此实施例中，模塑料42可经受化学机械抛光、纯机械抛光、化学蚀刻或另一合适还原工艺。在一些实施例中，所得还原模塑料42可具有在TIV 33和装置裸片34的顶部表面处或下方的顶部表面。在示范性实施例中，TIV33和装置裸片34的顶部表面可大体上与模塑料42的顶部表面齐平。因此，可在模塑料42的抛光侧处暴露TIV 33和装置裸片34的第一末端使得电接点形成在TIV 33和装置裸片34上。在一些实施例中，研磨也可降低TIV 33和装置裸片34的高度。
在图9中展示所得结构。归因于研磨，金属构件32的顶端32A大体上与金属柱40的顶端40A齐平(共面)，且大体上与模塑料42的顶部表面42A齐平(共面)。由于研磨，金属残留物(例如，金属颗粒)可经产生且留在顶部表面32A、40A和42A上。因此，在研磨之后，可例如通过清洁操作执行清洁使得去除金属残留物。
接着，参考图10，在模塑料42上方形成重布线(RDL)44以连接到金属柱40和TIV33。RDL 44也可使金属柱40和TIV 33互连。根据各种实施例，一或多个介电层46形成在图9中所示的结构上方，其中RDL 44形成在介电层46中。在一些实施例中，形成RDL 44和介电层46的层包含：形成毯覆式铜晶种层；在所述毯覆式铜晶种层上方形成并图案化掩模层；执行镀覆以形成RDL 44；去除掩模层；和执行蚀刻以去除毯覆式铜晶种层未由RDL 44所覆盖的部分。在替代实施例中，RDL 44通过沉积金属层、图案化金属层而形成且填充RDL 44与介电层46之间的间隙。RDL 44可包括金属或金属合金，包含铝、铜、钨和/或其合金。图10展示RDL44的两层，但取决于各自封装的绕线要求，可存在RDL的一个或两个以上层。在这些实施例中，介电层46可包括聚合物，例如，聚酰亚胺、苯并环丁烯(BCB)、聚苯并
Figure BDA0001371008810000051
唑(PBO)或类似物。或者，介电层46可包含无机介电材料，例如，氧化硅、氮化硅、碳化硅、氮氧化硅或类似物。
图11描绘根据一些示范性实施例形成电连接器48。形成电连接器48可包含在RDL44的暴露部分上放置焊球(或凸块下金属(如果形成，未展示))且接着使焊球回焊。在替代实施例中，形成电连接器48包含执行镀覆步骤以在RDL 44上方形成焊料区域，且接着使焊料区域回焊。电连接器48也可包含金属柱或金属柱和焊料帽，这些也可通过镀覆形成。贯穿描述，将包含装置裸片34、TIV 33、模塑料42、上方RDL 44和介电层46以及牺牲层24的组合结构称为TIV封装50，其可为复合晶片。
接着，TIV封装50一起从载体20卸离。牺牲层24也连同载体20一起去除。在图12中展示所得结构。如以上段落中所提及，实施例的概念是使用牺牲层24取代现有介电层。由于牺牲层24能够在卸离载体20时去除，故TIV 33、模塑料42和粘着层36经暴露且由此达成省去对常规介电层操作的激光钻孔工艺的目的以便敞开常规介电层且暴露TIV。此外，根据本揭露的一些实施例，也省去常规介电层的回蚀刻，且因此TIV 33与模塑料42之间的步阶高度可小于约1微米。换句话说，TIV 33可与模塑料42的顶部表面齐平或从模塑料42突出约小于1微米。
在一些实施例中，可将TIV封装50锯切成多个TIV封装60，且在TIV 33的末端上放置导体以形成图13中所示的焊料区域68。图13展示顶部封装62到TIV封装60的接合，其中所述接合可通过焊料区域(例如焊球)68。在一些实施例中，焊料区域68可为通过TIV 33连结到TIV封装60的顶部封装62的焊球。在示范性实施例中，焊料区域68完全接触并覆盖对应TIV 33的暴露顶部表面。由于对应TIV 33的顶部表面经暴露而未由常规介电层覆盖，故各焊料区域68与对应TIV 33之间的接触表面积大体上等于TIV 33的横截面积。
贯穿描述，TIV封装60也称为底部封装60，这是由于这些可充当底部封装。在一些实施例中，顶部封装62包含接合到封装衬底64的装置裸片66。装置裸片66可包含(若干)存储器裸片，其可为例如静态随机存取存储器(SRAM)裸片、动态随机存取存储器(DRAM)裸片或类似物。
在一些实施例中，将经接合顶部封装62和TIV封装60进一步接合到另一封装组件72(其可为封装衬底)。然而，此并非本揭露的限制。在一些实施例中，底胶填充74经施配以与模塑料42接触且至少围绕焊料区域68。在一些实施例中，底胶填充74可包含如针对模塑料42描述的类似材料。在一些实施例中，作为实例，底胶填充74可包含苯甲醇、环氧树脂、氧化硅和/或其它材料。
在一些实施例中，可使用底胶材料施配工具或系统涂敷底胶材料42。作为实例，可使用螺旋技术和施配阀涂敷底胶填充74。在一些实施例中，底胶填充74在涂敷时是液体使得其在底部封装60与顶部封装62之间的多个焊料区域68之间和周围流动。接着使底胶填充74固化或允许底胶填充74干燥使得其形成固体。
在替代实施例中，封装组件72包括印刷电路板(PCB)。封装组件72可具有相对侧上的电连接器76(例如，金属垫或金属柱)和使电连接器76互连的金属迹线78。
图14是根据本揭露的实施例的图12的区A的放大图。如上文所提及，示范性实施例通过使用牺牲层24取代现有介电层而揭示新颖半导体装置和相关联方法。由于牺牲层24能够在使载体20脱胶时连同载体20一起去除，故可自然地暴露TIV 33的晶种层26的顶端26A。以此方式，可略过对现有介电层执行以便敞开现有介电层并暴露TIV的常规激光钻孔工艺。此外，也可省去现有介电层的常规回蚀刻工艺。由于回蚀刻工艺或多或少可伤害或损害模塑料42下方，故可放大现有结构中的TIV与模塑料之间的步阶高度。
通常，使用回蚀刻工艺以去除现有介电层的常规结构可在TIV与模塑料之间具有大于1微米的步阶高度。然而，在本揭露中，如图14中所示，根据本揭露的一些实施例，在TIV33与模塑料42之间的步阶高度h经控制而小于约1微米。换句话说，如图14中所示，根据本揭露的一些实施例，在TIV 33的晶种层26的顶端26A与邻近模塑料42之间的步阶高度h可小于约1微米。即，TIV 33的晶种层26的顶端26A可大体上与邻近模塑料42齐平；或TIV 33的晶种层26的顶端26A可从邻近模塑料42突出约小于1微米。
图15是根据本揭露的实施例的图13的区B的放大图。如上文所提及，示范性实施例通过使用牺牲层24取代现有介电层而揭示新颖半导体装置和相关联方法。由于牺牲层24能够在使载体20脱胶时连同载体20一起去除，故可从然地暴露TIV 33的晶种层26的顶端26A。以此方式，对现有介电层执行以便敞开现有介电层并暴露TIV的常规激光钻孔工艺变得不必要。对于常规结构，现有介电层可仍或多或少覆盖TIV的顶端的一部分，尤其从俯视图观看时TIV的外环的边界周围的部分。因此，在未采用回蚀刻工艺时的所述情况中，需形成在TIV上的后续焊料区域可通过TIV的外环的边界周围的介电层而与TIV的顶端部分分离。TIV与焊料区域之间的不完全结合可降低电特性和剥落的可能性。
在示范性实施例中，完全暴露TIV 33的晶种层26的顶端。因此，焊料区域68可完全接触且完全覆盖TIV 33的晶种层26的顶端。由于TIV 33的顶端经暴露而未由常规介电层部分覆盖，故在各焊料区域68与对应TIV 33之间的接触表面积s1大体上等于TIV 33的晶种层26的顶端的面积。在一些实施例中，在各焊料区域68与对应TIV 33之间的接触表面积s1大体上等于TIV 33的横截面积。
也可包含其它构件和工艺。例如，可包含测试结构以辅助3D封装或3DIC装置的验证测试。例如，测试结构可包含形成在重布层中或允许测试3D封装或3DIC、使用探针和/或探针卡和类似物的衬底上的测试垫。验证测试可对中间结构以及最终结构执行。另外，本文中所揭示的结构和方法可结合并入已知良好裸片的中间验证的测试方法论使用以增加良率且降低成本。
本揭露的一些实施例提供一种半导体装置。所述半导体装置包含：底部封装；其中在导体与贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积，且所述底部封装包含：模塑料；贯穿通路，其穿透所述模塑料；裸片，其模制于所述模塑料中；和导体，其在所述贯穿通路上。
本揭露的一些实施例提供一种半导体装置。所述半导体装置包含：底部封装、所述底部封装上方且通过导体接合到所述底部封装的顶部封装；和底胶填充，其在所述顶部封装与所述底部封装之间；其中贯穿通路在所述导体所处的一侧处从模塑料突出小于约1微米，且所述底部封装包含：模塑料；贯穿通路，其穿透所述模塑料；裸片，其模制于所述模塑料中；和导体，其在所述贯穿通路上。
本揭露的一些实施例提供一种制造半导体装置的方法。所述方法包含：提供载体；在所述载体上形成牺牲层；在所述牺牲层上方形成贯穿通路；在所述牺牲层上放置裸片；在所述牺牲层上形成模塑料以填充所述裸片与所述贯穿通路之间的间隙；在所述裸片、所述贯穿通路和所述模塑料上方形成重布层；去除所述载体和所述牺牲层以暴露所述贯穿通路和所述模塑料的一个末端；在所述贯穿通路的所述末端上放置导体；和放置底胶填充以围绕所述导体，其中所述底胶填充与所述模塑料物理接触。
前文概述数项实施例的特征，使得所属领域的技术人员可更佳理解本揭露的方面。所属领域的技术人员应明白，这些可容易将本揭露用作设计或修改其它操作和结构的基础以实行本文中介绍的实施例的相同目的和/或达成相同优点。所属领域的技术人员也应认识到，这些等效构造并未脱离本揭露的精神和范围，且这些可在不脱离本揭露的精神和范围的情况下在本文中进行各种改变、置换和更改。
再者，本申请案的范围并不旨在限于说明书中描述的程序、机器、制造、物质组合物、构件、方法和步骤的特定实施例。一般技术者将容易从本揭露的揭露内容了解，可根据本揭露利用执行与本文描述的对应实施例大体上相同的功能或达成与这些大体上相同的结果的当前现有或随后开发的程序、机器、制造、物质组合物、构件、方法或步骤。因此，随附发明权利要求书旨在将这些程序、机器、制造、物质组合物、构件、方法或步骤包含于这些范围内。
符号说明
20 载体
24 牺牲层
26 晶种层
26A 钛层
26B 铜层
28 光阻剂
30 开口
32 金属构件
32A 金属构件的顶端
33 贯穿InFO通路(TIV)
34 装置裸片
35 半导体衬底
36 粘着层
38 介电层
40 金属柱
40A 金属柱的顶端
42 模塑料
42A 模塑料的顶部表面
44 重布线(RDL)
46 介电层
48 电连接器
50 TIV封装
60 TIV封装
62 顶部封装
64 封装衬底
66 装置裸片
68 焊料区域
72 封装组件
74 底胶填充
76 电连接器
78 金属迹线
A 区
B 区
s1 接触表面积
h 步阶高度

Claims (35)

1.一种半导体装置，其包括：
底部封装，其包含：
模塑料；
贯穿通路，其穿透所述模塑料；
裸片，其模制在所述模塑料中；以及
导体，其在所述贯穿通路上；
其中在所述导体被定位的侧处，所述贯穿通路与所述模塑料之间的步阶高度小于约1微米，所述导体与所述贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积，且所述贯穿通路在所述导体被定位的侧处的表面为完整的晶种层沉积面。
2.根据权利要求1所述的半导体装置，其进一步包括：
顶部封装，其在所述底部封装上方且透过所述导体接合至所述底部封装；以及
底部填充胶，其在所述顶部封装与所述底部封装之间；
其中所述底部填充胶与所述模塑料物理接触。
3.根据权利要求2所述的半导体装置，其中所述底部封装进一步包含：
粘着层，其在所述裸片上方。
4.根据权利要求3所述的半导体装置，其中所述粘着层在所述模塑料中，且所述粘着层的顶部表面与所述底部填充胶物理接触。
5.根据权利要求1所述的半导体装置，其中所述贯穿通路包含晶种层。
6.根据权利要求5所述的半导体装置，其中所述贯穿通路进一步包含金属构件。
7.根据权利要求6所述的半导体装置，其中所述晶种层的顶部表面完全与所述导体物理接触。
8.根据权利要求7所述的半导体装置，其中所述晶种层从邻近的所述模塑料突出小于约1微米。
9.一种半导体装置，其包括：
底部封装，其包含：
模塑料；
贯穿通路，其穿透所述模塑料；以及
裸片，其模制在所述模塑料中；
导体，其在所述贯穿通路上；
顶部封装，其在所述底部封装上方且透过所述导体接合至所述底部封装；以及
底部填充胶，其在所述顶部封装与所述底部封装之间；
其中所述贯穿通路在形成所述导体的侧处从所述模塑料突出小于约1微米，且所述贯穿通路在形成所述导体的侧处的表面为完整的晶种层沉积面。
10.根据权利要求9所述的半导体装置，其中所述底部填充胶与所述模塑料物理接触。
11.根据权利要求10所述的半导体装置，其中在所述导体与所述贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积。
12.根据权利要求9所述的半导体装置，其中所述底部封装进一步包含：
粘着层，其在所述裸片上方。
13.根据权利要求12所述的半导体装置，其中所述粘着层在所述模塑料中，且所述粘着层的顶部表面与所述底部填充胶物理接触。
14.根据权利要求9所述的半导体装置，其中所述贯穿通路包含晶种层。
15.根据权利要求14所述的半导体装置，其中所述贯穿通路进一步包含金属构件。
16.根据权利要求15所述的半导体装置，其中所述晶种层的顶部表面完全与所述导体物理接触。
17.根据权利要求16所述的半导体装置，其中所述晶种层的所述顶部表面与邻近的所述模塑料之间的步阶高度小于约1微米。
18.一种制造半导体装置的方法，所述方法包括：
提供载体；
在所述载体上形成牺牲层；
在所述牺牲层上方形成贯穿通路，所述贯穿通路的形成包含在所述牺牲层上沉积晶种层，且所述晶种层具有与所述牺牲层接触的晶种层沉积面；
在所述牺牲层上放置裸片；
在所述牺牲层上形成模塑料以填充所述裸片与所述贯穿通路之间的间隙；
在所述裸片、所述贯穿通路及所述模塑料上方形成重布层；
同时移除所述载体及所述牺牲层以自然暴露所述贯穿通路的所述晶种层沉积面及所述模塑料的一个末端；
在所述贯穿通路的所述晶种层沉积面上放置焊球；以及
放置底部填充胶以围绕所述焊球，其中所述底部填充胶与所述模塑料物理接触；
其中所述贯穿通路的所述晶种层沉积面与邻近的所述模塑料的所述末端之间的步阶高度小于约1微米。
19.一种半导体装置，其包括：
底部封装，其包含：
模塑料；
贯穿通路，其穿透所述模塑料；
裸片，其模制在所述模塑料中；以及
粘着层，其在所述裸片上方；
焊球，其在所述贯穿通路上；
顶部封装，其在所述底部封装上方且透过所述焊球接合至所述底部封装；以及
底部填充胶，其在所述顶部封装与所述底部封装之间；
其中在所述焊球被定位的侧处，所述贯穿通路与所述模塑料之间的步阶高度小于约1微米，所述焊球与所述贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积，且所述底部填充胶与所述模塑料物理接触，且所述贯穿通路在所述焊球被定位的侧处的表面为完整的晶种层沉积面。
20.根据权利要求19所述的半导体装置，其中所述粘着层在所述模塑料中，且所述粘着层的顶部表面与所述底部填充胶物理接触。
21.根据权利要求19所述的半导体装置，其中所述贯穿通路包含晶种层。
22.根据权利要求21所述的半导体装置，其中所述贯穿通路进一步包含金属构件。
23.根据权利要求22所述的半导体装置，其中所述晶种层的顶部表面完全与所述焊球物理接触。
24.根据权利要求21所述的半导体装置，其中所述晶种层从邻近的所述模塑料突出小于约1微米。
25.一种半导体装置，其包括：
底部封装，其包含：
模塑料；
贯穿通路，其穿透所述模塑料；
裸片，其模制在所述模塑料中；以及
粘着层，其在所述裸片上方；
导体，其在所述贯穿通路上；
顶部封装，其在所述底部封装上方且透过所述导体接合至所述底部封装；且
其中所述贯穿通路在形成所述导体的侧处从所述模塑料突出小于约1微米，且所述贯穿通路在形成所述导体的侧处的表面为完整的晶种层沉积面。
26.根据权利要求25所述的半导体装置，其进一步包括：
底部填充胶，其在所述顶部封装与所述底部封装之间；
其中所述底部填充胶与所述模塑料物理接触。
27.根据权利要求26所述的半导体装置，其中在所述导体与所述贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积。
28.根据权利要求26所述的半导体装置，其中所述粘着层在所述模塑料中，且所述粘着层的顶部表面与所述底部填充胶物理接触。
29.根据权利要求25所述的半导体装置，其中所述贯穿通路包含晶种层。
30.根据权利要求29所述的半导体装置，其中所述贯穿通路进一步包含金属构件。
31.根据权利要求30所述的半导体装置，其中所述晶种层的顶部表面完全与所述导体物理接触。
32.根据权利要求31所述的半导体装置，其中所述晶种层的所述顶部表面与邻近的所述模塑料之间的步阶高度小于约1微米。
33.一种半导体装置，其包括：
底部封装，其包含：
模塑料；
贯穿通路，其穿透所述模塑料，其中所述贯穿通路包含晶种层；
裸片，其模制在所述模塑料中；
粘着层，其在所述裸片上方；以及
导体，其在所述贯穿通路上，其中在所述导体被定位的侧处，所述贯穿通路与所述模塑料之间的步阶高度小于约1微米，所述导体与所述贯穿通路之间的接触表面积大体上等于所述贯穿通路的横截面积，且所述贯穿通路在所述导体被定位的侧处的表面为完整的晶种层沉积面。
34.根据权利要求33所述的半导体装置，其中所述贯穿通路进一步包含金属构件。
35.根据权利要求33所述的半导体装置，其中所述粘着层在所述模塑料中。
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