CN106997869B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN106997869B
CN106997869B CN201611151393.1A CN201611151393A CN106997869B CN 106997869 B CN106997869 B CN 106997869B CN 201611151393 A CN201611151393 A CN 201611151393A CN 106997869 B CN106997869 B CN 106997869B
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semiconductor device
redistribution layer
die
voltage regulator
encapsulant
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CN106997869A (zh
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余振华
张智援
王垂堂
谢政宪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

本发明实施例提供一种半导体装置及其制造方法，其中运用囊封剂来囊封第一半导体装置及通孔。重布层将所述第一半导体装置连接到第二半导体装置。在特定实施例中，所述第一半导体装置是集成式电压调节器，且所述第二半导体装置是逻辑装置，例如中央处理单元。

Description

半导体装置及其制造方法
技术领域
本发明实施例涉及半导体装置及其制造方法。
背景技术
半导体装置用于各种电子应用中，作为实例，例如个人计算机、手机、数码相机及其它电子设备。通常通过以下步骤制造半导体装置：将材料的各个绝缘层或电介质层、导电层及半导体层循序地沉积于半导体衬底上；及使用光刻图案化各个材料层以在各个材料层上形成电路组件及元件。通常将几十或几百个集成电路制造于单一半导体晶片上。通过沿切割道锯切集成电路而单粒化个别裸片。
一旦单粒化，接着可运用彼此互补工作的其它装置封装个别裸片。当不期望将全部所需功能性放置到单一裸片中时，此封装是有用的。例如，如果一个功能性可能干扰其它功能性，那么可期望使不同裸片互连，其中每一裸片执行所需功能性而无来自其它裸片的过度干扰。然而，单独裸片上不同功能性的此互连导致应解决的其它问题。
发明内容
本发明的实施例提供一种包括第一半导体装置的半导体装置，其中所述第一半导体装置包括第一电压调节器。囊封剂囊封所述第一半导体装置且贯穿通孔与所述第一半导体装置分离且从所述囊封剂的第一侧延伸到所述囊封剂的第二侧。第一重布层在所述囊封剂的第一侧上电连接到所述贯穿通孔，且第二半导体装置通过所述第一重布层电连接到所述第一半导体装置，其中所述第二半导体装置包括第一逻辑装置。
根据本发明另一实施例，提供一种包括囊封剂的半导体装置，所述囊封剂具有第一侧及与所述第一侧相对的第二侧。贯穿通孔从所述第一侧延伸到所述第二侧且第一电压调节器裸片从所述第一侧延伸到所述第二侧。第一重布层电连接到所述贯穿通孔及所述第一电压调节器裸片，且第一逻辑裸片通过所述第一重布层电连接到所述第一电压调节器裸片。
根据本发明又另一实施例，提供一种制造半导体装置的方法，其包括运用第一囊封剂囊封通孔及第一电压调节器裸片，其中所述第一囊封剂与所述通孔物理接触。在所述第一囊封剂的第一侧上形成第一重布层，所述第一重布层与所述通孔电连接，且将第一逻辑裸片接合到所述第一重布层，所述第一逻辑裸片与所述第一电压调节器裸片电连接。
根据本发明又另一实施例，提供一种制造半导体装置的方法，其包括在第一半导体裸片上方形成第一重布层，其中所述第一半导体裸片是逻辑裸片。在所述第一重布层的与所述第一半导体裸片相对的侧上形成通孔，且将第一集成式电压调节器放置成邻近于所述通孔。囊封所述第一集成式电压调节器及所述通孔。
附图说明
在结合附图阅读时，从下文详细描述最佳地理解本揭露的方面。应注意，根据标准工业实践，各个构件未按比例绘制。事实上，为了清晰讨论起见，可任意地增大或减小各个构件的尺寸。
图1到4说明根据一些实施例的具有多个重布层的集成半导体装置。
图5说明根据一些实施例的具有单一重布层的集成半导体装置。
图6说明根据一些实施例的具有单一重布层及底胶材料的集成半导体装置。
图7说明根据一些实施例的具有多个重布层及底胶材料的集成半导体装置。
图8说明根据一些实施例的具有多个重布层及延伸贯穿所述多个重布层的贯穿硅通孔的集成半导体装置。
图9说明根据一些实施例的具有多个重布层及延伸贯穿所述多个重布层的贯穿硅通孔以及底胶材料的集成半导体装置。
图10说明根据一些实施例的具有单一重布层以及延伸贯穿多个重布层的贯穿硅通孔的集成半导体装置。
图11说明根据一些实施例的具有单一重布层以及延伸贯穿多个重布层的贯穿硅通孔及底胶材料的集成半导体装置。
图12说明根据一些实施例的具有裸片堆叠的集成半导体装置。
图13A到13B说明其中最后附接第一半导体装置、第二半导体装置及第三半导体装置的实施例。
图14说明根据一些实施例的底胶材料的放置。
图15说明根据一些实施例的第一半导体装置、第二半导体装置及第三半导体装置的囊封。
图16说明根据一些实施例的散热片的放置。
具体实施方式
下文揭露提供用于实施本发明的不同特征的诸多不同实施例或实例。下文描述组件及布置的特定实例以简化本揭露。当然，这些仅是实例且并非旨在限制。例如，在下文描述中，第一构件在第二构件上方或其上形成可包含其中将所述第一构件及所述第二构件形成为直接接触的实施例，且还可包含其中可在所述第一构件与所述第二构件之间形成额外构件使得所述第一构件及所述第二构件可不直接接触的实施例。另外，本揭露可在各个实例中重复元件符号及/或字母。此重复用于简化及清晰的目的且自身不指示所讨论的各项实施例及/或配置之间的关系。
此外，为了方便描述，可在本文中使用空间关系术语(例如“下面”、“下方”、“下”、“上方”、“上”及类似术语)以描述如图中所说明的一个元件或构件与另一(些) 元件或构件的关系。除图中所描绘的定向以外，空间关系术语还希望涵盖装置在使用中或操作中的不同定向。设备可以其它方式定向(旋转90度或呈其它定向)，且据此可同样解释本文中所使用的空间关系描述词。
现参考图1，其展示具有粘合剂层103的第一载体衬底101。第一载体衬底101包括例如硅基材料(例如玻璃或氧化硅)或其它材料(例如氧化铝)或任何此类材料的组合或类似者。第一载体衬底101是平坦的以便容纳半导体装置(例如第一半导体装置401、第二半导体装置403及第三半导体装置405)的附接。
粘合剂层103放置于第一载体衬底101上以便协助上覆结构的粘合。在实施例中，粘合剂层103可包括紫外线胶，所述紫外线胶在暴露于紫外光时失去其粘合性质。然而，还可使用其它类型的粘合剂，例如压敏粘合剂、辐射可固化粘合剂、环氧树脂、此类粘合剂的组合或类似者。粘合剂层103可以可容易在压力下变形的半液体或凝胶形式放置到第一载体衬底101上。
一旦已形成粘合剂层103，可将第一半导体装置401、第二半导体装置403及第三半导体装置405放置于粘合剂层103上。在实施例中，第一半导体装置401可为例如逻辑裸片(例如中央处理单元(CPU))，其被设计以结合第四半导体装置107(图1中未说明但下文关于图2A到2B进一步说明及描述)、第五半导体装置109(图1中也未说明但下文关于图2A到2B说明及描述)、第二半导体装置403及第三半导体装置405工作。然而，第一半导体装置401可为任何合适半导体装置，例如图形处理单元、存储器、高速输出入端(I/O)或类似者。
在实施例中，第一半导体装置401可包括第一衬底(未个别地说明)、第一有源装置(未个别地说明)、第一金属层、第一重布层、第一钝化层407及第一通孔409。所述第一衬底可包括块状硅(掺杂或无掺杂)或绝缘体上覆硅(SOI)衬底的有源层。通常，SOI衬底包括半导体材料层，例如硅、锗、硅锗、SOI、绝缘体上覆硅锗(SGOI)或其组合。可使用的其它衬底包含多层衬底、梯度衬底或混合定向衬底。
第一有源装置包括可用来产生第一半导体装置401(例如，GPU)的设计所需的结构及功能需求的多种有源装置及无源装置，例如电容器、电阻器、电感器及类似者。可使用任何合适方法而在第一衬底内或在第一衬底上别处形成第一有源装置。
第一金属层形成于第一衬底及第一有源装置上方且被设计以连接各种有源装置以形成功能电路。在实施例中，第一金属层是由电介质材料及导电材料的交替层形成且可通过任何合适工艺(例如沉积、镶嵌、双镶嵌等)而形成。在实施例中，可存在通过至少一个层间电介质层(ILD)与第一衬底分离的四个金属层，但第一金属层的精确数目取决于第一半导体装置401的设计。
第一重布层可形成于第一金属层上方且与第一金属层电接触。第一重布层可包括铝，但可替代地使用其它材料，例如铜。可使用沉积工艺(例如溅镀)以形成材料层(未展示)而形成第一重布层且接着可通过合适工艺(例如光刻掩模及蚀刻)移除所述材料层的部分以形成第一重布层。然而，可利用任何其它合适工艺来形成第一重布层。
第一钝化层407可形成于第一衬底上且在第一金属层及第一重布层上方。第一钝化层407可由一或多种合适电介质材料制成，例如聚酰亚胺、氧化硅、氮化硅、低介电系数电介质(例如碳掺杂的氧化物)、极低介电系数电介质(例如多孔碳掺杂的二氧化硅)、此类材料的组合或类似者。第一钝化层可通过例如化学气相沉积(CVD)的工艺形成，但可利用任何合适工艺且可具有约0.5μm与约5μm之间(例如约
Figure BDA0001179812230000041
)的厚度。
一旦已形成第一钝化层407，便可形成贯穿第一钝化层407的第一通孔409使其与第一重布层接触。在实施例中，可通过最初使用例如光刻掩模及蚀刻工艺图案化贯穿第一钝化层407的开口而形成第一通孔409。一旦已形成开口，可使用例如电镀、溅镀的工艺或类似工艺运用例如铜、铝或钨的材料填充或过填充所述开口。一旦沉积，可使用例如平坦化工艺(例如化学机械抛光)移除留在所述开口外部的任何导电材料。
第二半导体装置403可为例如被设计以结合第四半导体装置107、第五半导体装置109、第一半导体装置401(例如，CPU)及第三半导体装置405工作的另一中央处理单元。然而，第二半导体装置403可为任何合适半导体装置，例如GPU、存储器、高速I/O或类似者。
在实施例中，第二半导体装置403可包括第二衬底、第二有源装置(未个别地说明)、第二金属层(未个别地说明)、第二重布层(未个别地说明)、第二钝化层411及第二通孔413。在实施例中，第二衬底、第二有源装置、第二金属层、第二重布层、第二钝化层 411及第二通孔413可类似于第一衬底、第一有源装置、第一金属层、第一重布层、第一钝化层407及第一通孔409，但其也可不同。
第三半导体装置405可为例如被设计以结合第四半导体装置107、第五半导体装置109、第一半导体装置401(例如，CPU)及第二半导体装置403(例如，CPU)工作的输入/ 输出装置。然而，第三半导体装置405可为任何合适半导体装置，例如CPU、GPU、存储器或类似者。
在实施例中，第三半导体装置405可包括第三衬底、第三有源装置(未个别地说明)、第三金属层(未个别地说明)、第三重布层(未个别地说明)、第三钝化层415及第三通孔417。在实施例中，第三衬底、第三有源装置、第三金属层、第三重布层、第三钝化层 415及第三通孔417可类似于第一衬底、第一有源装置、第一金属层、第一重布层、第一钝化层407及第一通孔409，但其也可不同。
在实施例中，可使用例如取放工艺将第一半导体装置401、第二半导体装置403及第三半导体装置405放置到粘合剂层103上。然而，还可利用放置第一半导体装置401、第二半导体装置403及第三半导体装置405的任何其它方法。
一旦已放置第一半导体装置401、第二半导体装置403及第三半导体装置405，可运用第一囊封剂201囊封第一半导体装置401、第二半导体装置403及第三半导体装置 405。所述囊封可在成型装置(图1中未个别地说明)中执行，所述成型装置可包括顶部成型部分及可与所述顶部成型部分分离的底部成型部分。在将所述顶部成型部分降低到邻近于所述底部成型部分时，可针对第一载体衬底101、第一半导体装置401、第二半导体装置403及第三半导体装置405形成模穴。
在囊封工艺期间，可将顶部成型部分放置成邻近于底部成型部分，由此将第一载体衬底101、第一半导体装置401、第二半导体装置403及第三半导体装置405围封于模穴内。一旦围封，顶部成型部分及底部成型部分可形成气密密封以便控制来自模穴的气体的流入量及流出量。一旦密封，可将第一囊封剂201放置于模穴内。第一囊封剂201 可为模塑料树脂，例如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、此类材料的组合或类似者。第一囊封剂201可在对准顶部成型部分及底部成型部分之前放置于模穴内，或以其它方式可通过注射端口注射到模穴中。
一旦已将第一囊封剂201放置到模穴中使得第一囊封剂201囊封第一载体衬底101、第一半导体装置401、第二半导体装置403及第三半导体装置405，便可固化第一囊封剂201以便硬化第一囊封剂201以用于最佳保护。虽然确切固化工艺至少部分取决于针对第一囊封剂201选取的特定材料，但在其中选取模塑料作为第一囊封剂201的实施例中，固化可通过例如将第一囊封剂201加热到约100℃与约130℃之间(例如约125 ℃)达约60秒到约3000秒(例如约600秒)的工艺而发生。另外，引发剂及/或催化剂可包含于第一囊封剂201内以更好地地控制固化工艺。
然而，如所述领域的技术人员将认知，上文所述的固化工艺仅是示范性工艺且并非意在限制本发明实施例。可替代地使用其它固化工艺，例如照射或甚至允许第一囊封剂201在室温下硬化。可使用任何合适固化工艺，且所有此类工艺完全旨在包含于本文中所讨论的实施例的范围内。
图1也说明薄化第一囊封剂201以便暴露第一通孔409(在第一半导体装置401上)、第二通孔413(在第二半导体装置403上)及第三通孔417(在第三半导体装置405上)以用于进一步处理。所述薄化可例如使用机械研磨或化学机械抛光(CMP)工艺来执行，由此利用化学蚀刻剂及磨料以使第一囊封剂201起化学反应且磨掉第一囊封剂201直到已暴露第一通孔409、第二通孔413及第三通孔417。因而，第一半导体装置401、第二半导体装置403及第三半导体装置405可具有也与第一囊封剂201齐平的平坦表面。
然而，虽然提出上文所述的CMP工艺作为一项说明性实施例，但其并非旨在限制实施例。可替代地使用任何其它合适移除工艺来薄化第一囊封剂201，且暴露第一通孔 409、第二通孔413及第三通孔417。例如，可利用一系列化学蚀刻。可替代地利用此工艺及任何其它合适工艺来薄化第一囊封剂201，且所有此类工艺完全旨在包含于实施例的范围内。
图1额外地说明与第一通孔409、第二通孔413及第三通孔417电连接的第一重布层309的形成。在实施例中，可通过最初形成RDL钝化层(图1中未单独标记)而形成第一重布层309。在实施例中，所述RDL钝化层可为聚苯并噁唑(PBO)，但可替代地利用任何合适材料，例如聚酰亚胺或聚酰亚胺衍生物。可使用例如旋涂工艺将所述RDL钝化层放置到约5μm与约25μm之间(例如约7μm)的厚度，但可使用任何合适方法及厚度。
一旦已放置RDL钝化层，可图案化RDL钝化层以便允许例如第一通孔409、第二通孔413及第三通孔417与后续形成的导电材料之间的电连接。在实施例中，可使用光刻掩模及蚀刻工艺图案化RDL钝化层，由此光致抗蚀剂被放置、暴露于能源，经显影且接着在蚀刻工艺期间被用作掩模。然而，可使用任何合适方法来形成并图案化RDL 钝化层。
一旦已图案化RDL钝化层，通过合适形成工艺(例如CVD或溅镀)形成钛铜合金的第一晶种层(未展示)。接着可形成光致抗蚀剂(也未展示)以覆盖所述第一晶种层，且接着可图案化所述光致抗蚀剂以暴露所述第一晶种层中定位于第一重布层309期望定位之处的那些部分。
一旦已形成并图案化光致抗蚀剂，可通过沉积工艺(例如镀覆)而在第一晶种层上形成导电材料，例如铜。所述导电材料可形成为具有约1μm与约10μm之间(例如5μm) 的厚度。然而，虽然所讨论的材料及方法适于形成所述导电材料，但此类材料仅是示范性的。可替代地使用任何其它合适材料(例如AlCu或Au)及任何其它合适形成工艺(例如 CVD或PVD)来形成第一重布层309。
一旦已形成导电材料，可通过合适移除工艺(例如灰化)移除光致抗蚀剂。另外，在移除光致抗蚀剂之后，可通过例如将导电材料用作掩模的合适蚀刻工艺移除第一晶种层中由光致抗蚀剂覆盖的那些部分。
在已形成导电材料之后，可重复RDL钝化层及导电材料的形成以便形成第二导电材料层。可重复工艺的此重复以形成第二电介质及导电材料层级。另外，虽然在图1中仅说明三个层，但工艺可重复任何次数以提供所需互连性。
图2A到2B说明通孔111的形成以及第四半导体装置107及第五半导体装置109 的放置。在实施例中，可通过最初在第一重布层309上方形成第二晶种层(图2 A中未单独说明)而形成通孔111。在实施例中，用于通孔111的第二晶种层是协助在后续处理步骤期间形成较厚层的导电材料的薄层。所述第二晶种层可包括约
Figure BDA0001179812230000071
厚的钛层，然后是约
Figure BDA0001179812230000072
厚的铜层。取决于所需材料，可使用例如溅镀、蒸镀或PECVD工艺的工艺产生所述第二晶种层。所述第二晶种层可形成为具有约0.3μm与约1μm之间(例如约0.5μm)的厚度。
一旦已形成第二晶种层，便在第二晶种层上放置并图案化光致抗蚀剂(图2A中未说明)。在实施例中，可使用例如旋涂技术而在第二晶种层上放置所述光致抗蚀剂到约50 μm与约250μm之间(例如约120μm)的高度。一旦在适当位置处，接着便可通过以下步骤图案化所述光致抗蚀剂：将所述光致抗蚀剂暴露于图案化能源(例如，图案化光源)以便引发化学反应，由此引发所述光致抗蚀剂中暴露于所述图案化光源的那些部分的物理变化。接着将显影剂施加于暴露的光致抗蚀剂以利用物理变化，且取决于所需图案选择性地移除光致抗蚀剂的暴露部分或光致抗蚀剂的未暴露部分。
在实施例中，形成到光致抗蚀剂中的图案是通孔111的图案(其还可称为贯穿InFO通孔或TIV)。通孔111以放置成位于随后附接的装置(例如第四半导体装置107及第五半导体装置109)的不同侧上的方式形成。然而，对于通孔111的图案可利用任何合适布置，例如被定位使得第四半导体装置107及第五半导体装置109放置于通孔111的相对侧上。
在实施例中，在光致抗蚀剂内形成通孔111。在实施例中，通孔111包括一或多种导电材料，例如铜、钨、其它导电金属或类似者，且可例如通过电镀、无电式电镀或类似者而形成。在实施例中，使用电镀工艺，其中将第二晶种层及光致抗蚀剂浸没或沉浸于电镀溶液中。第二晶种层表面电连接到外部DC电源供应器的负侧使得第二晶种层在电镀工艺中用作阴极。固态导电阳极(例如铜阳极)也沉浸于所述溶液中且附接到所述电源供应器的正侧。来自所述阳极的原子溶解于所述溶液中，阴极(例如，第二晶种层)从所述溶液获取所述溶解原子，由此将第二晶种层的暴露导电区镀覆于光致抗蚀剂的开口内。
一旦已使用光致抗蚀剂及第二晶种层形成通孔111，可使用合适移除工艺移除光致抗蚀剂。在实施例中，可使用等离子体灰化工艺来移除光致抗蚀剂，由此可增大光致抗蚀剂的温度直到光致抗蚀剂经历热分解且可被移除。然而，可替代地利用任何其它合适工艺，例如湿式剥离。光致抗蚀剂的移除可暴露第二晶种层的下伏部分。
一旦已暴露，可执行第二晶种层的暴露部分的移除。在实施例中，可通过例如湿式或干式蚀刻工艺移除第二晶种层的暴露部分(例如，未被通孔111覆盖的那些部分)。例如，在干式蚀刻工艺中，可使用通孔111作为掩模而引导反应物朝向第二晶种层。在另一实施例中，可将蚀刻剂喷涂成或以其它方式放置成与第二晶种层接触以便移除第二晶种层的暴露部分。
图2B说明将附接于通孔111内的第四半导体装置107的特写图。在实施例中，第四半导体装置107可为供应及/或控制供应到例如第一半导体装置401、第二半导体装置 403及第三半导体装置405的电压的电压调节器。在其中第四半导体装置107是电压调节器的实施例中，第四半导体装置107可供应约0.6V与约2.5V之间(例如约1.2V)的电压。然而，可由第四半导体装置107供应任何合适电压。
在实施例中，第四半导体装置107包括第四衬底(未个别地说明)、第四有源装置(未个别地说明)、第四金属层(未个别地说明)、第一接点垫、第四钝化层及第一外部连接器110。在特定实施例中，第四衬底、第四有源装置及第四金属层可由类似于上文关于第一衬底、第一有源装置及第一金属层所讨论的材料且使用类似于上文关于第一衬底、第一有源装置及第一金属层所讨论的工艺而形成，但可利用任何合适材料或工艺。
第一接点垫可形成于第四金属层上方且与第四金属层电接触。第一接点垫可包括铝，但可替代地使用其它材料，例如铜。可使用沉积工艺(例如溅镀)以形成材料层(未展示)而形成第一接点垫且接着可通过合适工艺(例如光刻掩模及蚀刻)移除所述材料层的部分以形成第一接点垫。然而，可利用任何其它合适工艺来形成接点垫。第一接点垫可形成为具有介于约0.5μm与约4μm之间(例如约1.45μm)的厚度。
第四钝化层可形成于第四衬底上且在第四金属层及第一接点垫上方。第四钝化层可由一或多种合适电介质材料制成，例如氧化硅、氮化硅、低介电系数电介质(例如碳掺杂的氧化物)、极低介电系数电介质(例如多孔碳掺杂的二氧化硅)、此类材料的组合或类似者。第四钝化层可通过例如化学气相沉积(CVD)的工艺而形成(但可利用任何合适工艺)，且可具有约0.5μm与约5μm之间(例如约
Figure BDA0001179812230000091
)的厚度。
可形成第一外部连接器110以提供用于第一接点垫与例如第一重布层309之间的接触的导电区。在实施例中，第一外部连接器110可为包括共晶材料(例如焊料)的微凸块，但可替代地使用任何合适材料。在其中第一外部连接器110是微凸块的实施例中，可使用植球方法(例如直接植球工艺)形成第一外部连接器110。在另一实施例中，可通过以下步骤形成微凸块：最初通过任何合适方法(例如蒸镀、电镀、印刷、焊料转移)形成锡层；及接着执行回焊以便使材料塑形为所需凸块形状。一旦已形成第一外部连接器110，可执行测试以确保结构适于进一步处理。在其中第一外部连接器110是微凸块的实施例中，第一外部连接器110可具有约20μm与约50μm之间的直径。
在另一实施例中，第一外部连接器110可为导电柱且可通过最初在第四钝化层上方形成光致抗蚀剂(未展示)到约5μm与约20μm之间(例如约10μm)的厚度而形成。可图案化所述光致抗蚀剂以暴露第四钝化层的部分，导电柱将延伸贯穿所述第四钝化层。一旦图案化，接着便可使用所述光致抗蚀剂作为掩模以移除第四钝化层的所需部分，由此暴露下伏第一接点垫中第一外部连接器110将接触的那些部分。
第一外部连接器110可被形成于第四钝化层及光致抗蚀剂两者的开口内。第一外部连接器110可为由导电材料(例如铜)形成，但还可使用其它导电材料，例如镍、金或金属合金、此类材料的组合，或类似者。另外，可使用例如电镀的工艺来形成第一外部连接器110，由此电流通过第一接点垫中第一外部连接器110期望被形成所到的导电部分，且第一接点垫沉浸于溶液中。所述溶液及所述电流在开口内沉积(例如，铜)以便填充及/ 或过填充光致抗蚀剂及第四钝化层的开口，由此形成第一外部连接器110。接着可使用 (例如)灰化工艺、化学机械抛光(CMP)工艺、此类工艺的组合或类似者来移除第四钝化层的开口外部的过量的导电材料及光致抗蚀剂。
然而，如所述领域的技术人员将认知，用来形成第一外部连接器110的上述工艺仅是描述，且并非意在将实施例限于此类确切工艺。确切来说，所描述的工艺旨在说明性，因为可利用用于形成第一外部连接器110的任何合适工艺。所有合适工艺完全旨在被包含于本发明实施例的范围内。
现参考图2A，图2A说明第四半导体装置107到第一重布层309上的放置以及第五半导体装置109的放置。在实施例中，第五半导体装置109可为另一电压调节器，且可包括第五衬底、第五有源装置、第五金属层、第二接点垫、第五钝化层(图2A 中未单独说明)及第二外部连接器113。在实施例中，第五衬底、第五有源装置、第五金属层、第二接点垫、第五钝化层及第二外部连接器113可类似于第四衬底、第四有源装置、第四金属层、第一接点垫、第四钝化层及第一外部连接器110，但其也可不同。在实施例中，可使用(例如)取放工艺来放置第四半导体装置107及第五半导体装置109。然而，还可利用放置第四半导体装置107及第五半导体装置109的任何其它方法。
一旦已将第四半导体装置107及第五半导体装置109放置成与第一重布层309电接触，便将第四半导体装置107及第五半导体装置109接合到第一重布层309。在其中第一外部连接器110及第二外部连接器113是微凸块的实施例中，可通过回焊工艺来接合第四半导体装置107及第五半导体装置109，由此增大微凸块的温度直到微凸块部分液化并开始流动。一旦随后降低温度，微凸块将重新凝固，由此将第四半导体装置107及第五半导体装置109物理与电接合到第一重布层309。
在其中第一外部连接器110及第二外部连接器113适合(例如是铜柱)的另一实施例中，可使用熔合接合工艺，将第四半导体装置107及第五半导体装置109接合到第一重布层309。例如，最初可使用(例如)湿式清洗程序(例如SC-1或SC-2清洗程序)来清洗第一重布层309及(第四半导体装置107的)第四钝化层及(第五半导体装置109的)第五钝化层内的电介质材料的暴露部分，以形成亲水性表面。一旦被清洗，便将第四半导体装置 107及第五半导体装置109对准到其相应所需部分中，且将所述亲水性表面放置成与第一重布层309物理接触，以开始接合程序。一旦已接触第四半导体装置107及第五半导体装置109，便可利用热退火来强化接合。
然而，如上文所述的熔合接合的描述仅是可用来将第四半导体装置107及第五半导体装置109接合到第一重布层309的另一类型的工艺的实例，其并非旨在限制实施例。确切来说，可替代地利用任何合适接合工艺(例如混合接合工艺，由此将第四半导体装置 107及第五半导体装置109的电介质部分及导电部分两者接合到第一重布层309)以将第四半导体装置107及第五半导体装置109接合到第一重布层309，且所有此类工艺完全旨在被包含于实施例内。
图3说明通孔111、第四半导体装置107及第五半导体装置109的囊封。在实施例中，如上文关于第一半导体装置401、第二半导体装置403及第三半导体装置405的囊封所述般囊封通孔111、第四半导体装置107及第五半导体装置109。例如，可将第四半导体装置107及第五半导体装置109放置到模穴(未单独说明)中且可将第二囊封剂419 放置于第四半导体装置107及第五半导体装置109上方。一旦处在适当位置中，如果需要，那么可使用例如CMP工艺平坦化第二囊封剂419、通孔111、第四半导体装置107 及第五半导体装置109直到暴露通孔111、第四半导体装置107及第五半导体装置109。然而，可使用任何合适工艺来囊封第四半导体装置107及第五半导体装置109。
图3说明形成第二重布层301以便使第四半导体装置107、第五半导体装置109、通孔111及第三外部连接器307互连。在实施例中，可使用类似于上文关于第一重布层 309所述的材料及工艺形成第二重布层301。然而，可利用任何合适工艺来形成第二重布层301。
图3还说明在第二重布层301上方形成第一重布层接点垫305及第一重布层钝化层303以便对第二重布层301及其它下伏结构提供保护及隔离。在实施例中，第一重布层接点垫305可形成于第二重布层301上方且与第二重布层301电接触，且可包括铝，但可替代地使用其它材料，例如铜。可使用沉积工艺(例如溅镀)以形成材料层(未展示)而形成第一重布层接点垫305且接着可通过合适工艺(例如光刻掩模及蚀刻)移除所述材料层的部分以形成第一重布层接点垫305。然而，可利用任何其它合适工艺来形成第一重布层接点垫305。第一重布层接点垫305可形成为具有约0.5μm与约4μm之间(例如约1.45 μm)的厚度。
在第一重布层接点垫305上方形成第一重布层钝化层303以便帮助保护第一重布层接点垫305及其它下伏结构。在实施例中，第一重布层钝化层303可为聚苯并噁唑 (PBO)，但可替代地利用任何合适材料，例如聚酰亚胺或聚酰亚胺衍生物。可使用例如旋涂工艺放置第一重布层钝化层303到约5μm与约25μm之间(例如约7μm)的厚度，但可替代地使用任何合适方法及厚度。
一旦已形成第一重布层接点垫305，可将第三外部连接器307形成为与第一重布层接点垫305电连接。在实施例中，第三外部连接器307可为包括共晶材料(例如焊料)的受控塌陷芯片连接(C4)凸块，但可替代地使用任何合适材料。选用地，可在第三外部连接器307与第一重布层接点垫305之间利用凸块下金属。在其中第三外部连接器307是 C4凸块的实施例中，可使用植球方法(例如直接植球工艺)形成第三外部连接器307。替代地，可通过以下步骤形成C4凸块：最初通过任何合适方法(例如蒸镀、电镀、印刷、焊料转移)形成锡层；及接着执行回焊以便使材料塑形为所需凸块形状。一旦已形成第三外部连接器307，便可执行测试以确保结构适于进一步处理。第三外部连接器307可形成为具有约40μm与约120μm之间(例如约80μm)的直径。
图3也说明第一载体衬底101的去接合。在实施例中，可将第三外部连接器307及(因此)包含第四半导体装置107及第五半导体装置109的结构附接到环结构(未单独说明)。所述环结构可为希望在去接合工艺期间及之后对所述结构提供支撑及稳定性的金属环。在实施例中，使用例如紫外线胶带将第三外部连接器307、第四半导体装置107及第五半导体装置109附接到所述环结构，但可替代地使用任何其它合适粘合剂或附接件。
一旦将第三外部连接器307及(因此)包含第四半导体装置107及第五半导体装置109 的结构附接到环结构，便可使用例如热工艺以改变粘合剂层103的粘合性质而使第一载体衬底101从包含第四半导体装置107及第五半导体装置109的结构去接合。在特定实施例中，利用例如紫外线(UV)激光、二氧化碳(CO2)激光或红外线(IR)激光的能源来照射并加热粘合剂层103直到粘合剂层103失去其至少一些粘合性质。一旦被执行，第一载体衬底101及粘合剂层103便可与包括第三外部连接器307、第四半导体装置107及第五半导体装置109的结构物理分离且从所述结构移除。
图4说明第三外部连接器307到衬底421的连接。在实施例中，衬底421可为封装衬底，其包括用来将第四半导体装置107、第五半导体装置109、第一半导体装置401、第二半导体装置403及第三半导体装置405连接到其它外部装置(未单独说明)的内部互连件(例如，贯穿硅通孔及金属层)。在另一实施例中，衬底421可为内插件，其用作中间衬底以将第四半导体装置107、第五半导体装置109、第一半导体装置401、第二半导体装置403及第三半导体装置405连接到外部装置。在此实施例中，衬底421可为例如硅衬底(掺杂或无掺杂)或绝缘体上覆硅(SOI)衬底的有源层。然而，衬底421可替代地是可提供合适保护及/或互连功能性的玻璃衬底、陶瓷衬底、聚合物衬底或任何其它衬底。此类及任何其它合适材料可用于衬底421。
第四外部连接件423可放置成与衬底421接触且用来提供衬底421与其它外部装置之间的连接能力。在实施例中，第四外部连接件423可为例如球栅阵列(BGA)，但可利用任何合适连接件。在其中第四外部连接件423是球栅阵列的实施例中，第四外部连接件423可包括例如锡的材料或例如银、无铅锡或铜的其它合适材料。在其中第四外部连接件423是锡焊凸块的实施例中，可通过最初经由常用方法(例如蒸镀、电镀、印刷、焊料转移、植球等)形成锡层到例如约100μm的厚度而形成第四外部连接件423。一旦已在结构上形成锡层，便可执行回焊以便使材料塑形为具有例如约150μm与约350μm之间(例如约250μm)的直径的所需凸块形状。
通过在第二囊封剂419以及通孔111内形成第四半导体装置107(例如，集成式电压调节器)及第五半导体装置109(例如，集成式电压调节器)且将第四半导体装置107及第五半导体装置109连接到第一半导体装置401(例如，CPU)、第二半导体装置403(例如， CPU)及第三半导体装置405(例如，I/O装置)，可将第四半导体装置107及第五半导体装置109放置成比其它解决方案更靠近定位于第一半导体装置401、第二半导体装置403 及第三半导体装置405内的切换负载。通过减小电压调节器与切换负载之间的物理距离，可解决已困扰其它结构的IR压降问题，由此提供具有紧凑尺寸架构及减小的板区的高效CPU功率管理的系统封装解决方案。另外，在其中第四半导体装置107及第五半导体装置109是电压调节器且第一半导体装置401及第二半导体装置403是CPU核心的实施例中，可将能量保存于具有每核心电压控制的此多核心CPU中。
图5说明其中在形成第一重布层接点垫305及第一重布层钝化层303之后将第三外部连接器307直接接合于通孔111上方而非形成第二重布层301以便将通孔111互连到第三外部连接器307的另一实施例。在特定实施例中，在已(使用例如CMP工艺)通过第二囊封剂419暴露通孔111之后，将第一重布层接点垫305直接形成于暴露通孔111上方且与暴露通孔111物理连接。一旦已形成第一重布层接点垫305，便形成第一重布层钝化层303以保护第一重布层接点垫305且可通过第一重布层钝化层303将第三外部连接器307放置到第一重布层接点垫305上。接着可将衬底421接合到第三外部连接器 307，由此避免使用第二重布层301。
通过将第三外部连接器307直接接合到通孔111，在其中第二重布层301是非所需的情境中可避免形成第二重布层301的额外工艺步骤及复杂性。通过减少工艺步骤及简化装置的制造，可更有效地且以更小缺陷机会制造装置。
图6说明类似于上文参考图5所述的实施例且其中放置第一底胶材料601以便保护第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)的实施例。在实施例中，第一底胶材料601是用来缓冲及支撑第一外部连接器 110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)以免受操作及环境劣化(例如由操作期间的热产生引起的应力)影响的保护性材料。第一底胶材料601可包括例如液态环氧树脂或其它保护性材料，且接着被固化以硬化。在实施例中，可在已放置第四半导体装置107及第五半导体装置109之后且在囊封之前通过以下步骤放置第一底胶材料601：使用例如注射工艺施配第一底胶材料601，由此以液态形式注射第一底胶材料601使得其围绕第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)流动。一旦已放置第一底胶材料601，可如上文所述般继续剩余工艺步骤。
通过施加第一底胶材料601，可更好地地保护第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)使其免受后续处理步骤影响。例如，第一底胶材料601可对第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)提供额外结构支撑以及额外隔离。此额外支撑及保护将减少或消除第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)的结构故障。
图7说明类似于上文参考图1到4所述的实施例的其中形成第二重布层301以帮助互连通孔111的实施例。然而，在此实施例中，在囊封第四半导体装置107及第五半导体装置109之前施配第一底胶材料601。在此实施例中，第一底胶材料601可如上文关于图6所述般，例如是使用注射工艺以液态形式施配的液态环氧树脂或其它保护性材料。然而，可使用任何合适施配材料或方法。一旦已放置第一底胶材料601，可如上文所述般继续剩余工艺步骤。
通过施加第一底胶材料601，可更好地地保护第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)使其免受后续处理步骤影响。例如，第一底胶材料601可对第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)提供额外结构支撑以及额外隔离。此额外支撑及保护将减少或消除第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)的结构故障。
图8说明类似于上文关于图4所讨论的实施例的另一实施例。然而，在此实施例中，贯穿硅通孔(TSV)801被形成贯穿第四半导体装置107的第四衬底及第五半导体装置109 的第五衬底。首先查看第四半导体装置107，在实施例中，可通过最初将贯穿硅通孔(TSV) 开口形成到第四半导体装置107的第四衬底中而形成TSV 801。可通过施加并显影合适光致抗蚀剂(未展示)以及移除第四半导体装置107的第四衬底中暴露达所需深度的部分而形成TSV开口。TSV开口可被形成以便延伸到第四半导体装置107的第四衬底中而至少远于形成于第四半导体装置107的第四衬底内及/或上的第四有源装置，且可延伸到大于第四半导体装置107的第四衬底的最终所需高度的深度。据此，虽然所述深度取决于总体设计，但所述深度可在与第四半导体装置107的第四衬底上的第四有源装置相隔约20μm与约200μm之间，例如与第四半导体装置107的第四衬底上的第四有源装置相隔约50μm的深度。
一旦已在第四半导体装置107的第四衬底内形成TSV开口，便可使用衬层加衬里于TSV开口。所述衬层可为例如由四乙基正硅酸盐(TEOS)或氮化硅形成的氧化物，但可替代地使用任何合适电介质材料。可使用等离子体增强化学气相沉积(PECVD)工艺形成所述衬层，但可替代地使用其它合适工艺，例如物理气相沉积或热工艺。另外，可将所述衬层形成到约0.1μm与约5μm之间(例如约1μm)的厚度。
一旦已沿TSV开口的侧壁及底部形成衬层，便可形成阻障层(也未单独说明)且可运用第一导电材料填充TSV开口的剩余部分。所述第一导电材料可包括铜，但可替代地利用其它合适材料，例如铝、合金、掺杂多晶硅、其组合及类似者。所述第一导电材料可通过以下步骤而形成：将铜电镀到第三晶种层(未展示)上；填充且过填充TSV开口。一旦已填充TSV开口，便可通过平坦化工艺(例如化学机械抛光(CMP))移除TSV开口外部的过量衬层、阻障层、第三晶种层及第一导电材料，但可使用任何合适移除工艺。
一旦已填充TSV开口，便可薄化第四半导体装置107的第四衬底的背面以暴露TSV开口且形成TSV 801。在实施例中，一旦已暴露TSV 801，便可使用例如CMP及研磨工艺以移除第四半导体装置107的第四衬底的材料而薄化第四半导体装置107的第四衬底，且平坦化第四半导体装置107的第四衬底及TSV 801。在另一实施例中，还可使用一或多个蚀刻工艺或其它移除工艺来移除第四衬底的材料且暴露TSV 801。
关于贯穿第五半导体装置109的第五衬底的TSV 801，可利用类似工艺来形成贯穿第五半导体装置109的TSV 801。例如，可在第五衬底内形成开口，可使用导电材料加衬里于所述开口及填充所述开口，且可薄化第五衬底以便暴露导电材料。然而，可利用任何合适工艺以形成贯穿第四半导体装置107及第五半导体装置109的TSV 801。
一旦已在第四半导体装置107及第五半导体装置109中形成TSV 801(且已执行任何其它所需处理，例如有源装置或金属层的形成)，便可放置第四半导体装置107及第五半导体装置109且运用通孔111囊封第四半导体装置107及第五半导体装置109，如上文关于图2A到3所述。另外，可在第四半导体装置107、第五半导体装置109及第二囊封剂419上方形成第二重布层301。然而，在此实施例中，也将电连接第二重布层301 与贯穿第四半导体装置107及第五半导体装置109的TSV 801，而非对通孔111重新布线。因而，还可使用第二重布层301以使第四半导体装置107、第五半导体装置109及通孔111互连。
通过形成贯穿第四半导体装置107及第五半导体装置109的TSV 801，可提供额外布线选择。另外，可将第四半导体装置107及第五半导体装置109连接到第二重布层 301。运用此类选择，可设计并实现更有效布局及连接图案，且可获得总体更有效装置。
图9说明其中形成贯穿第四半导体装置107及第五半导体装置109的TSV 801且将第二重布层301电连接到TSV 801的另一实施例。在此实施例中，除TSV 801以外，也放置第一底胶材料601以便帮助保护及支撑第四半导体装置107及第五半导体装置 109。在此实施例中，第一底胶材料601可如上文关于图6所述般，例如是使用注射工艺以液态形式施配的液态环氧树脂或其它保护性材料。然而，可使用任何合适施配材料或方法。
通过施加第一底胶材料601，可更好地地保护第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)使其免受后续处理步骤影响。例如，第一底胶材料601可对第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)提供额外结构支撑以及额外隔离。此额外支撑及保护将减少或消除第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)的结构故障。
图10说明其中形成贯穿第四半导体装置107及第五半导体装置109的TSV 801的另一实施例。在此实施例中，除形成TSV 801以外(如上文关于图8所述)，未形成第二重布层301，且使第三外部连接器307与通孔111(贯穿例如第一重布层接点垫305)以及 TSV 801直接接合。例如，可将第一重布层接点垫305形成为与TSV 801电连接及/或物理连接，且将第三外部连接器307直接放置于第一重布层接点垫305上方并与第一重布层接点垫305电连接。
通过将第三外部连接器307直接接合到通孔111及也直接接合到TSV 801，在其中第二重布层301是非所需的情境中可避免形成第二重布层301的额外工艺步骤及复杂性。通过减少工艺步骤及简化装置的制造，可更有效地且以更小缺陷机会制造装置。
图11说明类似于图10中的实施例的其中形成贯穿第四半导体装置107及第五半导体装置109的TSV 801且将第三外部连接器307直接接合到通孔111及TSV 801的另一实施例。然而，在此实施例中，也在囊封第四半导体装置107及第五半导体装置109之前施配第一底胶材料601。在此实施例中，第一底胶材料601可如上文关于图6所述般，例如是使用注射工艺以液态形式施配的液态环氧树脂或其它保护性材料。然而，可使用任何合适施配材料或方法。一旦已放置第一底胶材料601，可如上文所述般继续剩余工艺步骤。
通过施加第一底胶材料601，可更好地地保护第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)使其免受后续处理步骤影响。例如，第一底胶材料601可在所选取方向上对第一外部连接器110(在第四半导体装置107上)及第二外部连接器113(在第五半导体装置109上)提供额外结构支撑以及额外隔离。此额外支撑及保护将减少或消除第一外部连接器110(在第四半导体装置107上) 及第二外部连接器113(在第五半导体装置109上)的结构故障。
图12说明其中第一半导体装置401、第二半导体装置403或第三半导体装置405或其所有三者是包括多个个别裸片的裸片堆叠的又另一实施例。在实施例中，可由第一裸片堆叠1201取代第一半导体装置401，所述第一裸片堆叠1201可包括通过使用第三TSV 1209彼此互连的第一裸片1203、第二裸片1205及第三裸片1207。在特定实施例中，第一裸片1203、第二裸片1205及第三裸片1207中的每一者可为例如存储器裸片(例如 DRAM裸片或高带宽存储器裸片)，但第一裸片1203、第二裸片1205及第三裸片1207 可提供任何所需功能性。可使用类似于上文关于第一半导体装置401所述的结构及方法形成第一裸片1203、第二裸片1205及第三裸片1207中的每一者，且一旦形成，便可在放置及囊封之前使第一裸片1203、第二裸片1205及第三裸片1207彼此接合。
类似地，可由第二裸片堆叠1211取代第二半导体装置403，且可由第三裸片堆叠1213取代第三半导体装置405。可利用裸片堆叠及其它半导体装置的任何合适组合，且所有此类组合完全旨在包含于本发明实施例的范围内。
图13A到13B说明其中形成第一重布层309且在放置及囊封第一半导体装置401、第二半导体装置403及第三半导体装置405之前放置第四半导体装置107以及第五半导体装置109的另一实施例。在实施例中，聚合物层105形成于粘合剂层103上且可为聚苯并噁唑(PBO)，但可替代地利用任何合适材料，例如聚酰亚胺或聚酰亚胺衍生物。可使用例如旋涂工艺放置聚合物层105到约0.5μm与约10μm之间(例如约5μm)的厚度，但可替代地使用任何合适方法及厚度。
一旦已形成聚合物层105，便可在聚合物层105上形成第一重布层309。在实施例中，可如上文关于图1所述般形成第一重布层309。例如，可使用沉积以及光刻掩模及蚀刻工艺形成多个导电层及电介质层。然而，可利用用于形成第一重布层309的任何合适工艺。
一旦已在第一载体衬底101上方形成第一重布层309，便可形成通孔111，且在已形成通孔111之后将第四半导体装置107及第五半导体装置109放置于通孔111内，如上文参考图2A所述。另外，在此实施例中，还可将第六半导体装置1301连同第四半导体装置107及第五半导体装置109一起放置于第一重布层309上。在实施例中，第六半导体装置1301可为另一电压调节器且可包括第六衬底、第六有源装置、第六金属层、第三接点垫、第六钝化层(图13A中未单独说明)及第三外部连接器1303。在实施例中，第六衬底、第六有源装置、第六金属层、第三接点垫、第六钝化层及第三外部连接器1303 可类似于第四衬底、第四有源装置、第四金属层、第一接点垫、第四钝化层及第一外部连接器110，但其也可不同。
图13A额外说明第四半导体装置107、第五半导体装置109及第六半导体装置1301的囊封以及第二重布层301、第一重布层接点垫305、第一重布层钝化层303及第三外部连接器307的形成。在实施例中，可囊封第四半导体装置107、第五半导体装置109 及第六半导体装置1301以及通孔111，且可形成第二重布层301、第一重布层接点垫305 及第三外部连接器307，如上文关于图3所述。然而，可利用(若干)任何合适工艺。
图13B说明一旦已形成第三外部连接器307，便可移除第一载体衬底101。在实施例中，可如上文关于图3所述般移除第一载体衬底101。例如，可处理粘合剂层以降低其粘合性，且接着可移除第一载体衬底101及粘合剂层103。另外，在此阶段，如果需要，还可使用例如湿式蚀刻工艺移除聚合物层105。
一旦已移除第一载体衬底101，便可放置第一半导体装置401、第二半导体装置403及第三半导体装置405且使其连接到第一重布层309。在实施例中，在连接第一半导体装置401、第二半导体装置403及第三半导体装置405之前，可将第四外部连接器1305 放置于第一半导体装置401上，可将第五外部连接器1307放置于第二半导体装置403 上，且可将第六外部连接器1309放置于第三半导体装置405上。在实施例中，第四外部连接器1305、第五外部连接器1307及第六外部连接器1309可为包括共晶材料(例如焊料)的微凸块，但可替代地使用任何合适材料。在其中第四外部连接器1305、第五外部连接器1307及第六外部连接器1309是微凸块的实施例中，可使用植球方法(例如直接植球工艺)形成第四外部连接器1305、第五外部连接器1307及第六外部连接器1309。在另一实施例中，可通过以下步骤形成微凸块：最初通过任何合适方法(例如蒸镀、电镀、印刷、焊料转移)形成锡层；及接着执行回焊以便使材料塑形为所需凸块形状。在其中第四外部连接器1305、第五外部连接器1307及第六外部连接器1309是微凸块的实施例中，第一外部连接器110可具有约20μm与约50μm之间的直径。
一旦已将第四外部连接器1305、第五外部连接器1307及第六外部连接器1309放置或形成于第一半导体装置401、第二半导体装置403及第三半导体装置405上，便可将第一半导体装置401、第二半导体装置403及第三半导体装置405对准并接合到第一重布层309。在其中第四外部连接器1305、第五外部连接器1307及第六外部连接器1309 是微凸块的实施例中，可通过以下步骤来接合第一半导体装置401、第二半导体装置403 及第三半导体装置405：将第四外部连接器1305、第五外部连接器1307及第六外部连接器1309对准于第一重布层309的所需暴露部分上；及接着执行回焊以将第一半导体装置401、第二半导体装置403及第三半导体装置405接合到第一重布层309。
替代地，可使用熔合接合工艺或混合接合工艺，将第一半导体装置401、第二半导体装置403及第三半导体装置405接合到第一重布层309。在此类工艺中，未利用第四外部连接器1305、第五外部连接器1307及第六外部连接器1309，且将第一钝化层407、第二钝化层411及第三钝化层415直接接合到第一重布层309的电介质部分(在熔合接合工艺中)，或者，在混合熔合接合工艺中，将第一通孔409、第二通孔413及第三通孔417(除第一钝化层407、第二钝化层411及第三钝化层415以外)直接接合到第一重布层309。然而，可利用任何合适工艺，以将第一半导体装置401、第二半导体装置403及第三半导体装置405接合到第一重布层309。
一旦已将第一半导体装置401、第二半导体装置403及第三半导体装置405接合到第一重布层309，便可将第三外部连接器307接合到衬底421。在实施例中，如上文关于图4所述般，将第三外部连接器307接合到衬底421。然而，可利用任何合适方法。
图14说明第一重布层309与第一半导体装置401、第二半导体装置403及第三半导体装置405中的每一者之间的第二底胶材料1401的放置。在实施例中，第二底胶材料 1401可为类似于第一底胶材料601的材料，且使用类似于第一底胶材料601的工艺加以施配(上文关于图6所述)。例如，第二底胶材料1401可为通过注射工艺施配的环氧树脂材料。然而，可利用任何合适的施配材料或方法。
另外，在图14中所说明的实施例中，于已施配第二底胶材料1401之后，未囊封第一半导体装置401、第二半导体装置403及第三半导体装置405。确切来说，使第一半导体装置401、第二半导体装置403及第三半导体装置405保持未囊封，其中第一半导体装置401、第二半导体装置403及第三半导体装置405的侧壁无囊封材料。
图15说明其中运用第一囊封剂201来囊封第一半导体装置401、第二半导体装置403及第三半导体装置405的另一实施例。在实施例中，如上文关于图1中第一半导体装置401、第二半导体装置403及第三半导体装置405的囊封所述般，囊封第一半导体装置401、第二半导体装置403及第三半导体装置405。例如，可将第一半导体装置401、第二半导体装置403及第三半导体装置405(连同第四半导体装置107、第五半导体装置 109及第六半导体装置1301一起)放置到模穴(未单独说明)中，且可将第一囊封剂201 放置于第一半导体装置401、第二半导体装置403及第三半导体装置405上方。一旦处于适当位置中，如果需要，那么可使用(例如)CMP工艺来平坦化第一囊封剂201、第一半导体装置401、第二半导体装置403及第三半导体装置405直到暴露第一半导体装置 401、第二半导体装置403及第三半导体装置405。然而，可使用任何合适工艺来囊封第一半导体装置401、第二半导体装置403及第三半导体装置405。
图16说明其中未利用第一囊封剂201来囊封第一半导体装置401、第二半导体装置403及第三半导体装置405的另一实施例。在此实施例中，可将散热片1601放置于第一半导体装置401、第二半导体装置403及第三半导体装置405上方，以帮助保护第一半导体装置401、第二半导体装置403及第三半导体装置405，并且移除在第一半导体装置401、第二半导体装置403及第三半导体装置405的操作期间产生的热。在实施例中，可使用(例如)第一热界面材料1603将散热片1601附接到第一半导体装置401、第二半导体装置403及第三半导体装置405。在一些实施例中，作为实例，第一热界面材料1603 包括环氧树脂、聚硅氧、无机材料(例如轻度交联聚硅氧聚合物、一或多种基质聚合物、具有一或多个导热填充剂、其它材料或多个层的聚合物)或其组合。在其中第一热界面材料1603包括基质聚合物的实施例中，所述基质聚合物可包括乙烯-丙烯、乙烯-丙烯-二烯单体、氢化聚异戊二烯或其组合。在其中第一热界面材料1603包括导热填充剂的实施例中，所述导热填充剂可包含氧化铝、氮化硼、氮化铝、铝、铜、银、铟或其组合。在一些实施例中，作为实例，所述导热填充剂是施配于第一热界面材料1603内，且在第一热界面材料1603内具有约10重量百分比到约90重量百分比的百分比重量。替代地，第一热界面材料1603可包括其它材料、填充剂及性质。使用第一热界面材料1603，以通过填入在微小不均匀表面内所产生的显微气囊(例如第一半导体装置401、第二半导体装置403及第三半导体装置405的表面与散热片1601的表面之间的区)来改进电传导及/或热传导。
在一些实施例中，可将第一半导体装置401、第二半导体装置403及第三半导体装置405电连接且热连接到散热片1601且最终到散热器(图16中未单独说明)。对于此实例，可使用含有悬浮于聚硅氧油脂中的银、镍或铝颗粒的金属基导热膏。在其中第一半导体装置401、第二半导体装置403及第三半导体装置405可仅想要到所述散热器的热传导的替代实施例中，可施加填充有陶瓷粉末的非导电陶瓷基膏，例如氧化铍、氮化铝、氧化铝或氧化锌。此外，一些实施例可不利用第一导热膏。
在一些实施例中，尤其对于高功率应用，可部署散热片1601以对第一半导体装置401、第二半导体装置403及第三半导体装置405供应电路径及/或热路径以将从第一半导体装置401、第二半导体装置403及第三半导体装置405产生的热散布于较大区上方。在实施例中，散热片1601可包括铜、铝、其它金属、合金、其组合或具有高导电性及导热性的其它材料。另外，所述散热片可从第一半导体装置401、第二半导体装置403 及第三半导体装置405附接到衬底421的顶部表面以建立到衬底421的电连接。
散热器可安装于散热片以及第一半导体装置401、第二半导体装置403及第三半导体装置405上方且热耦合到散热片以及第一半导体装置401、第二半导体装置403及第三半导体装置405。可使用展现高导热性的材料形成散热器，例如铝、铜、钻石、其它金属、合金、其组合及类似者。所述散热器通过增大暴露于环绕其的冷却剂(例如空气) 的给定表面积而协助冷却第一半导体装置401、第二半导体装置403及第三半导体装置 405。热转移机制通过周围空气的对流、通过空气传导及辐射而发生。例如，与第一半导体装置401、第二半导体装置403及第三半导体装置405的表面积相比，通过采用以几何形鳍片矩阵或笔直或喇叭形鳍片阵列的形式的大量鳍片，散热器可展现更大对流表面积。在例如其中对流为低的另一实施例中，在可见光谱中，磨砂黑表面色彩可比闪亮金属色彩更有效地辐射。可替代地利用散热器的任何合适形式。
根据实施例，提供一种包括第一半导体装置的半导体装置，其中所述第一半导体装置包括第一电压调节器。囊封剂囊封所述第一半导体装置且贯穿通孔与所述第一半导体装置分离且从所述囊封剂的第一侧延伸到所述囊封剂的第二侧。第一重布层在所述囊封剂的第一侧上电连接到所述贯穿通孔，且第二半导体装置通过所述第一重布层电连接到所述第一半导体装置，其中所述第二半导体装置包括第一逻辑装置。
根据另一实施例，提供一种包括囊封剂的半导体装置，所述囊封剂具有第一侧及与所述第一侧相对的第二侧。贯穿通孔从所述第一侧延伸到所述第二侧且第一电压调节器裸片从所述第一侧延伸到所述第二侧。第一重布层电连接到所述贯穿通孔及所述第一电压调节器裸片，且第一逻辑裸片通过所述第一重布层电连接到所述第一电压调节器裸片。
根据又另一实施例，提供一种制造半导体装置的方法，其包括运用第一囊封剂囊封通孔及第一电压调节器裸片，其中所述第一囊封剂与所述通孔物理接触。在所述第一囊封剂的第一侧上形成第一重布层，所述第一重布层与所述通孔电连接，且将第一逻辑裸片接合到所述第一重布层，所述第一逻辑裸片与所述第一电压调节器裸片电连接。
根据又另一实施例，提供一种制造半导体装置的方法，其包括在第一半导体裸片上方形成第一重布层，其中所述第一半导体裸片是逻辑裸片。在所述第一重布层的与所述第一半导体裸片相对的侧上形成通孔，且将第一集成式电压调节器放置成邻近于所述通孔。囊封所述第一集成式电压调节器及所述通孔。
前文概述若干实施例的特征使得所属领域技术人员可更好地地理解本揭露的方面。所属领域技术人员应明白，其可容易将本揭露用作用于设计或修改其它工艺及结构的基础以实行相同目的及/或实现本文中所介绍的实施例的相同优点。所属领域技术人员还应认知，此类等效构造不背离本揭露的精神及范围，且其可在不背离本揭露的精神及范围的情况下在本文中作出各种改变、置换及更改。
[符号说明]
101 第一载体衬底
103 粘合剂层
105 聚合物层
107 第四半导体装置
109 第五半导体装置
110 第一外部连接器
111 通孔
113 第二外部连接器
201 第一囊封剂
301 第二重布层
303 第一重布层钝化层
305 第一重布层接点垫
307 第三外部连接器
309 第一重布层
401 第一半导体装置
403 第二半导体装置
405 第三半导体装置
407 第一钝化层
409 第一通孔
411 第二钝化层
413 第二通孔
415 第三钝化层
417 第三通孔
419 第二囊封剂
421 衬底
423 第四外部连接件
601 第一底胶材料
801 贯穿硅通孔(TSV)
1201 第一裸片堆叠
1203 第一裸片
1205 第二裸片
1207 第三裸片
1209 第三贯穿硅通孔(TSV)
1211 第二裸片堆叠
1213 第三裸片堆叠
1301 第六半导体装置
1303 第三外部连接器
1305 第四外部连接器
1307 第五外部连接器
1309 第六外部连接器
1401 第二底胶材料
1601 散热片
1603 第一热界面材料

Claims (25)

1.一种半导体装置，其包括：
第一半导体装置，其中所述第一半导体装置包括第一电压调节器；
第二半导体装置，其中所述第二半导体装置包括第二电压调节器；
囊封剂，其囊封所述第一半导体装置及所述第二半导体装置；
贯穿通孔，其与所述第一半导体装置及所述第二半导体装置分离，且设置于所述第一半导体装置及所述第二半导体装置之间，且从所述囊封剂的第一侧延伸到所述囊封剂的第二侧；
第一重布层，其在所述囊封剂的第一侧上电连接到所述贯穿通孔；
第三半导体装置，其是通过所述第一重布层电连接到所述第一半导体装置，其中所述第三半导体装置包括第一逻辑装置；及
第二重布层，其在所述囊封剂的第二侧上与所述第一半导体装置、所述第二半导体装置及所述贯穿通孔互连。
2.根据权利要求1所述的半导体装置，其进一步包括外部连接器，其在所述第一半导体装置之上，且被所述囊封剂囊封。
3.根据权利要求2所述的半导体装置，其进一步包括第四半导体装置，所述第四半导体装置电连接到所述第一重布层，且位于所述第一重布层的与所述第二半导体装置相对的侧上，所述第四半导体装置包括第二逻辑装置。
4.根据权利要求3所述的半导体装置，其进一步包括：
第五半导体装置，其电连接到所述第一重布层，且位于所述第一重布层的与所述第二半导体装置相对的侧上，所述第五半导体装置包括输出入装置；及
第二囊封剂，其囊封所述第三半导体装置、所述第四半导体装置及所述第五半导体装置。
5.根据权利要求1所述的半导体装置，其中所述第一半导体装置包括贯穿硅通孔。
6.根据权利要求1所述的半导体装置，其中所述第三半导体装置的侧壁无囊封剂。
7.根据权利要求1所述的半导体装置，其进一步包括与所述第一半导体装置物理接触的底胶材料。
8.一种半导体装置，其包括：
衬底；
囊封剂，其在所述衬底之上，且具有第一侧及与所述第一侧相对的第二侧；
贯穿通孔，其从所述第一侧延伸到所述第二侧；
第一电压调节器裸片，其从所述第一侧延伸到所述第二侧；
第一重布层，其电连接到所述贯穿通孔及所述第一电压调节器裸片；
第一逻辑裸片，其是通过所述第一重布层电连接到所述第一电压调节器裸片；及
散热片，其放置于所述第一逻辑裸片之上，且从所述第一逻辑裸片附接到所述衬底的顶部表面。
9.根据权利要求8所述的半导体装置，其进一步包括从所述第一侧延伸到所述第二侧的第二电压调节器。
10.根据权利要求9所述的半导体装置，其进一步包括电连接到所述第一重布层的第二逻辑裸片。
11.根据权利要求10所述的半导体装置，其进一步包括电连接到所述贯穿通孔的输出入裸片。
12.根据权利要求8所述的半导体装置，其进一步包括位于所述第一电压调节器裸片的与所述第一逻辑裸片相对的侧上的第二重布层。
13.根据权利要求12所述的半导体装置，其进一步包括延伸贯穿所述第一电压调节器裸片且电连接到所述第二重布层的贯穿硅通孔。
14.根据权利要求8所述的半导体装置，其进一步包括底胶材料，其环绕所述第一电压调节器裸片，且被所述囊封剂囊封。
15.一种制造半导体装置的方法，所述方法包括：
形成第一重布层；
在所述第一重布层之上形成通孔及第一电压调节器裸片，所述第一重布层与所述通孔电连接；
运用第一囊封剂来囊封所述通孔及所述第一电压调节器裸片，其中所述第一囊封剂与所述通孔物理接触；
将第一逻辑裸片接合到所述第一重布层，所述第一逻辑裸片与所述第一电压调节器裸片电连接；
将第二逻辑裸片接合到所述第一重布层；及
运用第二囊封剂来囊封所述第一逻辑裸片及所述第二逻辑裸片。
16.根据权利要求15所述的方法，其进一步包括：
在所述第一电压调节器裸片之上形成外部连接器；及
运用所述第一囊封剂来囊封所述外部连接器。
17.根据权利要求15所述的方法，其中所述囊封所述通孔及所述第一电压调节器裸片进一步包括运用所述第一囊封剂来囊封第二电压调节器。
18.根据权利要求15所述的方法，其进一步包括在所述第一囊封剂的与所述第一重布层相对的侧上形成第二重布层。
19.根据权利要求18所述的方法，其中所述形成所述第二重布层使所述第二重布层与延伸贯穿所述第一电压调节器裸片的贯穿通孔电连接。
20.根据权利要求15所述的方法，其进一步包括在与所述第一重布层相对的所述第一囊封剂的第二侧上，外部连接件与所述通孔直接接合。
21.一种制造半导体装置的方法，所述方法包括：
运用囊封剂来囊封第一半导体裸片及第二半导体裸片；
在所述第一半导体裸片及所述第二半导体裸片上方形成第一重布层，其中所述第一半导体裸片及所述第二半导体裸片是逻辑裸片；
将所述第一半导体裸片及所述第二半导体裸片接合到所述第一重布层；
在所述第一重布层的与所述第一半导体裸片相对的侧上形成通孔；
将第一集成式电压调节器放置成邻近于所述通孔；及
囊封所述第一集成式电压调节器及所述通孔，
其中所述第一集成式电压调节器包括贯穿所述第一集成式电压调节器的贯穿硅通孔。
22.根据权利要求21所述的方法，其中在所述形成所述第一重布层之前囊封所述第一半导体裸片及所述第二半导体裸片。
23.根据权利要求21所述的方法，其进一步包括在所述第一集成式电压调节器的与所述第一重布层相对的侧上形成第二重布层。
24.根据权利要求21所述的方法，其进一步包括将底胶材料施配于所述第一重布层与所述第一集成式电压调节器之间。
25.根据权利要求21所述的方法，其中所述第一集成式电压调节器由外部连接器与所述第一重布层接合。
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