TW201721828A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201721828A
TW201721828A TW105140001A TW105140001A TW201721828A TW 201721828 A TW201721828 A TW 201721828A TW 105140001 A TW105140001 A TW 105140001A TW 105140001 A TW105140001 A TW 105140001A TW 201721828 A TW201721828 A TW 201721828A
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Taiwan
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semiconductor device
layer
redistribution layer
external connector
die
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TW105140001A
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TWI626727B (zh
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余振華
張智援
王垂堂
謝政憲
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種方法及裝置，其中運用一囊封劑來囊封一第一半導體裝置及一通孔。一重佈層將該第一半導體裝置連接至一第二半導體裝置。在一特定實施例中，該第一半導體裝置係一整合式電壓調節器，且該第二半導體裝置係一邏輯裝置，諸如一中央處理單元。

Description

半導體裝置及其製造方法
本發明實施例係有關半導體裝置及其製造方法。
半導體裝置用於各種電子應用中，作為實例，諸如個人電腦、手機、數位相機及其他電子設備。通常藉由以下步驟製造半導體裝置：將材料之各個絕緣層或介電層、導電層及半導體層循序地沈積於一半導體基板上；及使用微影圖案化各個材料層以在各個材料層上形成電路組件及元件。通常將幾十或幾百個積體電路製造於一單一半導體晶圓上。藉由沿一切割道鋸切積體電路而單粒化個別晶粒。 一旦單粒化，接著可運用彼此互補工作之其他裝置封裝個別晶粒。當不期望將全部所要功能性放置至一單一晶粒中時，此封裝係有用的。例如，若一個功能性可能干擾其他功能性，則可期望使不同晶粒互連，其中各晶粒執行所要功能性而無來自其他晶粒之過度干擾。然而，單獨晶粒上不同功能性之此互連導致應解決之其他問題。
本發明之實施例提供一種包括一第一半導體裝置之半導體裝置，其中該第一半導體裝置包括一第一電壓調節器。一囊封劑囊封該第一半導體裝置且一貫穿通孔與該第一半導體裝置分離且從該囊封劑之一第一側延伸至該囊封劑之一第二側。一第一重佈層在該囊封劑之一第一側上電連接至該貫穿通孔，且一第二半導體裝置透過該第一重佈層電連接至該第一半導體裝置，其中該第二半導體裝置包括一第一邏輯裝置。 根據本發明另一實施例，提供一種包括一囊封劑之半導體裝置，該囊封劑具有一第一側及與該第一側相對之一第二側。一貫穿通孔從該第一側延伸至該第二側且一第一電壓調節器晶粒從該第一側延伸至該第二側。一第一重佈層電連接至該貫穿通孔及該第一電壓調節器晶粒，且一第一邏輯晶粒透過該第一重佈層電連接至該第一電壓調節器晶粒。 根據本發明又另一實施例，提供一種製造一半導體裝置之方法，其包括運用一第一囊封劑囊封一通孔及一第一電壓調節器晶粒，其中該第一囊封劑與該通孔實體接觸。在該第一囊封劑之一第一側上形成一第一重佈層，該第一重佈層與該通孔電連接，且將一第一邏輯晶粒接合至該第一重佈層，該第一邏輯晶粒與該第一電壓調節器晶粒電連接。 根據本發明又另一實施例，提供一種製造一半導體裝置之方法，其包括在一第一半導體晶粒上方形成一第一重佈層，其中該第一半導體晶粒係一邏輯晶粒。在該第一重佈層相對該第一半導體晶粒之一側上形成通孔，且將一第一整合式電壓調節器放置成鄰近於該等通孔。囊封該第一整合式電壓調節器及該等通孔。
下文揭露提供用於實施本發明之不同特徵之諸多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅係實例且並非旨在限制。例如，在下文描述中，將一第一構件形成在一第二構件上方或上可包含其中將該第一構件及該第二構件形成為直接接觸之實施例，且亦可包含其中可在該第一構件與該第二構件之間形成額外構件使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭露可在各個實例中重複元件符號及/或字母。此重複用於簡化及清晰之目的且自身不指示所論述之各項實施例及/或組態之間的一關係。 此外，為了方便描述，可在本文中使用空間相關術語(諸如「下面」、「下方」、「下」、「上方」、「上」及類似者)以描述如圖中所繪示之一個元件或構件與另一(些)元件或構件之關係。除圖中所描繪之定向以外，空間相關術語旨在涵蓋使用中或操作中裝置之不同定向。設備可以其他方式定向(旋轉90度或呈其他定向)，且據此可同樣解釋本文中所使用之空間相關描述符。 現參考圖1，其展示具有一黏著層103之一第一載體基板101。第一載體基板101包括例如矽基材料(諸如玻璃或氧化矽)或其他材料(諸如氧化鋁)或任何此等材料之組合或類似者。第一載體基板101係平坦的以便容納半導體裝置(諸如一第一半導體裝置401、一第二半導體裝置403及一第三半導體裝置405)之一附接。 黏著層103放置於第一載體基板101上以便協助上覆結構之黏著。在一實施例中，黏著層103可包括一紫外線膠，該紫外線膠在暴露於紫外光時失去其黏著性質。然而，亦可使用其他類型之黏著劑，諸如壓敏黏著劑、輻射可固化黏著劑、環氧樹脂、此等黏著劑之組合或類似者。黏著層103可以可容易在壓力下變形之一半液體或凝膠形式放置至第一載體基板101上。 一旦已形成黏著層103，可將一第一半導體裝置401、一第二半導體裝置403及一第三半導體裝置405放置於黏著層103上。在一實施例中，第一半導體裝置401可係例如一邏輯晶粒(諸如一中央處理單元(CPU))，其經設計以結合一第四半導體裝置107 (圖1中未繪示但下文關於圖2A至圖2B進一步繪示及描述)、一第五半導體裝置109 (圖1中亦未繪示但下文關於圖2A至圖2B繪示及描述)、第二半導體裝置403及第三半導體裝置405工作。然而，第一半導體裝置401可係任何合適半導體裝置，諸如一圖形處理單元、記憶體、一高速輸出入端(I/O)或類似者。 在一實施例中，第一半導體裝置401可包括一第一基板(未個別地繪示)、第一主動裝置(未個別地繪示)、第一金屬層、一第一重佈層、一第一鈍化層407及第一通孔409。該第一基板可包括塊狀矽(摻雜或無摻雜)或一絕緣體上覆矽(SOI)基板之一主動層。通常，一SOI基板包括一半導體材料層，諸如矽、鍺、矽鍺、SOI、絕緣體上覆矽鍺(SGOI)或其等之組合。可使用之其他基板包含多層基板、梯度基板或混合定向基板。 第一主動裝置包括可用來產生第一半導體裝置401 (例如，GPU)之設計之所要結構及功能需求的廣泛多種主動裝置及被動裝置，諸如電容器、電阻器、電感器及類似者。可使用任何合適方法而在第一基板內或在第一基板上別處形成第一主動裝置。 第一金屬層形成於第一基板及第一主動裝置上方且經設計以連接各種主動裝置以形成功能電路。在一實施例中，第一金屬層係由介電材料及導電材料之交替層形成且可透過任何合適製程(諸如沈積、鑲嵌、雙鑲嵌等)而形成。在一實施例中，可存在藉由至少一個層間介電層(ILD)與第一基板分離之四個金屬層，但第一金屬層之精確數目取決於第一半導體裝置401之設計。 第一重佈層可形成於第一金屬層上方且與第一金屬層電接觸。第一重佈層可包括鋁，但可替代地使用其他材料，諸如銅。可使用一沈積製程(諸如濺鍍)以形成一材料層(未展示)而形成第一重佈層且接著可透過一合適製程(諸如光微影遮罩及蝕刻)移除該材料層之部分以形成第一重佈層。然而，可利用任何其他合適製程來形成第一重佈層。 第一鈍化層407可形成於第一基板上第一金屬層及第一重佈層上方。第一鈍化層407可由一或多種合適介電材料製成，諸如聚醯亞胺、氧化矽、氮化矽、低介電係數介電質(諸如碳摻雜之氧化物)、極低介電係數介電質(諸如多孔碳摻雜之二氧化矽)、此等材料之組合或類似者。第一鈍化層可透過一製程(諸如化學氣相沈積(CVD))而形成，但可利用任何合適製程且可具有約0.5 μm與約5 μm之間(諸如約9.25 KÅ)的一厚度。 一旦已形成第一鈍化層407，便可形成貫穿第一鈍化層407之第一通孔409使之與第一重佈層接觸。在一實施例中，可藉由最初使用例如一光微影遮罩及蝕刻製程圖案化貫穿第一鈍化層407之一開口而形成第一通孔409。一旦已形成一開口，可使用一製程(諸如電鍍、濺鍍或類似者)運用一材料(諸如銅、鋁或鎢)填充或過填充該開口。一旦沈積，可使用例如一平坦化製程(諸如化學機械拋光)移除留在該開口外部之任何導電材料。 第二半導體裝置403可係例如經設計以結合第四半導體裝置107、第五半導體裝置109、第一半導體裝置401 (例如，CPU)及第三半導體裝置405工作之另一中央處理單元。然而，第二半導體裝置403可係任何合適半導體裝置，諸如一GPU、一記憶體、一高速I/O或類似者。 在一實施例中，第二半導體裝置403可包括一第二基板、第二主動裝置(未個別地繪示)、第二金屬層(未個別地繪示)、第二重佈層(未個別地繪示)、一第二鈍化層411及第二通孔413。在一實施例中，第二基板、第二主動裝置、第二金屬層、第二重佈層、第二鈍化層411及第二通孔413可類似於第一基板、第一主動裝置、第一金屬層、第一重佈層、第一鈍化層407及第一通孔409，但其等亦可不同。 第三半導體裝置405可係例如經設計以結合第四半導體裝置107、第五半導體裝置109、第一半導體裝置401 (例如，CPU)及第二半導體裝置403 (例如，CPU)工作之一輸入/輸出裝置。然而，第三半導體裝置405可係任何合適半導體裝置，諸如一CPU、一GPU、一記憶體或類似者。 在一實施例中，第三半導體裝置405可包括一第三基板、第三主動裝置(未個別地繪示)、第三金屬層(未個別地繪示)、第三重佈層(未個別地繪示)、一第三鈍化層415及第三通孔417。在一實施例中，第三基板、第三主動裝置、第三金屬層、第三重佈層、第三鈍化層415及第三通孔417可類似於第一基板、第一主動裝置、第一金屬層、第一重佈層、第一鈍化層407及第一通孔409，但其等亦可不同。 在一實施例中，可使用例如一取放製程將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405放置至黏著層103上。然而，亦可利用放置第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之任何其他方法。 一旦已放置第一半導體裝置401、第二半導體裝置403及第三半導體裝置405，可運用一第一囊封劑201囊封第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。該囊封可在一成型裝置(圖1中未個別地繪示)中執行，該成型裝置可包括一頂部成型部分及可與該頂部成型部分分離之一底部成型部分。在將該頂部成型部分降低至鄰近於該底部成型部分時，可針對第一載體基板101、第一半導體裝置401、第二半導體裝置403及第三半導體裝置405形成一模穴。 在囊封製程期間，可將頂部成型部分放置成鄰近於底部成型部分，藉此將第一載體基板101、第一半導體裝置401、第二半導體裝置403及第三半導體裝置405圍封於模穴內。一旦圍封，頂部成型部分及底部成型部分可形成一氣密密封以便控制來自模穴之氣體之流入量及流出量。一旦密封，可將第一囊封劑201放置於模穴內。第一囊封劑201可係模塑料樹脂，諸如聚醯亞胺、PPS、PEEK、PES、耐熱晶體樹脂、此等材料之組合或類似者。第一囊封劑201可在對準頂部成型部分及底部成型部分之前放置於模穴內，或以其他方式可透過一注射埠注射至模穴中。 一旦已將第一囊封劑201放置至模穴中使得第一囊封劑201囊封第一載體基板101、第一半導體裝置401、第二半導體裝置403及第三半導體裝置405，便可固化第一囊封劑201以便硬化第一囊封劑201以用於最佳保護。雖然確切固化製程至少部分取決於針對第一囊封劑201選取之特定材料，但在其中選取模塑料作為第一囊封劑201之一實施例中，固化可透過一製程(諸如將第一囊封劑201加熱至約100ºC與約130ºC之間(諸如約125ºC)達約60秒至約3000秒(諸如約600秒))而發生。另外，引發劑及/或催化劑可包含於第一囊封劑201內以更佳地控制固化製程。 然而，如一般技術者將認知，上文所述之固化製程僅係一例示性製程且並非意在限制本發明實施例。可替代地使用其他固化製程，諸如照射或甚至允許第一囊封劑201在室溫下硬化。可使用任何合適固化製程，且所有此等製程完全旨在包含於本文中所論述之實施例之範疇內。 圖1亦繪示薄化第一囊封劑201以便暴露第一通孔409 (在第一半導體裝置401上)、第二通孔413 (在第二半導體裝置403上)及第三通孔417 (在第三半導體裝置405上)以用於進一步處理。該薄化可例如使用一機械研磨或化學機械拋光(CMP)製程來執行，藉此利用化學蝕刻劑及磨料以使第一囊封劑201起化學反應且磨掉第一囊封劑201直至已暴露第一通孔409、第二通孔413及第三通孔417。因而，第一半導體裝置401、第二半導體裝置403及第三半導體裝置405可具有亦與第一囊封劑201齊平之一平坦表面。 然而，雖然提出上文所述之CMP製程作為一項闡釋性實施例，但其並非旨在限制實施例。可替代地使用任何其他合適移除製程來薄化第一囊封劑201，且暴露第一通孔409、第二通孔413及第三通孔417。例如，可利用一系列化學蝕刻。可替代地利用此製程及任何其他合適製程來薄化第一囊封劑201，且所有此等製程完全旨在包含於實施例之範疇內。 圖1額外地繪示與第一通孔409、第二通孔413及第三通孔417電連接之一第一重佈層309之一形成。在一實施例中，可藉由最初形成一RDL鈍化層(圖1中未單獨標記)而形成第一重佈層309。在一實施例中，該RDL鈍化層可係聚苯并唑(PBO)，但可替代地利用任何合適材料，諸如聚醯亞胺或聚醯亞胺衍生物。可使用例如一旋塗製程將該RDL鈍化層放置至約5 µm與約25 µm之間(諸如約7 µm)的一厚度，但可使用任何合適方法及厚度。 一旦已放置RDL鈍化層，可圖案化RDL鈍化層以便允許例如第一通孔409、第二通孔413及第三通孔417與一後續形成的導電材料之間的電連接。在一實施例中，可使用一光微影遮罩及蝕刻製程圖案化RDL鈍化層，藉此一光阻劑經放置，暴露於一能源，經顯影且接著在一蝕刻製程期間被用作一遮罩。然而，可使用任何合適方法來形成並圖案化RDL鈍化層。 一旦已圖案化RDL鈍化層，透過一合適形成製程(諸如CVD或濺鍍)形成鈦銅合金之一第一晶種層(未展示)。接著可形成一光阻劑(亦未展示)以覆蓋該第一晶種層，且接著可圖案化該光阻劑以暴露該第一晶種層中定位於第一重佈層309期望定位之處的該等部分。 一旦已形成並圖案化光阻劑，可透過一沈積製程(諸如鍍覆)而在第一晶種層上形成一導電材料，諸如銅。該導電材料可形成為具有約1 μm與約10 μm之間(諸如5 μm)的一厚度。然而，雖然所論述之材料及方法適於形成該導電材料，但此等材料僅係例示性的。可替代地使用任何其他合適材料(諸如AlCu或Au)及任何其他合適形成製程(諸如CVD或PVD)來形成第一重佈層309。 一旦已形成導電材料，可透過一合適移除製程(諸如灰化)移除光阻劑。另外，在移除光阻劑之後，可透過例如將導電材料用作一遮罩之一合適蝕刻製程移除第一晶種層中由光阻劑覆蓋之該等部分。 在已形成導電材料之後，可重複RDL鈍化層及導電材料之形成以便形成一第二導電材料層。可重複製程之此一重複以形成一第二介電及導電材料層級。另外，雖然在圖1中僅繪示三個層，但製程可重複任何次數以提供所要互連性。 圖2A至圖2B繪示通孔111之一形成以及第四半導體裝置107及第五半導體裝置109之一放置。在一實施例中，可藉由最初在第一重佈層309上方形成一第二晶種層(圖1A中未單獨繪示)而形成通孔111。在一實施例中，用於通孔111之第二晶種層係協助在後續處理步驟期間形成一較厚層的一導電材料之一薄層。該第二晶種層可包括約1,000 Å厚之一鈦層，然後係約5,000 Å厚之一銅層。取決於所要材料，可使用諸如濺鍍、蒸鍍或PECVD製程之製程產生該第二晶種層。該第二晶種層可形成為具有約0.3 μm與約1 μm之間(諸如約0.5 μm)的一厚度。 一旦已形成第二晶種層，便在第二晶種層上放置並圖案化一光阻劑(圖2A中未繪示)。在一實施例中，可使用例如一旋塗技術而在第二晶種層上放置該光阻劑至約50 μm與約250 μm之間(諸如約120 μm)的一高度。一旦在適當位置處，接著便可藉由以下步驟圖案化該光阻劑：將該光阻劑暴露於一圖案化能源(例如，一圖案化光源)以便引發一化學反應，藉此引發該光阻劑中暴露於該圖案化光源之該等部分之一物理變化。接著將一顯影劑施加於該暴露光阻劑以利用物理變化，且取決於所要圖案選擇性地移除該光阻劑之暴露部分或該光阻劑之未暴露部分。 在一實施例中，形成至光阻劑中之圖案係通孔111之一圖案(其亦可稱為貫穿InFO通孔或TIV)。通孔111以定位於隨後附接的裝置(諸如第四半導體裝置107及第五半導體裝置109)之不同側上之一放置形成。然而，可利用用於通孔111之圖案之任何合適配置，諸如經定位使得第四半導體裝置107及第五半導體裝置109放置於通孔111之相對側上。 在一實施例中，在光阻劑內形成通孔111。在一實施例中，通孔111包括一或多個導電材料，諸如銅、鎢、其他導電金屬或類似者，且可例如藉由電鍍、無電式電鍍或類似者而形成。在一實施例中，使用一電鍍製程，其中將第二晶種層及光阻劑浸沒或沉浸於一電鍍溶液中。第二晶種層表面電連接至一外部DC電源供應器之負側使得第二晶種層在電鍍製程中用作陰極。一固態導電陽極(諸如銅陽極)亦沉浸於該溶液中且附接至該電源供應器之正側。來自該陽極之原子溶解於該溶液中，陰極(例如，第二晶種層)從該溶液獲取該溶解原子，藉此將第二晶種層之暴露導電區鍍覆於光阻劑之開口內。 一旦已使用光阻劑及第二晶種層形成通孔111，可使用一合適移除製程移除光阻劑。在一實施例中，可使用一電漿灰化製程來移除光阻劑，藉此可增大光阻劑之溫度直至光阻劑經歷一熱分解且可被移除。然而，可替代地利用任何其他合適製程，諸如一濕式剝離。光阻劑之移除可暴露第二晶種層之下伏部分。 一旦已暴露，可執行第二晶種層之暴露部分之一移除。在一實施例中，可藉由例如一濕式或乾式蝕刻製程移除第二晶種層之暴露部分(例如，未被通孔111覆蓋之該等部分)。例如，在一乾式蝕刻製程中，可使用通孔111作為遮罩而引導反應物朝向第二晶種層。在另一實施例中，可將蝕刻劑噴塗成或以其他方式放置成與第二晶種層接觸以便移除第二晶種層之暴露部分。 圖2B繪示將附接於通孔111內之第四半導體裝置107之一特寫圖。在一實施例中，第四半導體裝置107可係供應及/或控制供應至例如第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之電壓之一電壓調節器。在其中第四半導體裝置107係一電壓調節器之一實施例中，第四半導體裝置107可供應約0.6 V與約2.5 V之間(諸如約1.2 V)的一電壓。然而，可由第四半導體裝置107供應任何合適電壓。 在一實施例中，第四半導體裝置107包括一第四基板(未個別地繪示)、第四主動裝置(未個別地繪示)、第四金屬層(未個別地繪示)、第一接點墊、一第四鈍化層及第一外部連接器110。在一特定實施例中，第四基板、第四主動裝置及第四金屬層可由類似於上文關於第一基板、第一主動裝置及第一金屬層所論述之材料且使用類似於上文關於第一基板、第一主動裝置及第一金屬層所論述之製程而形成，但可利用任何合適材料或製程。 第一接點墊可形成於第四金屬層上方且與第四金屬層電接觸。第一接點墊可包括鋁，但可替代地使用其他材料，諸如銅。可使用一沈積製程(諸如濺鍍)以形成一材料層(未展示)而形成第一接點墊且接著可透過一合適製程(諸如光微影遮罩及蝕刻)移除該材料層之部分以形成第一接點墊。然而，可利用任何其他合適製程來形成接點墊。第一接點墊可形成為具有介於約0.5 μm與約4 μm之間(諸如約1.45 μm)的一厚度。 第四鈍化層可形成於第四基板上第四金屬層及第一接點墊上方。第四鈍化層可由一或多種合適介電材料製成，諸如氧化矽、氮化矽、低介電係數介電質(諸如碳摻雜之氧化物)、極低介電係數介電質(諸如多孔碳摻雜之二氧化矽)、此等材料之組合或類似者。第四鈍化層可透過一製程(諸如化學氣相沈積(CVD))而形成(但可利用任何合適製程)，且可具有約0.5 μm與約5 μm之間(諸如約9.25 KÅ)的一厚度。 可形成第一外部連接器110以提供用於第一接點墊與例如第一重佈層309之間的接觸之導電區。在一實施例中，第一外部連接器110可係包括一共晶材料(諸如銲料)之微凸塊，但可替代地使用任何合適材料。在其中第一外部連接器110係微凸塊之一實施例中，可使用一植球方法(諸如一直接植球製程)形成第一外部連接器110。在另一實施例中，可藉由以下步驟形成微凸塊：最初透過任何合適方法(諸如蒸鍍、電鍍、印刷、銲料轉移)形成一錫層；及接著執行一回銲以便使材料塑形為所要凸塊形狀。一旦已形成第一外部連接器110，可執行一測試以確保結構適於進一步處理。在其中第一外部連接器110係微凸塊之一實施例中，第一外部連接器110可具有約20 μm與約50 μm之間的一直徑。 在另一實施例中，第一外部連接器110可係導電柱且可藉由最初在第四鈍化層上方形成一光阻劑(未展示)至約5 μm與約20 μm之間(諸如約10 μm)的一厚度而形成。可圖案化該光阻劑以暴露第四鈍化層之部分，導電柱將延伸貫穿該第四鈍化層。一旦圖案化，接著便可使用該光阻劑作為一遮罩以移除第四鈍化層之所要部分，藉此暴露下伏第一接點墊中將接觸第一外部連接器110之該等部分。 第一外部連接器110可經形成於第四鈍化層及光阻劑兩者之開口內。第一外部連接器110可係由一導電材料(諸如銅)形成，但亦可使用其他導電材料，諸如鎳、金或金屬合金、此等材料之組合，或類似者。另外，可使用一製程(諸如電鍍)來形成第一外部連接器110，藉此一電流通過第一接點墊中第一外部連接器110期望經形成所至之導電部分，且第一接點墊沉浸於一溶液中。該溶液及該電流在開口內沈積(例如，銅)以便填充及/或過填充光阻劑及第四鈍化層之開口，藉此形成第一外部連接器110。接著可使用(例如)一灰化製程、一化學機械拋光(CMP)製程、此等製程之組合或類似者來移除第四鈍化層之開口外部之過量的導電材料及光阻劑。 然而，如一般技術者將認知，用來形成第一外部連接器110之上述製程僅係描述，且並非意在將實施例限於此等確切製程。而是，所述製程旨在闡釋性，此係因為可利用用於形成第一外部連接器110之任何合適製程。所有合適製程完全旨在被包含於本發明實施例之範疇內。 現參考圖2A，圖2A繪示第四半導體裝置107至第一重佈層309上之一放置以及第五半導體裝置109之一放置。在一實施例中，第五半導體裝置109可係另一電壓調節器，且可包括一第五基板、第五主動裝置、第五金屬層、第二接點墊、一第五鈍化層(圖1A中未單獨繪示)及第二外部連接器113。在一實施例中，第五基板、第五主動裝置、第五金屬層、第二接點墊、第五鈍化層及第二外部連接器113可類似於第四基板、第四主動裝置、第四金屬層、第一接點墊、第四鈍化層及第一外部連接器110，但其等亦可不同。在一實施例中，可使用(例如)一取放製程來放置第四半導體裝置107及第五半導體裝置109。然而，亦可利用放置第四半導體裝置107及第五半導體裝置109之任何其他方法。 一旦已將第四半導體裝置107及第五半導體裝置109放置成與第一重佈層309電接觸，便將第四半導體裝置107及第五半導體裝置109接合至第一重佈層309。在其中第一外部連接器110及第二外部連接器113係微凸塊之一實施例中，可藉由一回銲製程來接合第四半導體裝置107及第五半導體裝置109，藉此增大微凸塊之溫度直至微凸塊部分液化並開始流動。一旦隨後降低溫度，微凸塊將重新凝固，藉此將第四半導體裝置107及第五半導體裝置109實體與電接合至第一重佈層309。 在其中第一外部連接器110及第二外部連接器113適合(諸如)係銅柱之另一實施例中，可使用一熔合接合製程，將第四半導體裝置107及第五半導體裝置109接合至第一重佈層309。例如，最初可使用(例如)一濕式清洗程序(諸如SC-1或SC-2清洗程序)來清洗第一重佈層309及(第四半導體裝置107之)第四鈍化層及(第五半導體裝置109之)第五鈍化層內之介電材料的暴露部分，以形成一親水性表面。一旦經清洗，便將第四半導體裝置107及第五半導體裝置109對準至其等各自所要部分中，且將該親水性表面放置成與第一重佈層309實體接觸，以開始接合程序。一旦已接觸第四半導體裝置107及第五半導體裝置109，便可利用一熱退火來強化接合。 然而，如上文所述之熔合接合之描述僅係可用來將第四半導體裝置107及第五半導體裝置109接合至第一重佈層309之另一類型之製程之一實例，其並非旨在限制實施例。而是，可替代地利用任何合適接合製程(諸如混合接合製程，藉此將第四半導體裝置107及第五半導體裝置109之介電部分及導電部分兩者接合至第一重佈層309)以將第四半導體裝置107及第五半導體裝置109接合至第一重佈層309，且所有此等製程完全旨在被包含於實施例內。 圖3繪示通孔111、第四半導體裝置107及第五半導體裝置109之一囊封。在一實施例中，如上文關於第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之囊封所述般囊封通孔111、第四半導體裝置107及第五半導體裝置109。例如，可將第四半導體裝置107及第五半導體裝置109放置至一模穴(未單獨繪示)中且可將一第二囊封劑419放置於第四半導體裝置107及第五半導體裝置109上方。一旦處在適當位置中，若需要，則可使用例如一CMP製程平坦化第二囊封劑419、通孔111、第四半導體裝置107及第五半導體裝置109直至暴露通孔111、第四半導體裝置107及第五半導體裝置109。然而，可使用任何合適製程來囊封第四半導體裝置107及第五半導體裝置109。 圖3繪示形成一第二重佈層301以便使第四半導體裝置107、第五半導體裝置109、通孔111及第三外部連接器307互連。在一實施例中，可使用類似於上文關於第一重佈層309所述之材料及製程形成第二重佈層301。然而，可利用任何合適製程來形成第二重佈層301。 圖3亦繪示在第二重佈層301上方形成第一重佈層接點墊305及一第一重佈層鈍化層303以便針對第二重佈層301及其他下伏結構提供保護及隔離。在一實施例中，第一重佈層接點墊305可形成於第二重佈層301上方且與第二重佈層301電接觸，且可包括鋁，但可替代地使用其他材料，諸如銅。可使用一沈積製程(諸如濺鍍)以形成一材料層(未展示)而形成第一重佈層接點墊305且接著可透過一合適製程(諸如光微影遮罩及蝕刻)移除該材料層之部分以形成第一重佈層接點墊305。然而，可利用任何其他合適製程來形成第一重佈層接點墊305。第一重佈層接點墊305可形成為具有約0.5 μm與約4 μm之間(諸如約1.45 μm)的一厚度。 在第一重佈層接點墊305上方形成第一重佈層鈍化層303以便幫助保護第一重佈層接點墊305及其他下伏結構。在一實施例中，第一重佈層鈍化層303可係聚苯并唑(PBO)，但可替代地利用任何合適材料，諸如聚醯亞胺或聚醯亞胺衍生物。可使用例如一旋塗製程放置第一重佈層鈍化層303至約5 µm與約25 µm之間(諸如約7 µm)的一厚度，但可替代地使用任何合適方法及厚度。 一旦已形成第一重佈層接點墊305，可將第三外部連接器307形成為與第一重佈層接點墊305電連接。在一實施例中，第三外部連接器307可係包括一共晶材料(諸如銲料)之受控倒疊晶片連接(C4)凸塊，但可替代地使用任何合適材料。視情況，可在第三外部連接器307與第一重佈層接點墊305之間利用一凸塊下金屬。在其中第三外部連接器307係C4凸塊之一實施例中，可使用一植球方法(諸如一直接植球製程)形成第三外部連接器307。替代地，可藉由以下步驟形成C4凸塊：最初透過任何合適方法(諸如蒸鍍、電鍍、印刷、銲料轉移)形成一錫層；及接著執行一回銲以便使材料塑形為所要凸塊形狀。一旦已形成第三外部連接器307，便可執行一測試以確保結構適於進一步處理。第三外部連接器307可形成為具有約40 μm與約120 μm之間(諸如約80 μm)的一直徑。 圖3亦繪示第一載體基板101之一去接合。在一實施例中，可將第三外部連接器307及(因此)包含第四半導體裝置107及第五半導體裝置109之結構附接至一環結構(未單獨繪示)。該環結構可係旨在於去接合製程期間及之後對該結構提供支撐及穩定性之一金屬環。在一實施例中，使用例如一紫外線膠帶將第三外部連接器307、第四半導體裝置107及第五半導體裝置109附接至該環結構，但可替代地使用任何其他合適黏著劑或附接件。 一旦將第三外部連接器307及(因此)包含第四半導體裝置107及第五半導體裝置109之結構附接至環結構，便可使用例如一熱製程使第一載體基板101與包含第四半導體裝置107及第五半導體裝置109之結構去接合，以改變黏著層103之黏著性質。在一特定實施例中，利用一能源(諸如紫外線(UV)雷射、二氧化碳(CO2 )雷射或紅外線(IR)雷射)來照射並加熱黏著層103直至黏著層103失去其黏著性質之至少一些。一旦經執行，第一載體基板101及黏著層103便可與包括第三外部連接器307、第四半導體裝置107及第五半導體裝置109之結構實體分離且從該結構移除。 圖4繪示第三外部連接器307至一基板421之一連接。在一實施例中，基板421可係一封裝基板，其包括用來將第四半導體裝置107、第五半導體裝置109、第一半導體裝置401、第二半導體裝置403及第三半導體裝置405連接至其他外部裝置(未單獨繪示)之內部互連件(例如，貫穿矽通孔及金屬層)。在另一實施例中，基板421可係一內插件，其用作一中間基板以將第四半導體裝置107、第五半導體裝置109、第一半導體裝置401、第二半導體裝置403及第三半導體裝置405連接至外部裝置。在此實施例中，基板421可係例如一矽基板(摻雜或無摻雜)或一絕緣體上覆矽(SOI)基板之一主動層。然而，基板421可替代地係可提供一合適保護及/或互連功能性之一玻璃基板、一陶瓷基板、一聚合物基板或任何其他基板。此等及任何其他合適材料可用於基板421。 第四外部連接件423可放置成與基板421接觸且用來提供基板421與其他外部裝置之間的連接能力。在一實施例中，第四外部連接件423可係例如一球柵陣列(BGA)，但可利用任何合適連接件。在其中第四外部連接件423係一球柵陣列之一實施例中，第四外部連接件423可包括諸如錫之一材料或諸如銀、無鉛錫或銅之其他合適材料。在其中第四外部連接件423係錫銲凸塊之一實施例中，可藉由最初透過常用方法(諸如蒸鍍、電鍍、印刷、銲料轉移、植球等)形成一錫層至例如約100 μm之一厚度而形成第四外部連接件423。一旦已在結構上形成一錫層，便可執行一回銲以便使材料塑形為具有例如約150 μm與約350 μm之間(諸如約250 μm)的一直徑之所要凸塊形狀。 藉由在第二囊封劑419以及通孔111內形成第四半導體裝置107 (例如，一整合式電壓調節器)及第五半導體裝置109 (例如，一整合式電壓調節器)且將第四半導體裝置107及第五半導體裝置109連接至第一半導體裝置401 (例如，一CPU)、第二半導體裝置403 (例如，一CPU)及第三半導體裝置405 (例如，一I/O裝置)，可將第四半導體裝置107及第五半導體裝置109放置成比其他解決方案更靠近定位於第一半導體裝置401、第二半導體裝置403及第三半導體裝置405內之切換負載。藉由減小電壓調節器與切換負載之間的實體距離，可解決已困擾其他結構之IR壓降問題，藉此提供具有一緊湊尺寸架構及一減小的板區之高效CPU功率管理之一系統封裝解決方案。另外，在其中第四半導體裝置107及第五半導體裝置109係電壓調節器且第一半導體裝置401及第二半導體裝置403係CPU核心之實施例中，可將能量保存於具有一每核心電壓控制之此一多核心CPU中。 圖5繪示其中在形成第一重佈層接點墊305及第一重佈層鈍化層303之後將第三外部連接器307直接接合於通孔111上方而非形成第二重佈層301以便將通孔111互連至第三外部連接器307的另一實施例。在一特定實施例中，在已(使用例如CMP製程)透過第二囊封劑419暴露通孔111之後，將第一重佈層接點墊305直接形成於暴露通孔111上方且與暴露通孔111實體連接。一旦已形成第一重佈層接點墊305，便形成第一重佈層鈍化層303以保護第一重佈層接點墊305且可透過第一重佈層鈍化層303將第三外部連接器307放置至第一重佈層接點墊305上。接著可將基板421接合至第三外部連接器307，藉此避免使用第二重佈層301。 藉由將第三外部連接器307直接接合至通孔111，在其中第二重佈層301係非所要之情境中可避免形成第二重佈層301之額外製程步驟及複雜性。藉由減少製程步驟及簡化裝置之製造，可更有效地且以更小缺陷機會製造裝置。 圖6繪示類似於上文參考圖5所述之實施例且其中放置一第一底膠材料601以便保護第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)的一實施例。在一實施例中，第一底膠材料601係用來緩衝及支撐第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)以免受操作及環境劣化(諸如由操作期間之熱產生引起之應力)影響之一保護性材料。第一底膠材料601可包括例如液態環氧樹脂或其他保護性材料，且接著經固化以硬化。在一實施例中，可在已放置第四半導體裝置107及第五半導體裝置109之後且在囊封之前藉由以下步驟放置第一底膠材料601：使用例如一注射製程施配第一底膠材料601，藉此以液態形式注射第一底膠材料601使得其圍繞第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)流動。一旦已放置第一底膠材料601，可如上文所述般繼續剩餘製程步驟。 藉由施加第一底膠材料601，可更佳地保護第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)使之免受後續處理步驟影響。例如，第一底膠材料601可對第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)提供額外結構支撐以及額外隔離。此額外支撐及保護將減少或消除第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)之結構故障。 圖7繪示類似於上文參考圖1A至圖4所述之實施例之其中形成第二重佈層301以幫助互連通孔111的一實施例。然而，在此實施例中，在囊封第四半導體裝置107及第五半導體裝置109之前施配第一底膠材料601。在此實施例中，第一底膠材料601可如上文關於圖6所述般，諸如係使用一注射製程以液態形式施配之液態環氧樹脂或其他保護性材料。然而，可使用任何合適施配材料或方法。一旦已放置第一底膠材料601，可如上文所述般繼續剩餘製程步驟。 藉由施加第一底膠材料601，可更佳地保護第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)使之免受後續處理步驟影響。例如，第一底膠材料601可對第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)提供額外結構支撐以及額外隔離。此額外支撐及保護將減少或消除第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)之結構故障。 圖8繪示類似於上文關於圖4所論述之實施例之另一實施例。然而，在此實施例中，貫穿矽通孔(TSV) 801經形成貫穿第四半導體裝置107之第四基板及第五半導體裝置109之第五基板。首先查看第四半導體裝置107，在一實施例中，可藉由最初將貫穿矽通孔(TSV)開口形成至第四半導體裝置107之第四基板中而形成TSV 801。可藉由施加並顯影一合適光阻劑(未展示)以及移除第四半導體裝置107之第四基板中暴露於所要深度之部分而形成TSV開口。TSV開口可經形成以便延伸至第四半導體裝置107之第四基板中而至少遠於形成於第四半導體裝置107之第四基板內及/或上之第四主動裝置，且可延伸至大於第四半導體裝置107之第四基板之最終所要高度之一深度。據此，雖然該深度取決於總體設計，但該深度可在與第四半導體裝置107之第四基板上之第四主動裝置相隔約20 μm與約200 μm之間，諸如與第四半導體裝置107之第四基板上之第四主動裝置相隔約50 μm之一深度。 一旦已在第四半導體裝置107之第四基板內形成TSV開口，便可使用一襯層加襯裡於TSV開口。該襯層可係例如由四乙基正矽酸鹽(TEOS)或氮化矽形成之氧化物，但可替代地使用任何合適介電材料。可使用一電漿增強化學氣相沈積(PECVD)製程形成該襯層，但可替代地使用其他合適製程，諸如物理氣相沈積或一熱製程。另外，可將該襯層形成至約0.1 μm與約5 μm之間(諸如約1 μm)的一厚度。 一旦已沿TSV開口之側壁及底部形成襯層，便可形成一阻障層(亦未單獨繪示)且可運用一第一導電材料填充TSV開口之剩餘部分。該第一導電材料可包括銅，但可替代地利用其他合適材料，諸如鋁、合金、摻雜多晶矽、其等之組合及類似者。該第一導電材料可藉由以下步驟而形成：將銅電鍍至一第三晶種層(未展示)上；填充且過填充TSV開口。一旦已填充TSV開口，便可透過一平坦化製程(諸如化學機械拋光(CMP))移除TSV開口外部之過量襯層、阻障層、第三晶種層及第一導電材料，但可使用任何合適移除製程。 一旦已填充TSV開口，便可薄化第四半導體裝置107之第四基板之一背面以暴露TSV開口且形成TSV 801。在一實施例中，一旦已暴露TSV 801，便可使用例如一CMP及研磨製程以移除第四半導體裝置107之第四基板之材料而薄化第四半導體裝置107之第四基板，且平坦化第四半導體裝置107之第四基板及TSV 801。在另一實施例中，亦可使用一或多個蝕刻製程或其他移除製程來移除第四基板之材料且暴露TSV 801。 關於貫穿第五半導體裝置109之第五基板之TSV 801，可利用一類似製程來形成貫穿第五半導體裝置109之TSV 801。例如，可在第五基板內形成一開口，可使用導電材料加襯裡於且填充該開口，且可薄化第五基板以便暴露導電材料。然而，可利用任何合適製程以形成貫穿第四半導體裝置107及第五半導體裝置109之TSV 801。 一旦已在第四半導體裝置107及第五半導體裝置109中形成TSV 801 (且已執行任何其他所要處理，諸如主動裝置或金屬層之一形成)，便可放置第四半導體裝置107及第五半導體裝置109且運用通孔111囊封第四半導體裝置107及第五半導體裝置109，如上文關於圖2A至圖3所述。另外，可在第四半導體裝置107、第五半導體裝置109及第二囊封劑419上方形成第二重佈層301。然而，在此實施例中，亦將電連接第二重佈層301與貫穿第四半導體裝置107及第五半導體裝置109之TSV 801，而非對通孔111重新佈線。因而，亦可使用第二重佈層301以使第四半導體裝置107、第五半導體裝置109及通孔111互連。 藉由形成貫穿第四半導體裝置107及第五半導體裝置109之TSV 801，可提供額外佈線選項。另外，可將第四半導體裝置107及第五半導體裝置109連接至第二重佈層301。運用此等選項，可設計並達成一更有效佈局及連接圖案，且可獲得一總體更有效裝置。 圖9繪示其中形成貫穿第四半導體裝置107及第五半導體裝置109之TSV 801且將第二重佈層301電連接至TSV 801之另一實施例。在此實施例中，除TSV 801以外，亦放置第一底膠材料601以便幫助保護及支撐第四半導體裝置107及第五半導體裝置109。在此實施例中，第一底膠材料601可如上文關於圖6所述般，諸如係使用一注射製程以液態形式施配之液態環氧樹脂或其他保護性材料。然而，可使用任何合適施配材料或方法。 藉由施加第一底膠材料601，可更佳地保護第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)使之免受後續處理步驟影響。例如，第一底膠材料601可對第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)提供額外結構支撐以及額外隔離。此額外支撐及保護將減少或消除第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)之結構故障。 圖10繪示其中形成貫穿第四半導體裝置107及第五半導體裝置109之TSV 801之另一實施例。在此實施例中，除形成TSV 801以外(如上文關於圖8所述)，未形成第二重佈層301，且使第三外部連接器307與通孔111 (貫穿例如第一重佈層接點墊305)以及TSV 801直接接合。例如，可將第一重佈層接點墊305形成為與TSV 801電連接及/或實體連接，且將第三外部連接器307直接放置於第一重佈層接點墊305上方並與第一重佈層接點墊305電連接。 藉由將第三外部連接器307直接接合至通孔111及(亦) TSV 801，在其中第二重佈層301係非所要之情境中可避免形成第二重佈層301之額外製程步驟及複雜性。藉由減少製程步驟及簡化裝置之製造，可更有效地且以更小缺陷機會製造裝置。 圖11繪示類似於圖10中之實施例之其中形成貫穿第四半導體裝置107及第五半導體裝置109之TSV 801且將第三外部連接器307直接接合至通孔111及TSV 801的另一實施例。然而，在此實施例中，亦在囊封第四半導體裝置107及第五半導體裝置109之前施配第一底膠材料601。在此實施例中，第一底膠材料601可如上文關於圖6所述般，諸如係使用一注射製程以液態形式施配之液態環氧樹脂或其他保護性材料。然而，可使用任何合適施配材料或方法。一旦已放置第一底膠材料601，可如上文所述般繼續剩餘製程步驟。 藉由施加第一底膠材料601，可更佳地保護第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)使之免受後續處理步驟影響。例如，第一底膠材料601可在所選取方向上對第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)提供額外結構支撐以及額外隔離。此額外支撐及保護將減少或消除第一外部連接器110 (在第四半導體裝置107上)及第二外部連接器113 (在第五半導體裝置109上)之結構故障。 圖12繪示其中第一半導體裝置401、第二半導體裝置403或第三半導體裝置405或其等之所有三者係包括複數個個別晶粒之晶粒堆疊的又另一實施例。在一實施例中，可由一第一晶粒堆疊1201取代第一半導體裝置401，該第一晶粒堆疊1201可包括透過使用第三TSV 1209彼此互連之一第一晶粒1203、一第二晶粒1205及一第三晶粒1207。在一特定實施例中，第一晶粒1203、第二晶粒1205及第三晶粒1207之各者可係例如記憶體晶粒(諸如DRAM晶粒或高頻寬記憶體晶粒)，但第一晶粒1203、第二晶粒1205及第三晶粒1207可提供任何所要功能性。可使用類似於上文關於第一半導體裝置401所述之結構及方法形成第一晶粒1203、第二晶粒1205及第三晶粒1207之各者，且一旦形成，便可在放置及囊封之前使第一晶粒1203、第二晶粒1205及第三晶粒1207彼此接合。 類似地，可由一第二晶粒堆疊1211取代第二半導體裝置403，且可由一第三晶粒堆疊1213取代第三半導體裝置405。可利用晶粒堆疊及其他半導體裝置之任何合適組合，且所有此等組合完全旨在包含於本發明實施例之範疇內。 圖13A至圖13B繪示其中形成第一重佈層309且在放置及囊封第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之前放置第四半導體裝置107以及第五半導體裝置109的另一實施例。在一實施例中，一聚合物層105形成於黏著層103上且可係聚苯并唑(PBO)，但可替代地利用任何合適材料，諸如聚醯亞胺或聚醯亞胺衍生物。可使用例如一旋塗製程放置聚合物層105至約0.5 µm與約10 µm之間(諸如約5 µm)的一厚度，但可替代地使用任何合適方法及厚度。 一旦已形成聚合物層105，便可在聚合物層105上形成第一重佈層309。在一實施例中，可如上文關於圖1所述般形成第一重佈層309。例如，可使用沈積以及光微影遮罩及蝕刻製程形成複數個導電層及介電層。然而，可利用用於形成第一重佈層309之任何合適製程。 一旦已在第一載體基板101上方形成第一重佈層309，便可形成通孔111，且在已形成通孔111之後將第四半導體裝置107及第五半導體裝置109放置於通孔111內，如上文參考圖2A所述。另外，在此實施例中，亦可將一第六半導體裝置1301連同第四半導體裝置107及第五半導體裝置109一起放置於第一重佈層309上。在一實施例中，第六半導體裝置1301可係另一電壓調節器且可包括一第六基板、第六主動裝置、第六金屬層、第三接點墊、一第六鈍化層(圖13A中未單獨繪示)及第三外部連接器1303。在一實施例中，第六基板、第六主動裝置、第六金屬層、第三接點墊、第六鈍化層及第三外部連接器1303可類似於第四基板、第四主動裝置、第四金屬層、第一接點墊、第四鈍化層及第一外部連接器110，但其等亦可不同。 圖13A額外繪示第四半導體裝置107、第五半導體裝置109及第六半導體裝置1301之一囊封以及第二重佈層301、第一重佈層接點墊305、第一重佈層鈍化層303及第三外部連接器307之形成。在一實施例中，可囊封第四半導體裝置107、第五半導體裝置109及第六半導體裝置1301以及通孔111，且可形成第二重佈層301、第一重佈層接點墊305及第三外部連接器307，如上文關於圖3所述。然而，可利用(若干)任何合適製程。 圖13B繪示一旦已形成第三外部連接器307，便可移除第一載體基板101。在一實施例中，可如上文關於圖3所述般移除第一載體基板101。例如，可處理黏著層以降低其黏著性，且接著可移除第一載體基板101及黏著層103。另外，在此階段，若需要，亦可使用例如一濕式蝕刻製程移除聚合物層105。 一旦已移除第一載體基板101，便可放置第一半導體裝置401、第二半導體裝置403及第三半導體裝置405且使其等連接至第一重佈層309。在一實施例中，在連接第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之前，可將第四外部連接器1305放置於第一半導體裝置401上，可將第五外部連接器1307放置於第二半導體裝置403上，且可將第六外部連接器1309放置於第三半導體裝置405上。在一實施例中，第四外部連接器1305、第五外部連接器1307及第六外部連接器1309可係包括一共晶材料(諸如銲料)之微凸塊，但可替代地使用任何合適材料。在其中第四外部連接器1305、第五外部連接器1307及第六外部連接器1309係微凸塊之一實施例中，可使用一植球方法(諸如一直接植球製程)形成第四外部連接器1305、第五外部連接器1307及第六外部連接器1309。在另一實施例中，可藉由以下步驟形成微凸塊：最初透過任何合適方法(諸如蒸鍍、電鍍、印刷、銲料轉移)形成一錫層；及接著執行一回銲以便使材料塑形為所要凸塊形狀。在其中第四外部連接器1305、第五外部連接器1307及第六外部連接器1309係微凸塊之一實施例中，第一外部連接器110可具有約20 μm與約50 μm之間的一直徑。 一旦已將第四外部連接器1305、第五外部連接器1307及第六外部連接器1309放置或形成於第一半導體裝置401、第二半導體裝置403及第三半導體裝置405上，便可將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405對準並接合至第一重佈層309。在其中第四外部連接器1305、第五外部連接器1307及第六外部連接器1309係微凸塊之一實施例中，可藉由以下步驟來接合第一半導體裝置401、第二半導體裝置403及第三半導體裝置405：將第四外部連接器1305、第五外部連接器1307及第六外部連接器1309對準於第一重佈層309之所要暴露部分上；及接著執行一回銲以將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405接合至第一重佈層309。 替代地，可使用一熔合接合製程或一混合接合製程，將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405接合至第一重佈層309。在此等製程中，未利用第四外部連接器1305、第五外部連接器1307及第六外部連接器1309，且將第一鈍化層407、第二鈍化層411及第三鈍化層415直接接合至第一重佈層309之介電部分(在一熔合接合製程中)，或以其他方式，在一混合熔合接合製程中，將第一通孔409、第二通孔413及第三通孔417(除第一鈍化層407、第二鈍化層411及第三鈍化層415以外)直接接合至第一重佈層309。然而，可利用任何合適製程，以將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405接合至第一重佈層309。 一旦已將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405接合至第一重佈層309，便可將第三外部連接器307接合至基板421。在一實施例中，如上文關於圖4所述般，將第三外部連接器307接合至基板421。然而，可利用任何合適方法。 圖14繪示第一重佈層309與第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之各者之間之一第二底膠材料1401之一放置。在一實施例中，第二底膠材料1401可係類似於第一底膠材料601之一材料，且使用類似於第一底膠材料601之一製程加以施配(上文關於圖6所述)。例如，第二底膠材料1401可係透過一注射製程施配之一環氧樹脂材料。然而，可利用任何合適之施配材料或方法。 另外，在圖14中所繪示之實施例中，於已施配第二底膠材料1401之後，未囊封第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。而是，使第一半導體裝置401、第二半導體裝置403及第三半導體裝置405保持未囊封，其中第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之側壁無囊封材料。 圖15繪示其中運用第一囊封劑201來囊封第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之另一實施例。在一實施例中，如上文關於圖1中第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之囊封所述般，囊封第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。例如，可將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405 (連同第四半導體裝置107、第五半導體裝置109及第六半導體裝置1301一起)放置至一模穴(未單獨繪示)中，且可將第一囊封劑201放置於第一半導體裝置401、第二半導體裝置403及第三半導體裝置405上方。一旦處於適當位置中，若需要，則可使用(例如)一CMP製程來平坦化第一囊封劑201、第一半導體裝置401、第二半導體裝置403及第三半導體裝置405直至暴露第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。然而，可使用任何合適製程來囊封第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。 圖16繪示其中未利用第一囊封劑201來囊封第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之另一實施例。在此實施例中，可將一散熱片1601放置於第一半導體裝置401、第二半導體裝置403及第三半導體裝置405上方，以幫助保護第一半導體裝置401、第二半導體裝置403及第三半導體裝置405，並且移除在第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之操作期間產生的熱。在一實施例中，可使用(例如)一第一熱介面材料1603將散熱片1601附接至第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。第一熱介面材料1603包括環氧樹脂、聚矽氧、無機材料(諸如輕度交聯聚矽氧聚合物、一或多種基質聚合物、具有一或多個導熱填充劑、其他材料或多個層之一聚合物)或其等之組合(在一些實施例中，作為實例)。在其中第一熱介面材料1603包括基質聚合物之實施例中，該基質聚合物可包括乙烯-丙烯、乙烯-丙烯-二烯單體、氫化聚異戊二烯或其等之一組合。在其中第一熱介面材料1603包括一導熱填充劑之實施例中，該導熱填充劑可包含氧化鋁、氮化硼、氮化鋁、鋁、銅、銀、銦或其等之一組合。該導熱填充劑係施配於第一熱介面材料1603內，且在第一熱介面材料1603內具有約10重量百分比至約90重量百分比(例如，在一些實施例中)之一百分比重量。替代地，第一熱介面材料1603可包括其他材料、填充劑及性質。使用第一熱介面材料1603，以藉由填入在微小不均勻表面內所產生的顯微氣囊(諸如第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之表面與散熱片1601之表面之間的區)來改良電傳導及/或熱傳導。 在一些實施例中，可將第一半導體裝置401、第二半導體裝置403及第三半導體裝置405電連接且熱連接至散熱片1601且最終至一散熱器(圖16中未單獨繪示)。對於此一實例，可使用含有懸浮於聚矽氧油脂中之銀、鎳或鋁顆粒之一金屬基導熱膏。在其中第一半導體裝置401、第二半導體裝置403及第三半導體裝置405可僅想要至該散熱器之熱傳導之替代實施例中，可施加填充有陶瓷粉末之非導電陶瓷基膏，諸如氧化鈹、氮化鋁、氧化鋁或氧化鋅。此外，一些實施例可不利用第一導熱膏。 在一些實施例中，尤其對於高功率應用，可部署散熱片1601以對第一半導體裝置401、第二半導體裝置403及第三半導體裝置405供應電路徑及/或熱路徑以將從第一半導體裝置401、第二半導體裝置403及第三半導體裝置405產生之熱散佈於一較大區上方。在一實施例中，散熱片1601可包括銅、鋁、其他金屬、合金、其等之組合或具有高導電性及導熱性之其他材料。另外，該散熱片可從第一半導體裝置401、第二半導體裝置403及第三半導體裝置405附接至基板421之頂部表面以建立至基板421之電連接。 一散熱器可安裝於散熱片以及第一半導體裝置401、第二半導體裝置403及第三半導體裝置405上方且熱耦合至散熱片以及第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。可使用展現高導熱性之材料形成散熱器，諸如鋁、銅、鑽石、其他金屬、合金、其等之組合及類似者。該散熱器藉由增大暴露於環繞其之一冷卻劑(諸如空氣)之一給定表面積而協助冷卻第一半導體裝置401、第二半導體裝置403及第三半導體裝置405。熱轉移機制透過周圍空氣之對流、透過空氣傳導及輻射而發生。例如，與第一半導體裝置401、第二半導體裝置403及第三半導體裝置405之表面積相比，藉由採用以一幾何形鰭片矩陣或一筆直或喇叭形鰭片陣列之形式之大量鰭片，散熱器可展現一更大對流表面積。在諸如其中對流為低之另一實施例中，在可見光譜中，一磨砂黑表面色彩可比閃亮金屬色彩更有效地輻射。可替代地利用散熱器之任何合適形式。 根據一實施例，提供一種包括一第一半導體裝置之半導體裝置，其中該第一半導體裝置包括一第一電壓調節器。一囊封劑囊封該第一半導體裝置且一貫穿通孔與該第一半導體裝置分離且從該囊封劑之一第一側延伸至該囊封劑之一第二側。一第一重佈層在該囊封劑之一第一側上電連接至該貫穿通孔，且一第二半導體裝置透過該第一重佈層電連接至該第一半導體裝置，其中該第二半導體裝置包括一第一邏輯裝置。 根據另一實施例，提供一種包括一囊封劑之半導體裝置，該囊封劑具有一第一側及與該第一側相對之一第二側。一貫穿通孔從該第一側延伸至該第二側且一第一電壓調節器晶粒從該第一側延伸至該第二側。一第一重佈層電連接至該貫穿通孔及該第一電壓調節器晶粒，且一第一邏輯晶粒透過該第一重佈層電連接至該第一電壓調節器晶粒。 根據又另一實施例，提供一種製造一半導體裝置之方法，其包括運用一第一囊封劑囊封一通孔及一第一電壓調節器晶粒，其中該第一囊封劑與該通孔實體接觸。在該第一囊封劑之一第一側上形成一第一重佈層，該第一重佈層與該通孔電連接，且將一第一邏輯晶粒接合至該第一重佈層，該第一邏輯晶粒與該第一電壓調節器晶粒電連接。 根據又另一實施例，提供一種製造一半導體裝置之方法，其包括在一第一半導體晶粒上方形成一第一重佈層，其中該第一半導體晶粒係一邏輯晶粒。在該第一重佈層相對該第一半導體晶粒之一側上形成通孔，且將一第一整合式電壓調節器放置成鄰近於該等通孔。囊封該第一整合式電壓調節器及該等通孔。 前文概述若干實施例之特徵使得熟習此項技術者可更佳地理解本揭露之態樣。熟習此項技術者應明白，其等可容易將本揭露用作用於設計或修改其他製程及結構的一基礎以實行相同目的及/或達成本文中所介紹之實施例之相同優點。熟習此項技術者亦應認知，此等等效構造不背離本揭露之精神及範疇，且其等可在不背離本揭露之精神及範疇之情況下在本文中作出各種改變、置換及更改。
101‧‧‧第一載體基板 103‧‧‧黏著層 105‧‧‧聚合物層 107‧‧‧第四半導體裝置 109‧‧‧第五半導體裝置 110‧‧‧第一外部連接器 111‧‧‧通孔 113‧‧‧第二外部連接器 201‧‧‧第一囊封劑 301‧‧‧第二重佈層 303‧‧‧第一重佈層鈍化層 305‧‧‧第一重佈層接點墊 307‧‧‧第三外部連接器 309‧‧‧第一重佈層 401‧‧‧第一半導體裝置 403‧‧‧第二半導體裝置 405‧‧‧第三半導體裝置 407‧‧‧第一鈍化層 409‧‧‧第一通孔 411‧‧‧第二鈍化層 413‧‧‧第二通孔 415‧‧‧第三鈍化層 417‧‧‧第三通孔 419‧‧‧第二囊封劑 421‧‧‧基板 423‧‧‧第四外部連接件 601‧‧‧第一底膠材料 801‧‧‧貫穿矽通孔(TSV) 1201‧‧‧第一晶粒堆疊 1203‧‧‧第一晶粒 1205‧‧‧第二晶粒 1207‧‧‧第三晶粒 1209‧‧‧第三貫穿矽通孔(TSV) 1211‧‧‧第二晶粒堆疊 1213‧‧‧第三晶粒堆疊 1301‧‧‧第六半導體裝置 1303‧‧‧第三外部連接器 1305‧‧‧第四外部連接器 1307‧‧‧第五外部連接器 1309‧‧‧第六外部連接器 1401‧‧‧第二底膠材料 1601‧‧‧散熱片 1603‧‧‧第一熱介面材料
在結合附圖閱讀時，從下文詳細描述最佳地理解本揭露之態樣。應注意，根據標準工業實踐，各個構件未按比例繪製。事實上，為了清晰論述起見，可任意地增大或減小各個構件之尺寸。 圖1至圖4繪示根據一些實施例之具有多個重佈層之積體半導體裝置。 圖5繪示根據一些實施例之具有一單一重佈層之積體半導體裝置。 圖6繪示根據一些實施例之具有一單一重佈層及一底膠材料之積體半導體裝置。 圖7繪示根據一些實施例之具有多個重佈層及一底膠材料之積體半導體裝置。 圖8繪示根據一些實施例之具有多個重佈層及延伸貫穿該多個重佈層之貫穿矽通孔的積體半導體裝置。 圖9繪示根據一些實施例之具有多個重佈層及延伸貫穿該多個重佈層之貫穿矽通孔以及一底膠材料的積體半導體裝置。 圖10繪示根據一些實施例之具有一單一重佈層以及延伸貫穿該多個重佈層之貫穿矽通孔的積體半導體裝置。 圖11繪示根據一些實施例之具有一單一重佈層以及延伸貫穿該多個重佈層之貫穿矽通孔及一底膠材料的積體半導體裝置。 圖12繪示根據一些實施例之具有晶粒堆疊之積體半導體裝置。 圖13A至圖13B繪示其中最後附接第一半導體裝置、第二半導體裝置及第三半導體裝置之一實施例。 圖14繪示根據一些實施例之一底膠材料之一放置。 圖15繪示根據一些實施例之第一半導體裝置、第二半導體裝置及第三半導體裝置之一囊封。 圖16繪示根據一些實施例之一散熱片之一放置。
107‧‧‧第四半導體裝置
109‧‧‧第五半導體裝置
110‧‧‧第一外部連接器
111‧‧‧通孔
113‧‧‧第二外部連接器
301‧‧‧第二重佈層
303‧‧‧第一重佈層鈍化層
305‧‧‧第一重佈層接點墊
307‧‧‧第三外部連接器
309‧‧‧第一重佈層
401‧‧‧第一半導體裝置
403‧‧‧第二半導體裝置
405‧‧‧第三半導體裝置
409‧‧‧第一通孔
413‧‧‧第二通孔
417‧‧‧第三通孔
419‧‧‧第二囊封劑
421‧‧‧基板
423‧‧‧第四外部連接件
1301‧‧‧第六半導體裝置
1303‧‧‧第三外部連接器
1601‧‧‧散熱片
1603‧‧‧第一熱介面材料

Claims (10)

  1. 一種半導體裝置，其包括： 一第一半導體裝置，其中該第一半導體裝置包括一第一電壓調節器； 一囊封劑，其囊封該第一半導體裝置； 一貫穿通孔，其與該第一半導體裝置分離，且從該囊封劑之一第一側延伸至該囊封劑之一第二側； 一第一重佈層，其在該囊封劑之一第一側上電連接至該貫穿通孔；及 一第二半導體裝置，其係透過該第一重佈層電連接至該第一半導體裝置，其中該第二半導體裝置包括一第一邏輯裝置。
  2. 如請求項1之半導體裝置，進一步包括一第三半導體裝置，其中該囊封劑囊封該第三半導體裝置，且其中該第三半導體裝置包括一第二電壓調節器。
  3. 如請求項2之半導體裝置，進一步包括一第四半導體裝置，該第四半導體裝置電連接至該第一重佈層，且位於該第一重佈層相對該第三半導體裝置之一側上，該第四半導體裝置包括一第二邏輯裝置。
  4. 如請求項3之半導體裝置，進一步包括： 一第五半導體裝置，其電連接至該第一重佈層，且位於該第一重佈層相對該第三半導體裝置之一側上，該第五半導體裝置包括一輸出入裝置；及 一第二囊封劑，其囊封該第二半導體裝置、該第四半導體裝置及該第五半導體裝置。
  5. 如請求項1之半導體裝置，其中該第一半導體裝置包括一貫穿矽通孔。
  6. 如請求項1之半導體裝置，其中該第一半導體裝置之側壁無囊封劑。
  7. 一種半導體裝置，其包括： 一囊封劑，其具有一第一側及與該第一側相對之一第二側； 一貫穿通孔，其從該第一側延伸至該第二側； 一第一電壓調節器晶粒，其從該第一側延伸至該第二側； 一第一重佈層，其電連接至該貫穿通孔及該第一電壓調節器晶粒；及 一第一邏輯晶粒，其係透過該第一重佈層電連接至該第一電壓調節器晶粒。
  8. 如請求項7之半導體裝置，進一步包括位於該第一電壓調節器晶粒相對該第一邏輯晶粒之一側上之一第二重佈層。
  9. 一種製造一半導體裝置之方法，該方法包括： 運用一第一囊封劑來囊封一通孔及一第一電壓調節器晶粒，其中該第一囊封劑與該通孔實體接觸； 在該第一囊封劑之一第一側上形成一第一重佈層，該第一重佈層與該通孔電連接；及 將一第一邏輯晶粒接合至該第一重佈層，該第一邏輯晶粒與該第一電壓調節器晶粒電連接。
  10. 一種製造一半導體裝置之方法，該方法包括： 在一第一半導體晶粒上方形成一第一重佈層，其中該第一半導體晶粒係一邏輯晶粒； 在該第一重佈層相對該第一半導體晶粒之一側上形成通孔； 將一第一整合式電壓調節器放置成鄰近於該等通孔；及 囊封該第一整合式電壓調節器及該等通孔。
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US20170170155A1 (en) 2017-06-15
KR101931416B1 (ko) 2018-12-20
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