CN110998836A - 使用具有双侧互连层的管芯的单片芯片堆叠 - Google Patents

使用具有双侧互连层的管芯的单片芯片堆叠 Download PDF

Info

Publication number
CN110998836A
CN110998836A CN201780094256.5A CN201780094256A CN110998836A CN 110998836 A CN110998836 A CN 110998836A CN 201780094256 A CN201780094256 A CN 201780094256A CN 110998836 A CN110998836 A CN 110998836A
Authority
CN
China
Prior art keywords
layer
die
interconnect
coupled
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201780094256.5A
Other languages
English (en)
Inventor
A.潘乔利
全箕玟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN202311535358.XA priority Critical patent/CN117995801A/zh
Publication of CN110998836A publication Critical patent/CN110998836A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2105—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92132—Sequential connecting processes the first connecting process involving a build-up interconnect
    • H01L2224/92133—Sequential connecting processes the first connecting process involving a build-up interconnect the second connecting process involving a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供了一种设备，所述设备包括：具有第一表面和第二表面的第一管芯，第一管芯包括：在第一管芯的第一表面上形成的第一层，以及在第一管芯的第二表面上形成的第二层；耦合到第一层的第二管芯；以及用来将设备耦合到外部组件的多个结构，其中多个结构耦合到第二层。

Description

使用具有双侧互连层的管芯的单片芯片堆叠
背景技术
一般地，当要堆叠两个或多于两个半导体管芯时，可使用附加互连管芯（诸如中介层、桥接管芯）、使用穿硅通孔（TSV）结构等来实现管芯到管芯互连。然而，添加此类附加管芯到管芯互连元件可导致成本和复杂性的增加，并且还可增加管芯到管芯互连长度。
附图说明
从下面给出的详细描述和从本公开的各种实施例的附图中，将更全面地理解本公开的实施例，然而，这不应被认为是将本公开限制于特定实施例，而是仅用于解释和理解。
图1示意性地示出根据一些实施例的半导体封装，所述半导体封装包括具有在两个相对侧上形成的互连层的第一管芯以及耦合到第一管芯的第二管芯。
图2A-2K示出根据一些实施例的形成半导体封装的工艺，其中所述半导体封装包括具有在两个相对侧上形成的互连层的第一管芯以及耦合到第一管芯的第二管芯。
图3A示意性地示出根据一些实施例的半导体封装，所述半导体封装包括具有在两个相对侧上形成的互连层的第一管芯以及耦合到第一管芯的第二管芯，而在第一管芯和第二管芯之间没有任何中间重分布层（RDL）。
图3B示意性地示出根据一些实施例的包括多个堆叠管芯的半导体封装，其中至少两个管芯中的每个管芯具有在两个相对侧上形成的互连层。
图4示出根据一些实施例的计算机系统、计算装置或SoC（片上系统），其中使用包括两个或多于两个堆叠管芯的半导体封装来形成计算系统的一个或多个组件，其中堆叠管芯中的至少一个具有在两个相对表面上形成的互连层。
具体实施方式
在一些实施例中，半导体封装可以包括多个堆叠管芯。所述堆叠管芯可以包括第一管芯，所述第一管芯具有在第一管芯的两个相对表面上形成的互连层。例如，第一管芯的第一表面上的第一互连层可以耦合到第二管芯；并且第一管芯的第二表面上的第二互连层可以耦合到封装互连结构（例如，以用于将设备耦合到外部组件）。
在一些实施例中，具有在两个相对表面上形成的互连层的第一管芯可以不具有用于连接互连层的任何TSV。例如，两个互连层可以连接到第一管芯的有源组件。相应地，第一管芯的厚度可以相对较小，并且这可以导致相对薄的管芯到管芯互连。从各种实施例和附图中，其它技术效果将是显然的。
在以下描述中，讨论了许多细节以提供对本公开的实施例的更透彻的解释。然而，对于本领域技术人员将显而易见的是，可以在没有这些特定细节的情况下实践本公开的实施例。在其它实例中，以框图形式示出而不是详细地示出公知的结构和装置，以便免于使本公开的实施例模糊。
注意到，在实施例的对应附图中，用线表示信号。一些线可以较粗以指示更多的组成信号路径，和/或在一个或多个端具有箭头以指示主要信息流方向。此类指示不意图是限制性的。相反，结合一个或多个示例性实施例使用这些线，以促进更容易理解电路或逻辑单元。如通过设计需要或偏好所指明的，任何表示的信号实际上可以包括可以在任一方向上行进并且可以用任何适合类型的信号方案实现的一个或多个信号。
在说明书通篇以及在权利要求书中，术语“连接”意味着在连接的事物之间的直接连接（诸如电、机械或磁连接）而没有任何中间装置。术语“耦合”意味着直接或间接连接，诸如连接的事物之间的直接电、机械或磁连接或者经过一个或多个无源或有源中间装置的间接连接。术语“电路”或“模块”可以指布置成与彼此协作以提供期望功能的一个或多个无源和/或有源组件。术语“信号”可以指至少一个电流信号、电压信号、磁信号或数据/时钟信号。“一（a、an）”和“该（the）”的含义包括复数引用。“在…中”的含义包括“在…中”和“在…上”。术语“基本上”、“接近”、“近似地”、“靠近”和“大约”一般指在目标值的+/﹣10%内。
除非以其它方式指定，否则使用序数形容词“第一”、“第二”和“第三”等来描述共同对象仅指示正在参考相似对象的不同实例，并且不意图暗示那样描述的对象必须在时间上、在空间上、在排序中或以任何其它方式处于给定序列中。
为了本公开的目的，短语“A和/或B”以及“A或B”意味着（A）、（B）或（A和B）。为了本公开的目的，短语“A、B和/或C”意味着（A）、（B）、（C）、（A和B）、（A和C）、（B和C）或（A、B和C）。在说明书和权利要求书中的术语“左”、“右”、“前”、“后”、“顶部”、“底部”、“上方”、“下方”等等，如果有的话，用于描述性目的，并且不一定用于描述固定的相对位置。
图1示意性地示出根据一些实施例的半导体封装100（后文也称为“封装100”），所述半导体封装100包括具有在两个相对侧上形成的互连层的第一管芯102以及耦合到第一管芯的第二管芯105。在一些实施例中，管芯102、105可以是用来实现任何适当类型的功能性的任何适当类型的管芯，例如存储器管芯、处理器管芯、图形管芯等等。
在一些实施例中，管芯102可以包括在管芯102的两个相对侧或表面上形成的互连层106和107，其中使用粗线象征性地示出互连层106和107。例如，互连层106和107中的每个互连层可以耦合到管芯102的各种对应的内部组件（例如，有源组件、晶体管等）。
在一些实施例中，互连层106和107可以包括迹线、重分布层（RDL）、布线结构、布线层、互连结构（例如，凸块、凸块焊盘、金属柱、使用金属、合金、可焊接材料形成的球、使用金属、合金、可焊接材料形成的焊料等等）和/或管芯102的相应表面上的其它互连组件。在一些实施例中，可以使用密封剂或模塑料114来密封（encapsulate）管芯102。
在一些实施例中，RDL层108可以附连或耦合到互连层107，其中RDL层108可以嵌入在密封剂或模塑料126内。在一些实施例中，RDL层108可重分布互连层107的连接。
管芯105可以经由互连结构110附连到或耦合到RDL层108。互连结构110可以包括例如凸块、凸块焊盘、金属柱（例如，铜柱）、使用金属、合金、可焊接材料形成的球、使用金属、合金、可焊接材料形成的焊料等等。在一些实施例中，可以使用密封剂或模塑料124来密封管芯105。
在一些实施例中，RDL层112可以附连到互连层106，其中RDL层112可以嵌入在密封剂或模塑料116内。在一些实施例中，RDL层112可以重分布互连层106的连接。在一些实施例中，RDL层112可以附连到或者耦合到封装互连结构120。互连结构120可以包括例如凸块、凸块焊盘、金属柱（例如，铜柱）、使用金属、合金、可焊接材料形成的球、使用金属、合金、可焊接材料形成的焊料等等。在一些实施例中，封装100可以使用互连结构120附连到外部组件（例如，图1中未示出的衬底、主板等）。
因此，在封装100中，管芯102可以使用在管芯102的第一侧上形成的互连层107耦合到管芯105。此外，管芯102可以使用在管芯102的第二侧上形成的互连层106耦合到封装互连结构120（例如，以用于附连到外部组件）。因此，管芯102可堆叠在管芯105上，而没有任何中间管芯结构，诸如中介层、桥接管芯等。在一些实施例中，互连层106和107可以不通过通孔或TSV连接到彼此。这可以导致管芯102和105之间的管芯到管芯互连长度的减少。
图2A-2K示出根据一些实施例的形成半导体封装（例如，图1的封装100）的工艺，其中所述半导体封装包括具有在两个相对侧上形成的互连层的第一管芯以及耦合到第一管芯的第二管芯。参考图2A，示出了包括临时衬底或晶圆（例如载体202）和附连到载体202的粘合层204的组件200a。参考图2B，示出了从组件200a形成的组件200b，其中组件200b可包括在临时载体202上形成的RDL层112a、112b、112c。在一些实施例中，RDL层112a、112b、112c可以嵌入在密封剂或模塑料116内。RDL层112a、112b、112c可以对应于图1的RDL层112。
要注意，图2A-2K示出了三个示例封装的形成，所述三个示例封装中的每个示例封装可以类似于图1的封装100。在一些示例中，可以形成多于三个封装。为了便于讨论，本文中详细讨论图2A-2L的三个封装中的一个或一些封装的形成。例如，参考图2B，三个封装可以分别被形成在RDL层112a、112b和112c上方，然而，可以为了便于讨论而详细讨论在RDL层112中的一个RDL层（例如RDL层112b）上形成的封装（并且相同的讨论可以适用于在两侧上形成的其它两个封装）。
本文中用后面跟着特定数字或字母的共同附图标记来指代的元件可以仅通过参考标记来被共同地指代。例如，可以将RDL 112a、112b和112c共同地并且一般地称为复数的RDL 112和单数的RDL 112。类似地，可以将管芯104a、104b和104c（例如，本文中稍后讨论的）共同地并且一般地称为复数的管芯104和单数的管芯104。
现在参考图2C，管芯104a、104b和104c被放置在载体202上方，例如分别放置在RDL层112a、112b和112c上方，以形成组件200c。作为示例，管芯104b可以包括区段（section）102b，所述区段102b可以包括诸如晶体管的有源组件。互连层106b和107b可以被形成在区段102b的两个相对侧上。例如，互连层106b可以附连或耦合到RDL层112b。管芯104b可以进一步包括区段103b，所述区段103b可以被形成在互连层107b上。在一些实施例中，区段103b可以不包括有源电路组件。例如，区段103b可以不包括任何晶体管。在示例中，区段103b可以被称为“体层”、“体区段”、“非有源层”、“支撑层”、“牺牲层”等等。在一些实施例中，区段103b可以包括体硅，而在一些其它实施例中，区段103b可以包括硅和/或异质集成，诸如III-V、III-N、蓝宝石、玻璃等等。
在一些实施例中，区段103b可以向区段102b和互连层107b提供机械强度和稳定性。在示例中，管芯104b在互连层106b和107b之间的区段可以被称为晶体管层（例如，因为此区段包括有源组件）。互连层107b可以在晶体管层和体层103b之间。
现在参考图2D，管芯104a、104b和104c被密封剂或模塑料114密封，以形成组件200d。现在参考图2E，可以选择性地或部分地去除（例如，使用研磨、化学机械平坦化或CMP、表面平坦（例如，通过刀片切割）、蚀刻等）模塑料114以形成组件200e。例如，可以在组件200e中去除模塑料114的顶部部分分别连同管芯104a、104b、104c的区段103a、103b、103c。在一些实施例中，由于关于图2E执行的去除工艺，互连层107a、107b、107c可以通过模塑料114而被暴露。在一些实施例中，可以使用例如机械研磨、抛光工艺（诸如化学机械平坦化（CMP））、蚀刻（例如干法蚀刻、湿法蚀刻等）、表面平坦（例如刀片切割）等等来执行组件200e中的去除。
现在参考图2F，在组件200f中，RDL层108a、108b和108c可以分别被形成在互连层107a、107b、107c上。在一些实施例中，RDL层108a、108b、108c可以嵌入在密封剂或模塑料126内。在示例中，RDL层108a、108b、108c可以对应于图1的RDL层108。
现在参考图2G，在组件200g中，管芯105a、105b和105c可以分别放置在组件200f的RDL层108a、108b和108c上。在示例中，管芯105a、105b、105c可以对应于图1的管芯105。
现在参考图2H，在组件200h中，在一些实施例中，可以使用密封剂或模塑料124来密封管芯105a、105b、105c。例如，模塑料124可以包覆管芯105a、105b、105c，使得这些管芯完全被模塑料124密封，并且不通过模塑料124而被暴露。
现在参考图2I，在组件200i中，在一些实施例中，可以翻转组件200h并且可以去除晶圆载体202。晶圆载体202的去除可以取决于临时载体中使用的粘合剂，并且可以使用一个或多个工艺，像紫外（UV）释放机制、热释放机制、机械释放机制、红外释放机制等等。
现在参考图2J，在组件200j中，在一些实施例中，互连结构120a、120b和120c可以分别附连到RDL层112a、112b和112c。在示例中，互连结构120a、120b、120c、120b可以对应于图1的组件100的互连结构120。
现在参考图2K，可以将组件200j单颗化（singulate）以形成三个半导体封装200k1、200k2及200k3。在示例中，其中封装200k1、200k2和200k3中的每个封装可以类似于图1的封装100。
因此，图1示出了管芯102，所述管芯102包括在管芯102的晶体管层的两侧上的互连层106和107，并且图2A-2K示出了用来形成此类管芯的示例工艺。在一些实施例中，通过互连106和107，管芯102可以从两侧附连到RDL、另一管芯、封装互连结构（例如，互连结构120）等。
在示例中，在管芯102中可以不存在通孔，例如像TSV的厚通孔。例如，可以不存在将互连层106和107互连的任何通孔（例如，TSV）。
在一些实施例中并且如关于图2A-2K所讨论的，例如在形成封装100时，可以不存在任何薄管芯处置。例如，管芯102可以是相对薄的。然而，如关于图2C所讨论的，管芯102可以被组装为相对厚的管芯104（例如，包括较薄的管芯102和支撑体层103）。组装厚管芯104（例如，而不是组装薄管芯103）并且稍后去除体层103可以例如使得能够消除最终管芯102中的支撑厚度。例如，互连层107可以最初被掩埋在管芯104内，并且可以在图2E中将体层103减薄并去除之后暴露互连层107。此类工艺可以使得能够在管芯102的两侧上形成互连层106和107，而没有对用来支撑或连接这两个层的任何TSV或管芯102的更高厚度的任何需要。
再次参考图1，此图示出了示例封装100。此封装100的变型可以是可能的。例如，可以去除管芯102与105之间的RDL层108，例如，如图3A中示出的。例如，图3A示意性地示出根据一些实施例的半导体封装300a（后文也称为“封装300a”），所述半导体封装300a包括具有在两个相对侧上形成的互连层的第一管芯102和耦合到第一管芯102的第二管芯105，而在第一管芯102和第二管芯105之间没有任何中间RDL层。封装300a至少部分地类似于图1的封装100。然而，不像封装100，在封装300中，在管芯102与105之间不存在中间RDL层（例如，封装100的RDL层108不被形成在封装300a中）。封装300a的形成和其它细节可以至少部分地从封装100的那些形成和其它细节而是明显的，并且因此，在本文中不进一步详细讨论封装300a。
在图1中，示出了在两侧上具有互连层的单个管芯102。然而，在一些实施例中，多个此类管芯可以被堆叠，例如，如在图3B中示出的。例如，图3B示意性地示出根据一些实施例的包括多个堆叠管芯的半导体封装300b（后文也称为“封装300b”），其中至少两个管芯中的每个管芯具有在两个相对侧上形成的互连层。封装300b至少部分地类似于图1的封装100。然而，不像封装100，在封装300b中，可以存在附加的管芯302。管芯302可以至少部分地类似于图1的管芯102。例如，管芯302可以具有在管芯302的两个相对表面上形成的互连层306和307。在一些实施例中，如图3B中示出的，可以堆叠管芯102、302和105。尽管在图3B中示出了在两侧上具有互连层的仅两个管芯（例如，管芯102和302），但是也可以堆叠多于两个此类管芯。封装300b的形成和其它细节可以至少部分地从封装100的那些形成和其它细节而是明显的，并且因此在本文中不进一步详细讨论封装300b。
封装100、300a、300b可以用在许多领域中。如所讨论的，在这些封装中，管芯（例如，管芯102、302）可以具有在两个相对侧上形成的互连层，而没有将两个相对侧互连的任何通孔或TSV。在一些实施例中，这可以导致例如与具有TSV的常规管芯的厚度相比管芯102、302的相对小的厚度，这可以导致更好的性能（例如，由于管芯到管芯互连长度和耦合电容的减少）。此外，关于图2A-2K讨论的管芯组装件可以允许不同技术、管芯和/或原始晶圆尺寸的集成。
在一些实施例中，管芯102、105和/或302可以用于各种目的，例如，作为微处理器、存储器管芯、图形管芯、微机电系统（MEMS）管芯、模拟和RF集成管芯等。
图4示出了根据一些实施例的计算机系统、计算装置或SoC（片上系统）2100，其中使用包括两个或多于两个堆叠管芯的半导体封装来形成计算系统2100的一个或多个组件，其中堆叠管芯中的至少一个具有在两个相对表面上形成的互连层。指出的是，具有与任何其它附图的元件相同的参考标号（或名称）的图4的那些元件能够以与所描述的方式类似的任何方式进行操作或起作用，但不限于此。
在一些实施例中，计算装置2100表示适当的计算装置，诸如计算平板电脑、移动电话或智能电话、膝上型电脑、桌面型电脑、IOT装置、服务器、机顶盒、无线使能的电子阅读器等等。将理解到，一般地示出了某些组件，并且在计算装置2100中并非示出此类装置的全部组件。
在一些实施例中，计算装置2100包括第一处理器2110。本公开的各种实施例还可以包括2170内的网络接口，诸如无线接口，使得系统实施例可以被合并在无线装置（例如蜂窝电话或个人数字助理）中。
在一个实施例中，处理器2110可包括一个或多个物理装置，诸如微处理器、应用处理器、微控制器、可编程逻辑装置或其它处理部件。由处理器2110执行的处理操作包括操作平台或操作系统的执行，在所述操作平台或操作系统上执行应用和/或装置功能。处理操作包括和与人类用户或与其它装置的I/O（输入/输出）相关的操作、与功率管理相关的操作和/或与将计算装置2100连接到另一装置相关的操作。处理操作还可以包括与音频I/O和/或显示I/O相关的操作。
在一个实施例中，计算装置2100包括音频子系统2120，所述音频子系统2120表示与向计算装置提供音频功能关联的硬件（例如，音频硬件和音频电路）和软件（例如，驱动程序、编解码器）组件。音频功能可包括扬声器和/或耳机输出以及麦克风输入。用于此类功能的装置可集成到计算装置2100中，或者连接到计算装置2100。在一个实施例中，用户通过提供由处理器2110接收和处理的音频命令来与计算装置2100交互。
显示子系统2130表示为用户提供视觉和/或触觉显示以与计算装置2100交互的硬件（例如，显示装置）和软件（例如，驱动程序）组件。显示子系统2130包括显示接口2132，所述显示接口2132包括用于向用户提供显示的特定屏幕或硬件装置。在一个实施例中，显示接口2132包括与处理器2110分离的逻辑以执行与显示相关的至少一些处理。在一个实施例中，显示子系统2130包括向用户提供输出和输入两者的触摸屏（或触摸板）装置。
I/O控制器2140表示和与用户交互相关的硬件装置和软件组件。I/O控制器2140可操作以管理作为音频子系统2120和/或显示子系统2130的一部分的硬件。此外，I/O控制器2140示出了用于连接到计算装置2100的附加装置的连接点，用户可能通过所述附加装置与系统交互。例如，可附连到计算装置2100的装置可能包括麦克风装置、扬声器或立体声系统、视频系统或其它显示装置、键盘或小键盘装置、或者供特定应用使用的其它I/O装置（诸如读卡器或其它装置）。
如上面提到的，I/O控制器2140可与音频子系统2120和/或显示子系统2130交互。例如，通过麦克风或其它音频装置的输入可提供用于计算装置2100的一个或多个应用或功能的输入或命令。此外，可提供音频输出来代替显示输出，或者除了显示输出之外还可提供音频输出。在另一示例中，如果显示子系统2130包括触摸屏，则显示装置还充当输入装置，其可至少部分地由I/O控制器2140管理。在计算装置2100上还可存在附加的按钮或开关以提供由I/O控制器2140管理的I/O功能。
在一个实施例中，I/O控制器2140管理诸如加速度计、相机、光传感器或其它环境传感器的装置，或者管理可包括在计算装置2100中的其它硬件。输入能够是直接用户交互的一部分，以及向系统提供环境输入以影响其操作（诸如针对噪声的过滤、针对亮度检测调整显示、针对相机应用闪光灯、或者其它特征）。
在一个实施例中，计算装置2100包括管理电池功率使用、电池的充电以及与功率节省操作相关的特征的功率管理2150。存储器子系统2160包括用于存储计算装置2100中的信息的存储器装置。存储器可包括非易失性（如果到存储器装置的功率中断，则状态不改变）和/或易失性（如果到存储器装置的功率中断，则状态是不确定的）存储器装置。存储器子系统2160可存储应用数据、用户数据、音乐、照片、文档或其它数据以及与计算装置2100的应用和功能的执行相关的系统数据（无论是长期的还是临时的）。在一个实施例中，计算装置2100包括用来生成时钟信号的时钟生成子系统2152。
实施例的元件还被提供作为用于存储计算机可执行指令（例如，用来实现本文中所讨论的任何其它过程的指令）的机器可读介质（例如，存储器2160）。机器可读介质（例如，存储器2160）可包括但不限于闪存、光盘、CD-ROM、DVD ROM、RAM、EPROM、EEPROM、磁卡或光卡、相变存储器（PCM）或适合用于存储电子或计算机可执行指令的其它类型的机器可读介质。例如，本公开的实施例可以作为计算机程序（例如BIOS）而被下载，所述计算机程序可以经由通信链路（例如调制解调器或网络连接）通过数据信号的方式从远程计算机（例如服务器）传输到请求计算机（例如客户端）。
连接性2170包括用来使得计算装置2100能够与外部装置通信的硬件装置（例如，无线和/或有线连接器和通信硬件）和软件组件（例如，驱动程序、协议栈）。计算装置2100能够是单独装置，诸如其它计算装置、无线接入点或基站以及外围设备，诸如耳机、打印机或者其它装置。
连接性2170可包括多个不同类型的连接性。概括来说，计算装置2100被示出为具有蜂窝连接性2172和无线连接性2174。蜂窝连接性2172一般指由无线载波提供的蜂窝网络连接性，诸如经由GSM（全球移动通信系统）或变型或衍生物、CDMA（码分多址）或变型或衍生物、TDM（时分复用）或变型或衍生物、或者其它蜂窝服务标准提供的蜂窝网络连接性。无线连接性（或无线接口）2174指不是蜂窝的无线连接性，并且可包括个人区域网络（诸如蓝牙、近场等）、局域网（诸如Wi-Fi）和/或广域网（诸如WiMax）或者其它无线通信。
外围连接2180包括用来进行外围连接的硬件接口和连接器以及软件组件（例如，驱动程序、协议栈）。将理解，计算装置2100能够既是到其它计算装置的外围装置（“到”2182），又具有连接到它的外围装置（“从”2184）。计算装置2100通常具有“对接（docking）”连接器以连接到其它计算装置，以用于诸如管理（例如，下载和/或上载、改变、同步）计算装置2100上的内容的目的。此外，对接连接器可允许计算装置2100连接到某些外围设备，所述外围设备允许计算装置2100控制例如到视听系统或其它系统的内容输出。
除了专用对接连接器或其它专用连接硬件之外，计算装置2100还可经由通常或基于标准的连接器进行外围连接2180。通常类型可包括通用串行总线（USB）连接器（其可包括多种不同硬件接口中的任何硬件接口）、包括MiniDisplayPort（MDP）的DisplayPort、高清晰度多媒体接口（HDMI）、火线（firewire）或其它类型。
在一些实施例中，可以使用包括两个或多于两个堆叠管芯的半导体封装来形成计算系统2100的一个或多个组件，其中堆叠管芯中的至少一个具有在两个相对表面上形成的互连层，例如，如关于图1-3B所讨论的。仅作为示例，计算装置2100的第一组件（例如，存储器子系统2160的存储器）可以被包括在图1-3B的管芯102或105中的一个管芯，并且计算装置2100的第二组件（例如，处理器2110）可以被包括在图1-3B的管芯102或105中的另一个管芯。
说明书中对“实施例”、“一个实施例”、“一些实施例”或“其它实施例”的参考意味着结合实施例描述的特定特征、结构或特性被包括在至少一些实施例中，但不一定被包括在全部实施例中。“实施例”、“一个实施例”或“一些实施例”的各种出现不一定全部指相同的实施例。如果说明书陈述“可以”、“可能”或“能够”包括组件、特征、结构或特性，则不要求包括该特定组件、特征、结构或特性。如果说明书或权利要求书提到“一（a或an）”元件，则这不意味着仅存在元件中的一个元件。如果说明书或权利要求书提到“附加”元件，则这不排除存在附加元件中的多于一个附加元件。
此外，特定特征、结构、功能或特性可以以任何合适的方式组合在一个或多个实施例中。例如，在与两个实施例关联的特定特征、结构、功能或特性不相互排斥的任何地方，第一实施例可以与第二实施例组合。
虽然已经结合本公开的特定实施例描述了本公开，但是依据前面的描述，此类实施例的许多备选方案、修改和变型对于本领域普通技术人员将是显而易见的。本公开的实施例意图涵盖落入所附权利要求书的宽泛范围内的全部此类备选方案、修改和变型。
此外，为了说明和讨论的简单性，并且为了不使本公开模糊，在所呈现的附图内可以或可以不示出到集成电路（IC）芯片和其它组件的公知的功率/接地连接。此外，可以以框图形式示出布置以便免于使本公开模糊，并且还鉴于关于此类框图布置的实现的详情高度取决于要在其中实现本公开的平台的事实（即，此类详情应该充分在本领域技术人员的知识范围内）而示出布置。在阐述特定细节（例如电路）以便描述本公开的示例实施例的情况下，对于本领域技术人员应该显而易见的是，能够在没有这些特定细节的情况下或者在有这些特定细节的变型的情况下来实践本公开。因此，本描述要被看作是说明性而不是限制性的。
以下示例条项涉及进一步的实施例。可以在一个或多个实施例中在任何地方使用示例条项中的详情。本文中所描述的设备的全部可选特征也可以关于方法或过程来被实现。
示例1. 一种设备，包括：具有第一表面和第二表面的第一管芯，所述第一管芯包括：在所述第一管芯的所述第一表面上形成的第一层，其中所述第一层包括一个或多个第一互连，以及在所述第一管芯的所述第二表面上形成的第二层，其中所述第二层包括一个或多个第二互连；耦合到所述第一层的第二管芯；以及用来将所述设备耦合到外部组件的多个结构，其中所述多个结构耦合到所述第二层。
示例2. 如示例1或任何其它示例所述的设备，其中所述第一管芯缺少将所述第一表面上的所述第一层和所述第二表面上的所述第二层连接的穿硅通孔（TSV）。
示例3. 如示例1或任何其它示例所述的设备，其中所述第一管芯包括：耦合到所述第一层的第一多个有源组件；以及耦合到所述第二层的第二多个有源组件。
示例4. 如示例1-3中任一项或任何其它示例所述的设备，其中所述多个结构是第一多个结构，并且其中所述设备进一步包括：耦合到所述第二管芯的第二多个结构，其中所述第二管芯通过所述第二多个结构耦合到所述第一层。
示例5. 如示例4或任何其它示例所述的设备，进一步包括：耦合到第一层的第三层，其中所述第三层包括一个或多个重分布结构，其中所述第二管芯通过所述第三层耦合到所述第一层。
示例6. 如示例4或任何其它示例的设备，其中所述第二管芯耦合到所述第一层，而在所述第二管芯与所述第一层之间没有包括重分布结构的任何中间层。
示例7. 如示例1-3中任一项或任何其它示例所述的设备，进一步包括：耦合到第二层的第三层，其中所述第三层包括一个或多个重分布结构，其中所述多个结构经由所述第三层耦合到所述第二层。
示例8. 如示例1-3中任一项或任何其它示例所述的设备，进一步包括：设置在所述第一管芯和所述第二管芯之间的第三管芯，其中所述第二管芯经由所述第三管芯耦合到所述第一层。
示例9. 如示例8或任何其它示例所述的设备，其中所述第三管芯包括：在所述第三管芯的第一表面上形成的第三层；以及在所述第三管芯的第二表面上形成的第四层，其中所述第三管芯缺少将所述第三层和所述第四层连接的穿硅通孔（TSV）。
示例10. 一种半导体封装，包括：以堆叠布置来布置的第一管芯、第二管芯和第三管芯，其中所述第二管芯包括：第一互连层，所述第一互连层被形成在所述第二管芯的第一表面上并且耦合到所述第一管芯，以及第二互连层，所述第二互连层被形成在所述第二管芯的第二表面上并且耦合到所述第三管芯，以及其中所述第二管芯缺少用来将所述第一互连层和所述第二互连层连接的任何穿硅通孔（TSV）。
示例11. 如示例10或任何其它示例所述的半导体封装，其中所述第二管芯的所述第一表面和所述第二管芯的所述第二表面是所述第二管芯的两个相对表面。
示例12. 如示例10或任何其它示例所述的半导体封装，其中所述第一管芯包括：第三互连层，所述第三互连层被形成在所述第一管芯的第一表面上并且耦合到封装互连结构以将所述半导体封装耦合到外部组件；以及第四互连层，所述第四互连层被形成在所述第一管芯的第二表面上并且耦合到所述第二管芯的所述第一互连层，其中所述第一管芯缺少用来将所述第三互连层和所述第四互连层连接的任何穿硅通孔（TSV）。
示例13. 如示例10-12中任一项或任何其它示例所述的半导体封装，其中所述第二管芯包括：耦合到所述第一互连层的第一多个有源组件；以及耦合到所述第二互连层的第二多个有源组件。
示例14. 如示例10-12中任一项或任何其它示例所述的半导体封装，进一步包括：用来密封所述第一管芯、所述第二管芯和所述第三管芯的模塑料。
示例15. 一种方法，包括：将第一管芯放置在衬底上，所述第一管芯包括：包括一个或多个有源装置的第一层，在所述第一层的第一侧上的第二层，其中所述第二层包括一个或多个第一互连，在所述第一层的第二侧上的第三层，其中所述第三层包括一个或多个第二互连，以及包括体材料的第四层，其中所述第二层在所述第一层和所述第四层之间；以及选择性地去除所述第四层以暴露所述第二层，使得所述第一管芯的两个相对表面分别包括所述第二层和所述第三层。
示例16. 如示例15或任何其它示例所述的方法，进一步包括：在所述衬底上形成第五层，其中所述第五层包括重分布结构，并且其中所述第一管芯被放置在所述衬底上，使得所述第三层被设置在所述第五层上。
示例17. 如示例15或任何其它示例所述的方法，其中选择性地去除所述第四层包括：沉积模塑料以密封所述第一管芯；以及选择性地去除所述模塑料的至少一部分连同所述第四层，以通过所述模塑料暴露所述第二层。
示例18. 如示例15或任何其它示例所述的方法，其中选择性地去除所述第四层包括：经由蚀刻、研磨或抛光操作中的一个或多个选择性地去除所述第四层。
示例19. 如示例15或任何其它示例所述的方法，进一步包括：在所述第二层上形成第五层，所述第五层包括重分布结构；以及将第二管芯放置在所述第五层上。
示例20. 如示例15-18中任一项或任何其它示例所述的方法，进一步包括：将第二管芯放置在所述第二层上，而在所述第二管芯和所述第一管芯之间没有包括重分布结构的任何中间层。
示例21. 如示例15-18中任一项或任何其它示例所述的方法，进一步包括：去除所述衬底以暴露所述第三层；以及在所述第三层上沉积多个互连结构。
示例22. 如示例21或任何其它示例所述的方法，其中：所述多个互连结构要将所述第一管芯耦合到外部组件。
示例23. 如示例15-18中任一项或任何其它示例所述的方法，其中将所述第一管芯放置在所述衬底上包括：将所述第一管芯的所述第三层放置在所述衬底上。
示例24. 如示例15-18中任一项或任何其它示例所述的方法，其中选择性地去除所述第四层包括：选择性地去除所述第四层，同时将所述第一管芯放置在所述衬底上。
示例25. 如示例15-18中任一项或任何其它示例所述的方法，进一步包括：避免形成用于将所述第二层和所述第三层连接的任何通孔。
示例26. 一种设备，包括：用于执行如示例15-25中任一项或任何其它示例所述的方法的部件。
示例27. 一种设备，包括：用于将第一管芯放置在衬底上的部件，所述第一管芯包括：包括一个或多个有源装置的第一层，在所述第一层的第一侧上的第二层，其中所述第二层包括一个或多个第一互连，在所述第一层的第二侧上的第三层，其中所述第三层包括一个或多个第二互连，以及包括体材料的第四层，其中所述第二层在所述第一层和所述第四层之间；以及用于选择性地去除所述第四层以暴露所述第二层使得所述第一管芯的两个相对表面分别包括所述第二层和所述第三层的部件。
示例28. 如示例27或任何其它示例所述的设备，进一步包括：用于在所述衬底上形成第五层的部件，其中所述第五层包括重分布结构，并且其中所述第一管芯被放置在所述衬底上，使得所述第三层被设置在所述第五层上。
示例29. 如示例27或任何其它示例所述的设备，其中用于选择性地去除所述第四层的所述部件包括：用于沉积模塑料以密封所述第一管芯的部件；以及用于选择性地去除所述模塑料的至少一部分连同所述第四层以通过所述模塑料暴露所述第二层的部件。
示例30. 如示例27或任何其它示例所述的设备，其中用于选择性地去除所述第四层的所述部件包括：用于经由蚀刻、研磨或抛光操作中的一个或多个选择性地去除所述第四层的部件。
示例31. 如示例27或任何其它示例所述的设备，进一步包括：用于在所述第二层上形成第五层的部件，所述第五层包括重分布结构；以及用于将第二管芯放置在所述第五层上的部件。
示例31. 如示例27-30中任一项或任何其它示例所述的设备，进一步包括：用于将第二管芯放置在所述第二层上而在所述第二管芯和所述第一管芯之间没有包括重分布结构的任何中间层的部件。
示例32. 如示例27-30中任一项或任何其它示例所述的设备，进一步包括：用于去除所述衬底以暴露所述第三层的部件；以及用于在所述第三层上沉积多个互连结构的部件。
示例33. 如示例32或任何其它示例所述的设备，其中：所述多个互连结构要将所述第一管芯耦合到外部组件。
示例34. 如示例27-30中任一项或任何其它示例所述的设备，其中用于将所述第一管芯放置在所述衬底上的所述部件包括：用于将所述第一管芯的所述第三层放置在所述衬底上的部件。
示例35. 如示例27-30中任一项或任何其它示例所述的设备，其中用于选择性地去除所述第四层的所述部件包括：用于选择性地去除所述第四层同时将所述第一管芯放置在所述衬底上的部件。
示例36. 如示例27-30中任一项或任何其它示例所述的设备，进一步包括：用于避免形成用于将所述第二层和所述第三层连接的任何通孔的部件。
提供了将允许读者确定技术公开的性质和要点的摘要。在摘要将不用于限制权利要求书的范围或含义的前提下提交摘要。以下权利要求书由此被合并在具体实施方式中，其中每个权利要求独立地作为单独的实施例。

Claims (25)

1.一种设备，包括：
具有第一表面和第二表面的第一管芯，所述第一管芯包括：
在所述第一管芯的所述第一表面上形成的第一层，其中所述第一层包括一个或多个第一互连，以及
在所述第一管芯的所述第二表面上形成的第二层，其中所述第二层包括一个或多个第二互连；
耦合到所述第一层的第二管芯；以及
用来将所述设备耦合到外部组件的多个结构，其中所述多个结构耦合到所述第二层。
2.如权利要求1所述的设备，其中所述第一管芯缺少将所述第一表面上的所述第一层和所述第二表面上的所述第二层连接的穿硅通孔（TSV）。
3. 如权利要求1所述的设备，其中所述第一管芯包括：
耦合到所述第一层的第一多个有源组件；以及
耦合到所述第二层的第二多个有源组件。
4.如权利要求1-3中任一项所述的设备，其中所述多个结构是第一多个结构，并且其中所述设备进一步包括：
耦合到所述第二管芯的第二多个结构，
其中所述第二管芯通过所述第二多个结构耦合到所述第一层。
5.如权利要求4所述的设备，进一步包括：
耦合到第一层的第三层，其中所述第三层包括一个或多个重分布结构，
其中所述第二管芯通过所述第三层耦合到所述第一层。
6.如权利要求4所述的设备，其中所述第二管芯耦合到所述第一层，而在所述第二管芯与所述第一层之间没有包括重分布结构的任何中间层。
7.如权利要求1-3中任一项所述的设备，进一步包括：
耦合到第二层的第三层，其中所述第三层包括一个或多个重分布结构，
其中所述多个结构经由所述第三层耦合到所述第二层。
8.如权利要求1-3中任一项所述的设备，进一步包括：
设置在所述第一管芯和所述第二管芯之间的第三管芯，
其中所述第二管芯经由所述第三管芯耦合到所述第一层。
9. 如权利要求8所述的设备，其中所述第三管芯包括：
在所述第三管芯的第一表面上形成的第三层；以及
在所述第三管芯的第二表面上形成的第四层，
其中所述第三管芯缺少将所述第三层和所述第四层连接的穿硅通孔（TSV）。
10.一种半导体封装，包括：
以堆叠布置来布置的第一管芯、第二管芯和第三管芯，
其中所述第二管芯包括：
第一互连层，所述第一互连层被形成在所述第二管芯的第一表面上并且耦合到所述第一管芯，以及
第二互连层，所述第二互连层被形成在所述第二管芯的第二表面上并且耦合到所述第三管芯，以及
其中所述第二管芯缺少用来将所述第一互连层和所述第二互连层连接的任何穿硅通孔（TSV）。
11.如权利要求10所述的半导体封装，其中所述第二管芯的所述第一表面和所述第二管芯的所述第二表面是所述第二管芯的两个相对表面。
12. 如权利要求10所述的半导体封装，其中所述第一管芯包括：
第三互连层，所述第三互连层被形成在所述第一管芯的第一表面上并且耦合到封装互连结构以将所述半导体封装耦合到外部组件；以及
第四互连层，所述第四互连层被形成在所述第一管芯的第二表面上并且耦合到所述第二管芯的所述第一互连层，
其中所述第一管芯缺少用来将所述第三互连层和所述第四互连层连接的任何穿硅通孔（TSV）。
13. 如权利要求10-12中任一项所述的半导体封装，其中所述第二管芯包括：
耦合到所述第一互连层的第一多个有源组件；以及
耦合到所述第二互连层的第二多个有源组件。
14.如权利要求10-12中任一项所述的半导体封装，进一步包括：
用来密封所述第一管芯、所述第二管芯和所述第三管芯的模塑料。
15.一种方法，包括：
将第一管芯放置在衬底上，所述第一管芯包括：
包括一个或多个有源装置的第一层，
在所述第一层的第一侧上的第二层，其中所述第二层包括一个或多个第一互连，
在所述第一层的第二侧上的第三层，其中所述第三层包括一个或多个第二互连，以及
包括体材料的第四层，其中所述第二层在所述第一层和所述第四层之间；以及
选择性地去除所述第四层以暴露所述第二层，使得所述第一管芯的两个相对表面分别包括所述第二层和所述第三层。
16.如权利要求15所述的方法，进一步包括：
在所述衬底上形成第五层，其中所述第五层包括重分布结构，并且其中所述第一管芯被放置在所述衬底上，使得所述第三层被设置在所述第五层上。
17. 如权利要求15所述的方法，其中选择性地去除所述第四层包括：
沉积模塑料以密封所述第一管芯；以及
选择性地去除所述模塑料的至少一部分连同所述第四层，以通过所述模塑料暴露所述第二层。
18.如权利要求15所述的方法，其中选择性地去除所述第四层包括：
经由蚀刻、研磨或抛光操作中的一个或多个选择性地去除所述第四层。
19. 如权利要求15所述的方法，进一步包括：
在所述第二层上形成第五层，所述第五层包括重分布结构；以及
将第二管芯放置在所述第五层上。
20.如权利要求15-18中任一项所述的方法，进一步包括：
将第二管芯放置在所述第二层上，而在所述第二管芯和所述第一管芯之间没有包括重分布结构的任何中间层。
21. 如权利要求15-18中任一项所述的方法，进一步包括：
去除所述衬底以暴露所述第三层；以及
在所述第三层上沉积多个互连结构。
22.如权利要求21所述的方法，其中：
所述多个互连结构要将所述第一管芯耦合到外部组件。
23.如权利要求15-18中任一项所述的方法，其中将所述第一管芯放置在所述衬底上包括：
将所述第一管芯的所述第三层放置在所述衬底上。
24.如权利要求15-18中任一项所述的方法，其中选择性地去除所述第四层包括：
选择性地去除所述第四层，同时将所述第一管芯放置在所述衬底上。
25.如权利要求15-18中任一项所述的方法，进一步包括：
避免形成用于将所述第二层和所述第三层连接的任何通孔。
CN201780094256.5A 2017-09-25 2017-09-25 使用具有双侧互连层的管芯的单片芯片堆叠 Pending CN110998836A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311535358.XA CN117995801A (zh) 2017-09-25 2017-09-25 使用具有双侧互连层的管芯的单片芯片堆叠

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2017/053291 WO2019059950A1 (en) 2017-09-25 2017-09-25 STACK OF MONOLITHIC CHIPS USING A DOUBLE-SIDED INTERCONNECTION LAYER

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202311535358.XA Division CN117995801A (zh) 2017-09-25 2017-09-25 使用具有双侧互连层的管芯的单片芯片堆叠

Publications (1)

Publication Number Publication Date
CN110998836A true CN110998836A (zh) 2020-04-10

Family

ID=65810504

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202311535358.XA Pending CN117995801A (zh) 2017-09-25 2017-09-25 使用具有双侧互连层的管芯的单片芯片堆叠
CN201780094256.5A Pending CN110998836A (zh) 2017-09-25 2017-09-25 使用具有双侧互连层的管芯的单片芯片堆叠

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202311535358.XA Pending CN117995801A (zh) 2017-09-25 2017-09-25 使用具有双侧互连层的管芯的单片芯片堆叠

Country Status (4)

Country Link
US (4) US11251158B2 (zh)
CN (2) CN117995801A (zh)
DE (1) DE112017008093T5 (zh)
WO (1) WO2019059950A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115424980A (zh) * 2022-11-04 2022-12-02 成都复锦功率半导体技术发展有限公司 一种芯片双面互连的堆叠封装方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117995801A (zh) * 2017-09-25 2024-05-07 英特尔公司 使用具有双侧互连层的管芯的单片芯片堆叠
EP3732713A4 (en) * 2017-12-28 2021-08-04 INTEL Corporation DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF INTEGRATED CIRCUIT CHIPS

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080296763A1 (en) * 2007-05-31 2008-12-04 Chen-Shien Chen Multi-Die Wafer Level Packaging
US20110204505A1 (en) * 2010-02-23 2011-08-25 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier
WO2013016264A2 (en) * 2011-07-27 2013-01-31 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
DE102014108992A1 (de) * 2013-06-28 2014-12-31 Intel Corporation Fließverhalten von Unterfüllmaterial für reduzierte Abstände zwischen den Chiplagen in Halbleiterpaketen
US20150340327A1 (en) * 2014-05-22 2015-11-26 Invensas Corporation Compact semiconductor package and related methods
US20150371938A1 (en) * 2014-06-19 2015-12-24 Invensas Corporation Back-end-of-line stack for a stacked device
CN106133897A (zh) * 2014-02-14 2016-11-16 高通股份有限公司 包括重分布层上的堆叠管芯的集成器件
WO2017111792A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Fabrication and use of through silicon vias on double sided interconnect device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US7056810B2 (en) * 2002-12-18 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance
US7670927B2 (en) * 2006-05-16 2010-03-02 International Business Machines Corporation Double-sided integrated circuit chips
US9893042B2 (en) 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR102351676B1 (ko) * 2017-06-07 2022-01-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
CN117995801A (zh) * 2017-09-25 2024-05-07 英特尔公司 使用具有双侧互连层的管芯的单片芯片堆叠

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080296763A1 (en) * 2007-05-31 2008-12-04 Chen-Shien Chen Multi-Die Wafer Level Packaging
US20110204505A1 (en) * 2010-02-23 2011-08-25 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier
WO2013016264A2 (en) * 2011-07-27 2013-01-31 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
DE102014108992A1 (de) * 2013-06-28 2014-12-31 Intel Corporation Fließverhalten von Unterfüllmaterial für reduzierte Abstände zwischen den Chiplagen in Halbleiterpaketen
CN106133897A (zh) * 2014-02-14 2016-11-16 高通股份有限公司 包括重分布层上的堆叠管芯的集成器件
US20150340327A1 (en) * 2014-05-22 2015-11-26 Invensas Corporation Compact semiconductor package and related methods
US20150371938A1 (en) * 2014-06-19 2015-12-24 Invensas Corporation Back-end-of-line stack for a stacked device
WO2017111792A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Fabrication and use of through silicon vias on double sided interconnect device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115424980A (zh) * 2022-11-04 2022-12-02 成都复锦功率半导体技术发展有限公司 一种芯片双面互连的堆叠封装方法
CN115424980B (zh) * 2022-11-04 2023-02-07 成都复锦功率半导体技术发展有限公司 一种芯片双面互连的堆叠封装方法

Also Published As

Publication number Publication date
US20230411356A1 (en) 2023-12-21
WO2019059950A1 (en) 2019-03-28
US20200212011A1 (en) 2020-07-02
US11784165B2 (en) 2023-10-10
CN117995801A (zh) 2024-05-07
US11251158B2 (en) 2022-02-15
US20220093569A1 (en) 2022-03-24
US20240030188A1 (en) 2024-01-25
DE112017008093T5 (de) 2020-07-02

Similar Documents

Publication Publication Date Title
US11784165B2 (en) Monolithic chip stacking using a die with double-sided interconnect layers
TWI786068B (zh) 半導體封裝及用於半導體封裝的設備
US11664290B2 (en) Package with underfill containment barrier
US20130292840A1 (en) Stacked memory allowing variance in device interconnects
TW202101702A (zh) 基板補片重構選項
US10714446B2 (en) Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such
US11908802B2 (en) Multi-chip package with high density interconnects
US11705377B2 (en) Stacked die cavity package
US20190311983A1 (en) Stacking multiple dies having dissimilar interconnect structure layout and pitch
US10879152B2 (en) Through mold via (TMV) using stacked modular mold rings
US11594463B2 (en) Substrate thermal layer for heat spreader connection
US11948831B2 (en) Apparatus with multi-wafer based device and method for forming such
CN111052374B (zh) 多级分布式钳位器
EP3506348B1 (en) Thin film passive devices integrated in a package substrate
US20240222346A1 (en) Architectures for memory on integrated circuit device packages
US11037916B2 (en) Apparatus with multi-wafer based device comprising embedded active devices and method for forming such
US20190169020A1 (en) Package substrate integrated devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination