TWI786068B - 半導體封裝及用於半導體封裝的設備 - Google Patents

半導體封裝及用於半導體封裝的設備 Download PDF

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TWI786068B
TWI786068B TW106135296A TW106135296A TWI786068B TW I786068 B TWI786068 B TW I786068B TW 106135296 A TW106135296 A TW 106135296A TW 106135296 A TW106135296 A TW 106135296A TW I786068 B TWI786068 B TW I786068B
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die
substrate
component
interposer
interconnect
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TW106135296A
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TW201841314A (zh
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迪格維傑 羅雷恩
拉文德納斯 馬哈加
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美商英特爾股份有限公司
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Abstract

提供一種設備包含：基板；具有第一側和第二側的晶粒，其中該晶粒被裝設在該基板上使得該晶粒之該第一側面對該基板，且其中該晶粒之該第一側的至少部分被移除以在該晶粒中形成凹入部；以及組件，其中該組件的至少一部分被配置在該第一晶粒中的該凹入部中。

Description

半導體封裝及用於半導體封裝的設備
本發明係關於在晶粒堆疊中用以容納組件之凹入的半導體晶粒。
現代消費者電子裝置，例如蜂巢式電話、智慧電話、平板、膝上型電腦等正變得更薄。包括在這些裝置中的半導體封裝通常需要用以裝設在該封裝的基板上的組件。在半導體封裝中，這些組件能例如增加封裝的高度及/或能增加封裝的覆蓋區(foot print)。
100:半導體封裝
102a:晶粒
102b:晶粒
102c:晶粒
104:基板
106:互連結構
108:互連結構
S1a:晶粒102a之頂部表面
S1b:晶粒102a之底部表面
110:互連結構
112:互連結構
114:互連結構
116:互連結構
118:直通矽穿孔
120:模製複合物
122:互連組件
124:組件
126:互連結構
128:互連結構
130:凹入區域
100a:部分的封裝
100b:部分的封裝
100c:部分的封裝
100d:部分的封裝
300a:部分的封裝
308:互連墊
400:半導體封裝
130’:凹入區域
430:凹入區域
500:半導體封裝
118’:直通矽穿孔
500a:封裝
500b:封裝
501:互連墊
530:凹入區域
600:半導體封裝
126’:互連結構
126”:互連結構
128’:互連結構
128”:互連結構
700:半導體封裝
706:互連結構
708:互連結構
710:互連墊
118”:直通矽穿孔
724:組件
700b:封裝
706’:互連結構
708’:互連結構
710’:互連墊
2100:計算裝置
2110:第一處理器
2120:音頻子系統
2130:顯示子系統
2132:顯示介面
2140:I/O控制器
2150:電源管理
2160:記憶體子系統
2170:通訊連結
2172:蜂巢式通訊連結
2174:無線通訊連結
2180:周邊連接
2190:感測器
2200:微機電系統
本揭露之實施例將從下面給定的詳細說明以及從本揭露之各種實施例之附隨的圖式更充分地了解，然而其不應被採用來將本揭露限制到特定實施例，而僅用於解釋或了解。
圖1依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來在第一晶粒中的凹入區中容納組件。
圖2A~2G依據一些實施例闡述形成半導體封裝的過程，其中該半導體封裝包含在組件裝設於其中的晶粒中的凹入區域。
圖3A~3D依據一些實施例闡述形成半導體封裝的另一過程，其中該半導體封裝包含在組件裝設於其中的晶粒中的凹入區域。
圖4依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒和基板被選擇性地凹入以容納組件。
圖5A依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來容納電耦接至該第一晶粒的組件。
圖5B依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒和基板被選擇性地凹入來容納電耦接至該第一晶粒的組件。
圖6依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來容納電耦接至該第一晶粒及至 基板的組件。
圖7A依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來容納第一組件，且其中第二組件配置在該第一晶粒之未凹入區域與該基板之間。
圖7B依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來容納第一組件，且其中第二組件配置在該第一晶粒之未凹入的區域與該基板之間且附接至該基板。
圖8依據一些實施例闡述描繪用於將組件配置在晶粒之凹入的區域中的方法之流程圖，其中該晶粒為堆疊的多個晶粒之一部分。
圖9依據一些實施例闡述計算裝置、智慧裝置、計算裝置或電腦系統或SoC(晶片上系統)，在其中第二晶粒以覆晶晶片組態堆疊於第一晶粒上，其中該第一晶粒之非有效側被凹入且組件係配置至少部分在該第一晶粒中的凹入區域上。
【發明內容】及【實施方式】
在一些實施例中，半導體封裝可包括若干個堆疊的晶粒。例如，第一晶粒能被裝設在基板上，且一或多個額外的晶粒能被裝設在該第一晶粒上。在一些實施例中，該第一側之非有效(inactive)側能面對該基板，同時該 一或多個額外的晶粒能被裝設在該第一晶粒之有效(active)側。因為該第一晶粒作為該一或多個額外的晶粒與該基板之間的中介層(interposer)，該第一晶粒亦有時稱為中介層晶粒(interposer die)或是矽中介層(silicon interposer)。
在一些實施例中，組件被裝設在該基板之表面上，其中該組件亦有時稱為表面裝設技術(SMT；surface mount technology)組件。組件能為任何適當的主動或被動組件，例如電容器、電阻器、電感器、磁心電感器(MCI；magnetic core inductor)、時脈產生電路、電壓調控電路、晶粒或類似者。
在一些實施例中，在該半導體封裝中該第一晶粒之非有效側的區段被移除或被切割以在該第一晶粒中形成凹入區域。在一些實施例中，該組件被裝設到基板上使得該組件的至少部分在該凹入區域中。在一些其他實施例中，該組件被裝設到該第一晶粒上使得該組件的至少部分在該凹入區域中。
有許多各種實施例的技術效果。例如，能使用於此說明的技術來將第二晶粒裝設到第一晶粒上、將該第一晶粒裝設到基板上、在該第一晶粒中創建凹入區域以及將組件至少部分配置於該凹入區域內。據此，由於在半導體封裝中裝設該組件，該半導體封裝之高度並未增加。由於在半導體封裝中裝設該組件，該半導體封裝之覆蓋區的表面積亦未增加。進一步而言，亦可使用本揭露之原理 來將多於一個這類的組件(例如，多於一個SMT組件)包括在半導體封裝內。其它技術效果從各種實施例及圖將為明白的。
在下列說明中，討論眾多的細節來提供本揭露之實施例的更全面的解釋。然而，對本領域具有通常知識者將為顯見的是，本發明之實施例可不以這些特定細節來實行。在其它實例中，周知的結構及裝置係以方塊圖形式而非詳細地來繪示，以避免模糊本揭露之實施例。
注意，在實施例之對應的圖式中，信號係以線來代表。一些線可能較厚，用以指示更多組成的信號路徑，及/或在一或兩端具有箭頭，用以指示主要資訊流向。這類指示並不打算為限制的。相反的，線係連同一或多個示範性實施例來使用，用以促進更容易的了解電路或邏輯單元。如由設計需要或優選所指定的任何代表的信號可實際包含可在任一的方向上行進且可以任何合適類型的信號方案來實施的一或多個信號。
貫穿說明書且在申請專利範圍中，術語「連接」意味直接連接，像是在連接的物之間的電性、機械或磁性連接而沒有任何中間的裝置。術語「耦接」意味直接或間接連接，像是透過一或多個被動或主動中間裝置在連接的物之間的直接電性、機械或磁性連接或是間接連接。術語「電路」或「模組」可指的是一或多個被動及/或主動組件，其被安排來與彼此配合，用以提供所欲的功能。術語「信號」可指的是至少一電流信號、電壓信號、磁信 號或資料/時脈信號。「一種(a)」、「一(an)」及「該」的意義包括複數個參考。「在…中(in)」之意義包括「在…中」和「在…上」。術語「實質的」、「接近」、「大約」、「附近」以及「約」一般指的是目標值的+/- 10%內。
除非另以明定，用以描述普通物件的序數形容詞「第一」、「第二」及「第三」等的使用僅指示相似的物件之不同的實例正被參照並且不打算暗示所描述的物件在時間地、空間地、排序地或以任何其它方式必需在給定的順序中。
為了本揭露的目的，詞彙「A及/或B」及「A或B」意味(A)、(B)或(A及B)。為了本揭露的目的，詞彙「A、B及/或C」意味(A)，(B)，(C)，(A及B)，(A及C)，(B及C)，或(A、B及C)。在說明書中及在申請專利範圍中術語「左」、「右」、「前」、「後」、「頂」、「底」、「在…之上」、「在…之下」及類似者(若有任一者)被使用於描述性的目的且不必然用於說明永久的相對位置。
圖1依據一些實施例闡述包含堆疊的複數個晶粒(例如，晶粒102a、102b、102c)的半導體封裝100(此後亦稱為「封裝100」)的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒(例如，晶粒102a)被選擇性的凹入，用以容納組件124。在一些實施例中，堆疊的複數個晶粒包含第一晶粒102a，第二晶粒102b和第三晶粒102c係堆疊於其 上。雖然在圖1的範例中兩個晶粒102b及102c被堆疊在晶粒102a上，任何其它數目的晶粒能以任何適當的組態被堆疊於晶粒102a上。僅作為範例，一、多個晶粒能被堆疊在晶粒102b及102c其中一者或兩者上。在另一範例中，僅單一晶粒102b能被堆疊在晶粒102a上。又在另一範例中，三或更多晶粒(例如，晶粒102b、102c及另外一或更多晶粒)能在晶粒102a上以併排的組態來堆疊。
在一些實施例中，晶粒102a、102b及102c能為任何適當的積體電路晶粒。例如，晶粒102a、102b、102c之個別者能為處理器、晶片上系統(SOC)、記憶體、特定應用電路(ASIC)、數據機(modem)、基帶處理器、RF(無線電頻率)IC、這類功能的某種組合及/或類似者。在一些實施例中，封裝100之一或多個頂部晶粒(例如，晶粒102b或102c的一或兩者)能為記憶體晶粒，同時底部晶粒102a能為處理器。
晶粒102a之頂部表面及底部表面在圖1中被分別標記為S1a和S1b。例如，晶粒102a在封裝100中形成底部晶粒，並且晶粒102b及102c被組態以於晶粒102a之頂部表面S1a上堆疊。
在一些實施例中，晶粒102a可被裝設在基板104上。在一些實施例中，基板104可為印刷電路板(PCB；Printed Circuit Board)，其由電絕緣材料組成，像是環氧積層(epoxy laminate)。例如，基板104可包括由像是酚醛棉紙(phenolic cotton paper)材料(例如，FR-1)、棉紙及環 氧材料(例如，FR-3)、使用環氧樹脂層疊在一起的織狀玻璃材料(FR-4)、具有環氧樹脂的玻璃/紙(例如，CEM-1)、具有環氧樹脂的玻璃合成物、具有聚四氟乙烯(polytetrafluoroethylene)的織狀玻璃布料(例如，PTFE CCL)或其它基於聚四氟乙烯的(polytetrafluoroethylene-based)的預浸布(prepreg)材料的材料所組成的電絕緣層。
在一些實施例中，晶粒102a之底部表面S1b例如經由複數個互連結構106及108附接至基板104。互連結構106例如為凸塊、凸塊墊(bump pad)、金屬柱(例如，銅柱)、使用金屬、合金、可焊的材料形成的球或類似者。互連結構108例如為使用金屬、合金、可焊的材料或類似者形成的焊接。
在一些實施例中，晶粒102b及102c係例如經由互連結構110、112及114裝設在晶粒102a之頂部表面S1a上。互連結構110例如為凸塊、凸塊墊、金屬柱(例如，銅柱)、使用金屬、合金、可焊的材料形成的球或類似者，其在晶粒102b及102c之底部表面上形成。互連結構114例如為凸塊、凸塊墊、金屬柱(例如，銅柱)、使用金屬、合金、可焊的材料形成的球或類似者，其在晶粒102之頂部表面上形成。互連結構112例如為附接組件(attachment component)，像是使用金屬、合金、可焊材料或類似者形成的焊接，其將互連結構110與114附接，如在圖1中所繪示。
在一些實施例中，例如，互連結構110、112 及114亦稱為第一級互連(FLI；first level interconnect)，因為這些互連結構形成互連之第一層級，晶粒102b、102c透過其經由晶粒102a被連接至基板104。在一些實施例中，例如，互連結構106及108亦稱為第二級互連(SLI；second level interconnect)，因為這些互連結構形成互連之第二層級，晶粒102a、102b、102c透過其被連接至基板104。
在此揭露中各種圖闡述半導體封裝之兩個元件使用其連接的互連結構，並且該互連結構例如為凸塊、凸塊墊、金屬柱(例如，銅柱)、使用金屬、合金、可焊的材料形成的球、使用金屬、合金、可焊材料形成的焊接及/或類似者。然而，在其它實施例中並且雖然未在圖之任一者中闡述，在此揭露中討論的半導體封裝之任一者中，兩個元件能藉由其他適當的方式被附接、裝設、堆疊或耦接，例如使用異向性導電膜(ACF；anisotropic conductive film)、異向性導電膏(ACP；anisotropic conductive paste)及/或任何基於接著的(adhesive based)互連。
在一些實施例中，晶粒102b之互連結構110以球格陣列(BGA；ball grid array)來佈設。同樣的，在一些實施例中，晶粒102c之互連結構110以BGA來佈設。也同樣，在一些實施例中，晶粒102a之互連結構106以BGA來佈設。
晶粒102b和102c例如以覆晶晶片組態被裝設或堆疊在晶粒102a上。在一些實施例中，晶粒102a之頂側S1a可為通常被稱為晶粒102a之「有效(active)」或「前 (front)」側的晶粒102a之側。在一些實施例中，頂側S1a可包括一或多個電晶體、邏輯閘、電路、邏輯組件等(未在圖中闡述)。在一些實施例中，晶粒102a之底側S1b通常被稱為晶粒102a之「非有效(inactive)」或「後(back)」側。
在一些實施例中，晶粒102b之底部表面可為通常稱為晶粒102b之有效或前側的晶粒102b之側，且晶粒102c之底部表面可為通常稱為晶粒102c之有效或前側的晶粒102c之側。因此，舉例來說，晶粒102a和102b之有效側係經由互連結構110、112及114來附接，且亦同樣的，晶粒102a和102c之有效側係經由互連結構110、112及114來附接。因此，舉例來說，晶粒102a和102b係以面對面安排來佈設，且同樣的，晶粒102a和102c亦以面對面安排來佈設。
在一些實施例中，模製複合物(molding compound)120係在封裝100之至少一區段上形成。例如，模製複合物120將晶粒102a、102b及102c之至少一區段囊封，例如如在圖1中所闡述的。在一些實施例中，模製複合物120能為任何合適的材料，像是基於環氧建立的基板、其它介電/有機材料、樹脂、環氧、高分子接著劑(polymer adhesive)、矽、丙烯基(acrylic)、聚亞醯氨(polyimide)、氰酸酯(cyanate ester)、熱塑性塑料(thermoplastics)及/或熱固物(thermoset)。
在一些實施例中，晶粒102a包含複數個互連 組件116和複數個直通矽穿孔(TSV；through-silicon-via)118。互連組件116及/或TSV 118將晶粒102a、102b及/或102c之各種組件電互連至互連結構106的分別者。例如，TSV118將晶粒102a、102b及/或102c之各種組件經由互連結構106連接至基板104。在一些實施例中，各個互連結構106係在相應的TSV 118之端部上形成，如圖1所示。僅為範例的是，互連組件116之個別者包含跡線、溝槽、佈線層(routing layer)、接地面(ground plane)、電源面(power plane)、重分佈層(RDL；re-distribution layer)及/或任何其它適當的電佈線特徵。雖然互連組件116之特定型樣係闡述於圖1，這樣的型樣僅為範例。
在一些實施例中，晶粒102a作為晶粒102b、102c與基板104之間的中介層。據此，晶粒102a亦稱為中介層晶粒或矽中介層。在一些實施例中，中介層晶粒102a包括主動電路組件，像是電晶體、邏輯閘、電路及/或一般被包括在半導體晶粒中適當的組件。
在一些實施例中，基板104包含互連組件122的層。互連組件122能例如為跡線、重分佈層(RDL)、佈線結構、佈線層或用以將基板104之各種組件互連的其它互連結構。
在一些實施例中，封裝100包含組件124。組件124能例如為任何適當的主動或被動組件，例如電容器、電阻器、電感器、磁心電感器(MCI)、時脈產生電路、電壓調控電路或類似者。在另一範例中，組件124亦 能例如為晶粒，其尺寸相對的小(例如，相比於晶粒102a之尺寸)。在一些實施例中，組件124能裝設在基板104之表面上，例如如在圖1中所闡述(雖然在另一實施例中，組件124不可被裝設在基板104上，如於此之後所討論的)，因而於此亦稱為SMT組件。
在一些實施例中，組件124經由互連結構126及128被裝設且附接到基板104。互連結構128例如為凸塊、凸塊墊、金屬柱(例如，銅柱)、使用金屬、合金、可焊的材料形成的球或類似者，並且被附接到組件124的底部表面。互連結構126例如為使用金屬、合金、可焊的材料或類似者形成的焊接，並將互連結構128附接至基板104。
在一些實施例中，組件124係至少配置在晶粒102a之凹入區域130中。例如，晶粒102a之非有效側的部分(例如，其對應至底部表面S1b)被移除或切割以形成凹入區域130，並且組件124至少部分被配置在此凹入的區域130內。在一些實施例中，在晶粒102a之部分中形成凹入區域130而缺乏TSV 118和互連組件116。
雖然圖1闡述組件124被配置接近晶粒102a的周邊(例如，凹入區域130接近晶粒102a之周邊而形成)，組件124能被配置在基板104上的任何區域中。例如，凹入區域130能在晶粒102之非有效側上的任何適當的位置中形成(例如，在缺少任何TSV 118和互連組件116的區段上)。在一些其它實施例中(例如，於此之後在圖5A中所闡述的)， 凹入區域甚至能在包括TSV的晶粒102a之區域中形成(例如，組件124經由其能被連接至封裝的各種其它組件)。
雖然在圖1中闡述單一組件124以於晶粒102a之單一凹入區域130中沉積，多於一個這樣的組件能分別被配置在多於一個的晶粒102a之凹入區域。在另一範例中並且雖然未闡述於圖1中，多個這類組件能被配置在晶粒102a之單一凹入的區域(例如，凹入區域130)中。
依據一些實施例，圖2A~2G闡述圖1之形成封裝100的過程，其中封裝100包含組件124所被裝設於其中的晶粒102a中凹入區域。請參照圖2A，封裝100之部分100a包含晶粒102a、102b以及102c和模製複合物120。TSV 118係在晶粒102a之中間區段中形成。例如，TSV 118之底端還未被暴露而通過晶粒102a之底部表面。如在圖2A中所闡述，封裝100之部分100a能使用任何適當的技術來形成以用於形成這類封裝之部分。
在圖2B中，例如藉由使用化學機械平坦化(CMP；chemical-mechanical planarization)法、藉由蝕刻、藉由研磨等移除晶粒102a之底部表面直到例如TSV 118之底端被露出為止。舉例來說，在圖2B中TSV 118之底端和底部表面S1b可例如為齊平的，使得TSV 118之底端被露出而通過晶粒102a之底部表面S1b。
在一些實施例中，於圖2C中，移除晶粒102a之部分以在晶粒102a中形成腔室或凹入區域130(例如，從而形成部分的封裝100c)，例如如相對圖1所討論的。凹入 區域130能例如藉由蝕刻(例如，乾蝕刻及/或濕蝕刻)晶粒102a之底部表面S1b的區段來形成。在另一範例中，凹入區域130能藉由藉任何適當的方式移除晶粒102a之底部表面S1b的區段來形成，例如藉由機械切割該區段、藉由CMP法、藉由雷射或機械鑽孔及/或類似者。
在一些實施例中，於圖2D中，複數個互連結構106例如在晶粒102a之底部表面S1b上形成，從而形成部分的封裝100d。例如，各個互連結構106被附接至TSV 118之對應者。
在一些實施例中，於圖2E中，例如使用用於形成這類基板的適當的技術來形成基板104。基板104例如包括互連組件122和互連結構108及126。於圖2F中，在一些實施例中，組件124例如經由互連結構126及128被裝設到基板104上。在範例中，組件124能經由互連墊(未在圖2F中闡述)或經由在組件124(例如，互連結構126)上形成的銅凸塊被附接至互連結構126。
要注意的是，能無關於相對圖2E~2F所討論的操作來進行相對圖2A~2D討論的操作(例如，圖2A~2D之操作能在相對圖2E~2F討論的操作之前、至少部分並行及/或之後來進行)。
在一些實施例中，於圖2G中，圖2D之部分封裝100d被裝設到圖2F之基板104上。在範例中，將圖2D之部分封裝100d裝設到圖2F之基板104上(如在圖2G中所闡述)造成了圖1的封裝100。在一些實施例中，圖2D之部分 封裝100d被裝設到圖2F之基板104上，使得組件124配適於晶粒102a之凹入區域130中。
在圖2A~2G中所述的過程之幾個變化能例如基於本揭露之教示由本領域之該些者預見。例如，如在圖2E中所闡述的，互連結構108被假定為初始地沉積在基板上(例如，在晶粒102a被裝設在基板104上之前)。在另一範例中，能在晶粒102a上形成互連結構108，如在圖3A~3D中所闡述。依據一些實施例，圖3A~3D闡述圖1之形成封裝100的過程，其中封裝100包含組件124所被裝設於其中的晶粒102a中凹入區域。
圖3A闡述部分封裝300a，其係藉由將互連結構108沉積在圖2D之部分封裝100d之互連結構106上來形成。在一些實施例中，因為互連結構108(其例如為焊接)係在晶粒102a上形成，故在圖3A中的過程亦稱為晶粒上焊接(SOD；solder on die)過程。
在一些實施例中，於圖3B中，例如使用用於形成這類基板的適當的技術來形成基板104。基板104例如包括互連組件122和互連結構126。在一些實施例中(且雖然未闡述於圖1中)，基板100可包含複數個互連墊308。例如，當部分封裝300a要用來最終裝設在基板104上時，互連結構108能被附接到互連墊308。
於圖3C中，在一些實施例中，組件124例如經由互連結構126及128被裝設到基板104上。要注意的是，能無關於相對圖3B~3C討論的操作來進行相對於圖3A所討 論的操作。
在一些實施例中，於圖3D中，圖3A之部分封裝300a被裝設到圖3C之基板104上。在範例中，將部分封裝300a裝設到圖3C之基板104上(如在圖3D中所闡述)造成了圖1的封裝100。在一些實施例中，圖3A之部分封裝300a被裝設到圖3C之基板104上，使得組件124配適於晶粒102a之凹入區域130中，且各個互連結構108被附接到對應的互連墊308。
在圖1~3D中，組件124被裝設到基板104上。在一些實施例中，基板104之至少部分亦能被凹入，並且組件124能至少部分的在基板104之凹入區域內。例如，圖4依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝400的剖面視圖(此後亦稱為「封裝400」)，其中該堆疊的複數個晶粒之第一晶粒和基板被選擇性地凹入以容納組件124。封裝400類似於圖1之封裝100，因而類似的組件被類似地標記。然而，不似圖1，除了在晶粒102a中的凹入區域130’以外，另一凹入區域430係例如在組件124要被裝設於其中的基板104上形成。組件124配適於兩個凹入區域130’和430內。在一些範例中，因為凹入的區域430提供一些空間給予組件124，故封裝400之凹入區域130’相較於封裝100之凹入區域130可以是相對的小。
封裝100之幾個其它的變化亦為可能的。例如，在圖1之封裝100的組件124被裝設到基板124上並且電連接到基板124。然而，在其它實施例中，組件124能電連 接至及/或裝設於晶粒102a上。例如，圖5A依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝500(從此之後亦稱為「封裝500」)的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來容納電耦接至該第一晶粒的組件124。封裝500包含至少部分類似於圖1之封裝100的組件的組件，因而在圖1及5中的該些組件使用類似的標號來標示。然而，不似封裝100，在封裝500中，組件124被裝設到且附接到晶粒102a。組件124被裝設到凹入區域130內。例如，使用互連結構126及128裝設組件124到晶粒102a上。
在一些實施例中，於封裝500中，互連墊501係形成於凹入區域130之頂部表面中，而互連結構128被附接到互連墊501。在一些實施例中，為了促進組件124與封裝500之其它組件之間的電連接，通過晶粒102a的TSV 118’被連接到互連墊501。
圖5B依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒和基板被選擇性地凹入來容納電耦接至該第一晶粒的組件。在圖5B中闡述的封裝500b實質上類似於圖5A的封裝500。然而，在圖5B中，除了凹入區域130以外，另一凹入區域530係形成於基板104中(例如，類似於圖4之凹入區域430)。組件124至少配置於兩個凹入區域130和530內。圖5B鑒於圖5A來看是不言自明的，因而於此將不會進一步詳細地討論。
圖6依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝600(此後亦稱為「封裝600」)的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來容納電耦接至該第一晶粒及至該基板的組件124。封裝600包含至少部分類似於圖1之封裝100的組件的組件，因而在圖1及6中的該些組件使用類似的標號來標示。在一些實施例中，不似封裝100，於封裝500中，組件124被附接到晶粒102a和基板104。組件124被裝設到凹入區域130內。組件124係例如使用互連結構126’和128’在晶粒102a上電連接且例如使用互連結構126”和128”在基板104上電連接。
僅為範例的是，組件124可包含電容器，並且電容器124之一端能電耦接至晶粒102a，而另一端至基板104。又在另一範例中，組件124為電壓調節器，而該電壓調節器供應電壓給晶粒102a和基板104兩者(例如經由在圖6中所闡述分別的連接)。
圖7A依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝700(此後亦稱為「封裝700」)的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒(例如，晶粒102a)被選擇性地凹入來容納第一組件124，且其中第二組件配置在該第一晶粒之未凹入區域與該基板之間。封裝700包含至少部分類似於圖1之封裝100的組件的組件，因而在圖1及7A中的該些組件使用類似的標號來標示。在一些實施例中，除了組件124以外，另一組件724被附接到晶 粒102a之底部表面S1b(例如，在晶粒102a與基板104之間的空間中)。組件724係例如經由互連結構706及708和互連墊710裝設在晶粒102a上。互連結構706例如為凸塊、凸塊墊、金屬柱(例如，銅柱)、使用金屬、合金、可焊的材料形成的球或類似者，並且被附接到晶粒102a的底部表面。互連結構708例如為使用金屬、合金、可焊的材料或類似者形成的焊接並且將互連結構706附接到晶粒102a。組件724例如包含任何主動及/或被動組件，例如電容器、電感器、電阻器、時脈產生器、電壓調節器等。雖然未在圖7A中闡述，在一些實施例中，組件724能使用ACF、ACP及/或任何基於互連的接著被附接到晶粒102a(例如，取代互連結構706及708)。
圖7B依據一些實施例闡述包含堆疊的複數個晶粒之半導體封裝的剖面視圖，其中該堆疊的複數個晶粒之第一晶粒被選擇性地凹入來容納第一組件，且其中第二組件配置在該第一晶粒之未凹入的區域與該基板之間且附接至該基板。在圖7B中闡述的封裝700b實質上類似於圖7A的封裝700。然而，在圖7B中，組件724例如使用互連結構706’和708’以及互連墊710’被附接到基板104。圖7B鑒於圖7A來看是不言自明的，因而於此將不會進一步詳細地討論。
雖然圖7A~7B闡述組件724被附接至晶粒102a或基板104其一者，但在一些實施例中(且雖然未在圖中闡述)，組件724能例如經由分別的互連結構被附接至晶粒 102a與基板104兩者。
圖8依據一些實施例闡述描繪用於將組件(例如，圖1之組件124)配置到晶粒之凹入區域中(例如，圖1之晶粒102a的凹入區域130中)的方法800之流程圖，其中該晶粒為堆疊的多個晶粒之一部分(例如，晶粒102a、102b、102c)。在804處，形成晶粒，例如如相對圖2A~2B所討論的。在808處，移除晶粒之部分以在晶粒中形成凹入區域，如相對圖2C所討論的。
在812處，形成基板(例如，圖1的基板104)，如相對圖2E所討論的。在一些實施例中，能在不具有任何凹入區域下形成基板，如相對圖1所討論的。在一些實施例中，能在具有凹入區域下(例如，凹入區域530)形成基板，如相對圖5B所討論的。
在816處，組件被裝設在基板上，如相對圖2F所討論的。在820處，晶粒被裝設在基板上，如相對圖2G所討論的。在一些實施例中，裝設晶粒以使得組件至少部分被配置在晶粒中的凹入區域內。在其中基板亦具有凹入區域的一些實施例中，裝設晶粒以使得組件至少部分被配置在基板中的凹入區域內，例如如在圖5B中所闡述的。
雖然圖8以特定次序闡述方法800的各種操作，但也能以不同的次序進行操作。僅為範例的是，如在方塊812及816中所討論的，能至少部分並行於或先前於相對方法800之方塊804及808所討論的操作來進行基板之形成和將組件裝設到基板上。在圖8中所列舉的方塊及/或操 作之一些者依據某些實施例是可選的。將呈現的方塊編號是為了闡明的緣故且並不打算以各種方塊必需發生的操作之次序來規範。
圖9依據一些實施例闡述計算裝置2100、智慧裝置、計算裝置或電腦系統或SoC(晶片上系統)2100，在其中第二晶粒以覆晶晶片組態堆疊於第一晶粒上，其中該第一晶粒之非有效側被凹入且組件係配置至少部分在該第一晶粒中的凹入區域上。要指出的是，具有與任何其它圖之元件相同參考號碼(或名稱)的圖9之該些元件能以類似於所說明之該者的任何方式來操作或作用，但不限於如此。
於此，形成計算裝置2100的各種方塊可被封裝為具有組件被配置於其中之至少一凹入區域的堆疊的晶粒，例如如相對圖1~7所討論的以及如在本揭露中所討論的。於此，能例如以在圖1~7之一或多個中闡述的封裝之一或多個來封裝形成計算裝置2100的一或多個方塊。
在一些實施例中，計算裝置2100代表適當的計算裝置，像是計算平板、行動電話或智慧電話、膝上型電腦、桌上型電腦、IOT裝置、伺服器、機上盒、無線致能電子書閱讀器(e-reader)或類似者。將了解的是，概括地繪示某些組件，而非這類裝置之所有組件被繪示於計算裝置2100中。
在一些實施例中，計算裝置2100包括第一處理器2110。本揭露之各種實施例亦可包含在2170內像是無 線介面的網路介面，使得系統實施例可被納入到例如巢蜂式電話或個人數位助理的無線裝置中。
在一實施例中，處理器2110能包括一或多個實體裝置，像是微處理器、應用處理器、微控制器、可編程邏輯裝置或其它處理單元。由處理器2110所進行的處理操作包括應用及/或裝置功能執行於其上的作業平台或作業系統之執行。處理操作包括關於與人類使用者或與其它裝置的I/O(輸入/輸出)之操作、關於電源管理的操作及/或關於將計算裝置2100連接到另一裝置的操作。處理操作亦可包括關於音頻I/O及/或顯示I/O的操作。
在一實施例中，計算裝置2100包括音頻子系統2120，其代表與提供音頻功能給計算裝置關聯的硬體(例如，音頻硬體及音頻電路)和軟體(例如，驅動器編牽碼器)組件。音頻功能可以包括揚聲器及/或耳機輸出以及麥克風輸入。用於這類功能的裝置能被整合到計算裝置2100中或被連接到計算裝置2100。在一實施例中，使用者藉由提供由處理器2110接收的及處理的音頻命令來與計算裝置2100互動。
顯示子系統2130代表硬體(例如，顯示裝置)及軟體(例如，驅動程式(driver))組件，其提供視覺及/或觸覺顯示器以用於使用者來與計算裝置2100互動。顯示子系統2130包括顯示介面2132，其包括使用以提供顯示給使用者的特別螢幕或硬體裝置。在一實施例中，顯示介面2132包括自處理器2110分離的邏輯，用以進行關於顯示器的至 少一些處理。在一實施例中，顯示子系統2130包括觸控螢幕(或觸控板(touch pad))裝置，其提供輸出及輸入兩者給使用者。
I/O控制器2140代表關於與使用者互動的硬體裝置和軟體組件。I/O控制器2140可操作以管理作為音頻子系統2120及/或顯示子系統2130之一部分的硬體。此外，I/O控制器2140闡述用於額外裝置的連接點，其連接到計算裝置2100，使用者透過該計算裝置可與系統互動。例如，能被附接到計算裝置2100的裝置可包括麥克風裝置、揚聲器或立體聲系統、視頻系統或其它顯示裝置、鍵盤或鍵板裝置或用於以像是讀卡機(card reader)或其它裝置的特定應用來使用的其它I/O裝置。
如上所提及的，I/O控制器2140能與音頻子系統2120及/或顯示子系統2130來互動。例如，透過麥克風或其它音頻裝置的輸入能提供用於計算裝置2100之一或多個應用或功能的輸入或命令。此外，能取代顯示輸出或除了顯示輸出以外提供音頻輸出。在另一範例中，若顯示子系統2130包括觸控螢幕，則顯示裝置亦作為輸入裝置，其能至少部分地由I/O控制器2140來管理。在計算裝置2100上亦能有額外的按鈕或開關，用以提供由I/O控制器2140管理的I/O功能。
在一實施例中，I/O控制器2140管理像是加速度計、攝像機、光感測器或其它環境感測器的裝置，或是能被包括在計算裝置2100中的其它硬體。輸入能為一部分 的直接使用者互動以及提供環境輸入給系統用以影響其操作(像是對於噪音過濾、針對亮度偵測調整顯示器、施用用於攝像機的閃光或其它特徵)。
在一實施例中，計算裝置2100包括電源管理2150，其管理電池功率使用、電池之充電及關於電源節約操作的特徵。記憶體子系統2160包括記憶體裝置以用於儲存在計算裝置2100中的資訊。記憶體能包括非揮發性(若對記憶體裝置的電力中斷，狀態不會改變)及/或揮發性(若對記憶體裝置的電力中斷，狀態為未定的)記憶體裝置。記憶體子系統2160能儲存關於執行計算裝置2100之應用及功能的應用資料、使用者資料、音樂、相片、文件或其它資料以及系統資料(無論長期或暫時)。
實施例之元件亦被提供為機器可讀媒體(例如，記憶體2160)以用於儲存電腦可執行指令(例如，用以實施於此討論的任何其它過程的指令)。機器可讀媒體(例如，記憶體2160)可包括(但不限於)快閃記憶體、光碟、CD-ROM、DVD ROM、RAM、EPROM、EEPROM、磁或光卡、相變記憶體(PCM；phase change memory)或合適於儲存電子或電腦可執行指令的其它類型機器可讀媒體。例如，本揭露之實施例可被下載為電腦程式(例如，BIOS)，其可藉由經由通訊鏈結(例如，數據機或網路連接)的資訊信號之方式從遠端電腦(例如，伺服器)轉移到請求的電腦(例如，客戶端)。
通訊連結(Connectivity)2170包括用以致能計 算裝置2100來與外部裝置通訊的硬體裝置(例如，無線及/或有線的連接器和通訊硬體)和軟體組件(例如，驅動程式、協定堆疊(protocol stack))。通訊裝置2100可以為分開的裝置，像是其它計算裝置、無線存取點或基地台以及像是耳麥組(headset)、印表機或其它裝置的周邊設備。
通訊連結2170能包括多個不同類型的通訊連結。概括而言，計算裝置2100係闡述具有蜂巢式通訊連結2172和無線通訊連結2174。蜂巢式通訊連結2172一般指的是由無線載波提供的蜂巢式網路通訊連結，像是經由GSM(用於行動通訊的全球系統)或變化或衍生、CDMA(分碼多重存取)或變化或衍生、TDM(分時多工)或變化或衍生或其它蜂巢式服務標準所提供。無線通訊連結(或無線介面)2174指的是非蜂巢式的無線通訊連結，且能包括個人區域網路(像是藍牙、近場(Near Field)等)、局部區域網路(像是WiFi)及/或廣域網路(像是WiMax)或其它無線通訊。
周邊連接2180包括硬體介面和連接器以及軟體組件(例如，驅動程式、協定堆疊)，用以作成周邊連接。將了解的是，計算裝置2100可以為到其它計算裝置(「到」2182)以及讓周邊裝置(「自」2184)連接到其的周邊裝置。計算裝置2100常具有「對接(docking)」連接器，用以連接到其它計算裝置，以為了像是管理(例如，下載及/或上載、改變、同步)在計算裝置2100上的內容。此外，對接連接器能允許計算裝置2100連接到允許計算裝置2100控制內容輸出的某些周邊，例如連接到視聽 (audiovisual)或其它系統。
除了專屬對接連接器或其它專屬連接硬體以外，計算裝置2100能經由普通或基於標準的連接器作成周邊連接2180。普通類型能包括通用串列匯流排(USB；Universal Serial Bus)連接器(其能包括若干個不同硬體介面之任一者)、包括迷你顯示埠(MDP；MiniDisplayPort)的顯示埠(DisplayPort)、高解析度多媒體介面(HDMI；High Definition Multimedia Interface)、火線(Firewire)或其它類型。
在一些實施例中，SOC 2100包括感測器2190(例如，溫度感測器、加速度計、陀螺儀等)。在一些實施例中，SOC 2100包括一或多個MEMs 2200(微機電系統)。
在說明書中參考「實施例」、「一實施例」、「一些實施例」或「其它實施例」意味連同實施例說明的特別特徵、結構或特性被包括在至少一些實施例中，但不必然在所有實施例中。「實施例」、「一實施例」或「一些實施例」之各方面的出現並不必然全指的是相同的實施例。若說明書述及組件、特徵、結構或特性「可(may)」、「可能(might)」或「可以(could)」被包括，則該特別組件、特徵、結構或特性並不要求要被包括。若說明書或申請專利範圍指的是「一種」或「一」元件，其並不意味有該些元件其中僅一者。若說明書或申請專利範圍指的是「額外的」元件，其並未排除有多於一個 該額外元件。
進一步而言，特別特徵、結構、功能、或特性可在一或多個實施例中以任何合適的方式來結合。例如，第一實施例可與第二實施例結合於在與兩個實施例關聯的特別特徵、結構、功能或特性不互斥的任何處。
在當本揭露已連同其特定實施例說明的同時，按照前述說明，這類實施例的許多替代、修飾及變化將對本領域具有通常知識之該些者為顯見的。本揭露之實施例打算要包含所有這類替代、修飾及變化以致落入所附的申請專利範圍的寬闊範圍。
此外，對積體電路(IC)晶片及其它組件的周知的電源/接地連接可或不可繪示於提出的圖內，以為了闡述及討論的簡化，且以致不會模糊本揭露。進一步，可以方塊圖形式繪示佈設以為了避免模糊本揭露，且亦鑒於相對於實施這類方塊圖佈設的特異性高度取決於本揭露要被實施於其內的平台的事實(亦即，這樣的特異性應恰當的在本領域具有通常知識者的見識內)。在當提出特定細節(例如，電路)以為了說明本揭露之範例實施例下，對本領域具有通常知識者應顯見的是，本揭露能在不具有或具有這些特定細節下被實踐。因此，本發明說明要被視為闡述性的而非限制的。
下列條項屬於進一步實施例。在範例款項中的特異性可在一或多個實施例中任何處被使用。於此說明的設備之所有可選的特微亦可相對於方法或過程來實施。
條項1.一種設備包含：基板；具有第一側和第二側的晶粒，其中該晶粒被裝設在該基板上使得該晶粒之該第一側面對該基板，且其中該晶粒之該第一側的至少部分被移除以在該晶粒中形成凹入部；以及組件，其中該組件的至少一部分被配置在該第一晶粒中的該凹入部中。
條項2.如條項1所述的設備，其中該組件被裝設在該基板上且被電耦接至該基板。
條項3.如條項1所述的設備，其中該組件被裝設在該晶粒上且被電耦接至該晶粒。
條項4.如條項1~3之任一項所述的設備，其中該組件(i)透過第一互連結構被電耦接至該晶粒以及(ii)透過第二互連結構被電耦接至該基板。
條項5.如條項1~3之任一項所述的設備，其中該晶粒之該第一側為該晶粒的非有效側，且其中該晶粒的該第二側為該晶粒的有效側。
條項6.如條項1~3之任一項所述的設備，其中該晶粒為第一晶粒，且其中該設備更包含：裝設在該第一晶粒之該第二側上的第二晶粒。
條項7.如條項6所述的設備，更包含：裝設在該第一晶粒之該第二側上的第三晶粒。
條項8.如條項6~7之任一項所述的設備，更包含：在該第一晶粒中形成的直通矽穿孔(TSV)，其中該第二晶粒透過在該第一晶粒中形成的該TSV電耦接至該 基板。
條項9.如條項1~8之任一項所述的設備，其中該組件為第一組件，且其中該設備更包含：第二組件，其中晶粒之該第一側的至少另一部分為未凹入的，且其中該第二組件被附接到該晶粒之該第一側的該至少另一部分，使得該第二組件在該晶粒與該基板之間。
條項10.一種半導體封裝，包含：如條項1~9之任一項所述的設備；以及至少部分囊封該晶粒的模製複合物。
條項11.一種半導體封裝，包含：基板；裝設在該基板上的複數個晶粒，該複數個晶粒包含裝設在該基板上的第一晶粒；在該第一晶粒中形成的凹入區域；以及至少部分配置在該凹入區域內的組件。
條項12.如條項11所述的半導體封裝，其中：該組件經由一或多個互連結構電耦接至該基板。
條項13.如條項11所述的半導體封裝，其中：該組件經由一或多個互連結構電耦接至該第一晶粒。
條項14.如條項11~13之任一項所述的半導體封裝，更包含：至少部分囊封該複數個晶粒的模製複合物。
條項15.如條項11~14之任一項所述的半導體封裝，其中：該凹入區域形成於該第一晶粒之非有效側中。
條項16.如條項15所述的半導體封裝，其 中：該複數個晶粒包含裝設在該第一晶粒之有效側上的第二晶粒。
條項17.如條項11~16之任一項所述的半導體封裝，其中該組件為第一組件，且其中該半導體封裝更包含：配置在該第一晶粒之未凹入區域與該基板之間的第二組件。
條項18.一種方法，包含：形成第一晶粒；移除該第一晶粒之部分以在該第一晶粒中形成凹入區域；形成基板；將組件裝設到該基板上；以及將該第一晶粒裝設在該基板上使得該組件至少部分被配置在該第一晶粒中的該凹入區域內。
條項19.如條項18所述的方法，其中該凹入區域形成在該第一晶粒之第一側上，且其中該方法更包含：以覆晶晶片組態將第二晶粒裝設到該第一晶粒的第二側上。
條項20.如條項19所述的方法，其中該第一晶粒之該第一側為該第一晶粒的非有效側，且其中該第一晶粒的該第二側為該第一晶粒的有效側。
條項21.如條項19~20之任一項所述的方法，更包含：在該第一晶粒中形成的直通矽穿孔(TSV)，以及透過該TSV將該第二晶粒電耦接到該基板。
條項22.如條項18~21之任一項所述的方法，更包含：將另一組件附接到該第一晶粒之未凹入區域，使得該另一組件在該第一晶粒與該基板之間。
條項23.如條項18~21之任一項所述的方法，更包含：透過第一互連結構將該組件電耦接至該第一晶粒。
條項24.如條項23所述的方法，更包含：透過第二互連結構將該組件電耦接至該基板。
條項25.一種設備，包含：用於進行如條項18~24之任一項所述的方法的機構。
條項26.一種設備，包含：用於形成第一晶粒的機構；用於移除該第一晶粒之部分以在該第一晶粒中形成凹入區域的機構；用於形成基板的機構；用於將組件裝設到該基板上的機構；以及用於將該第一晶粒裝設到該基板上使得該組件至少部分被配置在該第一晶粒中的該凹入區域內的機構。
條項27.如條項26所述的設備，其中該凹入區域形成在該第一晶粒之第一側上，且其中該設備更包含：用於以覆晶晶片組態將第二晶粒裝設到該第一晶粒的第二側上的機構。
條項28.如條項27所述的設備，其中該第一晶粒之該第一側為該第一晶粒的非有效側，且其中該第一晶粒的該第二側為該第一晶粒的有效側。
條項29.如條項27~28之任一項所述的設備，更包含：用於在該第一晶粒中形成直通矽穿孔(TSV)的機構；以及用於透過該TSV將該第二晶粒電耦接到該基板的機構。
條項30.如條項26~30之任一項所述的設備，更包含：用於將另一組件附接到該第一晶粒之未凹入區域使得該另一組件在該第一晶粒與該基板之間的機構。
條項31.如條項26~31之任一項所述的設備，更包含：用於透過第一互連結構將該組件電耦接至該第一晶粒的機構。
條項32.如條項31所述的設備，更包含：用於透過第二互連結構將該組件電耦接至該基板的機構。
提供摘要，其將允許讀者確定本技術揭露的本質及要旨。具理解的提出摘要而其將不會被使用來限定申請專利範圍之範圍或意義。下列申請專利範圍係以各自獨立的請求項作為分開的實施例特此併入詳細的發明說明中。
100:半導體封裝
102a:晶粒
102b:晶粒
102c:晶粒
104:基板
106:互連結構
108:互連結構
S1a:晶粒102a之頂部表面
S1b:晶粒102a之底部表面
110:互連結構
112:互連結構
114:互連結構
116:互連結構
118:直通矽穿孔
120:模製複合物
122:互連組件
124:組件
126:互連結構
128:互連結構
130:凹入區域

Claims (16)

  1. 一種用於半導體封裝的設備，包含：基板；耦接至該基板的中介層，該中介層包含第一側和第二側，其中該第一側相鄰該基板，且其中該中介層之該第一側的部分包含在該中介層中的凹入部，用以界定第一表面的凹入的部分和在該凹入部外側該第一表面的未凹入的部分；以及組件，其中該組件的至少一部分在該凹入部內，且其中該中介層包含第一中介層通孔，其從該中介層之第一互連組件延伸到該第一表面的該凹入的部分，以及包含第二中介層通孔，其從該第一互連組件或與該第一互連組件實質共面的第二互連組件延伸到該第一表面的該未凹入的部分。
  2. 如申請專利範圍第1項所述的設備，其中該組件被裝設在該基板上且被電耦接至該基板。
  3. 如申請專利範圍第1項所述的設備，其中該第一中介層通孔具有第一垂直長度，其比該第二中介層通孔之第二垂直長度還短。
  4. 如申請專利範圍第1項所述的設備，其中該組件：透 過第一互連結構被電耦接至該中介層；以及透過第二互連結構被電耦接至該基板。
  5. 如申請專利範圍第1項所述的設備，其中該中介層之該第一側包含該中介層的非有效側，且其中該中介層的該第二側包含該中介層的有效側。
  6. 如申請專利範圍第1項的設備，更包含：在該中介層之該第二側上的晶粒。
  7. 如申請專利範圍第6項的設備，更包含：在該中介層之該第二側上的第二晶粒。
  8. 如申請專利範圍第6項的設備，其中該晶粒透過該第二中介層通孔電耦接至該基板。
  9. 如申請專利範圍第1項的設備，其中該組件為第一組件，且其中該設備更包含：第二組件，其耦接到該中介層之該第一側的該未凹入的部分，使得該第二組件在該中介層與該基板之間。
  10. 一種半導體封裝，包含：基板；在該基板上的複數個晶粒，該複數個晶粒包含在該基 板上的第一晶粒；在該第一晶粒中的凹入區域；以及至少部分配置在該凹入區域內的組件，其中該第一晶粒包含第一矽通孔，其從該第一晶粒之第一互連組件延伸到第一表面該凹入區域，且包含第二中介層通孔，其從該第一互連組件或與該第一互連組件實質共面的第二互連組件延伸到該第一晶粒之未凹入區域。
  11. 如申請專利範圍第10項所述的半導體封裝，其中：該組件經由一或多個互連結構被電耦接至該基板，其包含該第一互連結構。
  12. 如申請專利範圍第10項所述的半導體封裝，其中：該組件經由一或多個互連結構被電耦接至該第一晶粒，其包含該第二互連結構。
  13. 如申請專利範圍第10項所述的半導體封裝，更包含：至少部分地囊封該複數個晶粒的複合物。
  14. 如申請專利範圍第10項所述的半導體封裝，其中：該凹入區域係在該第一晶粒之非有效側中。
  15. 如申請專利範圍第14項所述的半導體封裝，其中：該複數個晶粒包含在該第一晶粒之有效側上的第二晶 粒。
  16. 如申請專利範圍第14項所述的半導體封裝，其中該組件為第一組件，且其中該半導體封裝更包含：在該第一晶粒之該未凹入區域與該基板之間的第二組件。
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