TW201413872A - 封裝元件與其製法 - Google Patents

封裝元件與其製法 Download PDF

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Publication number
TW201413872A
TW201413872A TW102129621A TW102129621A TW201413872A TW 201413872 A TW201413872 A TW 201413872A TW 102129621 A TW102129621 A TW 102129621A TW 102129621 A TW102129621 A TW 102129621A TW 201413872 A TW201413872 A TW 201413872A
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Taiwan
Prior art keywords
substrate
package
vias
conductive
interposer
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TW102129621A
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English (en)
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TWI499002B (zh
Inventor
Shih-Wei Liang
Kai-Chiang Wu
Ming-Che Ho
Yi-Wen Wu
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201413872A publication Critical patent/TW201413872A/zh
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Publication of TWI499002B publication Critical patent/TWI499002B/zh

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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

本發明提供一種封裝元件，包括：一中介層基板；複數個基板通孔配置於該中介層基板中，其中該中介層基板凹蝕至低於該些基板通孔的頂部表面；以及一導電球耦合到每一個該些基板通孔。

Description

封裝元件與其製法
本發明係有關於一種半導體元件，且特別是有關於一種封裝元件與其製法。
半導體元件應用於各種電子產品，例如個人電腦、手機、數位相機以及其他電子設備。半導體元件的製造通常藉由在一半導體基板上連續地沉積絕緣材料或介電材料層、導電材料層以及半導體材料層，接著利用微影製程對上述各個材料層進行圖案化，藉以形成電路元件或組件。
藉由持續降低最小特徵尺寸(minimum faeature size)，半導體工業持續改善各種電子組件(例如電晶體、二極體、電阻、電容等等)的集積密度(integration density)，如此一來可使更多元件整合於一特定區域中。在一些應用中，這些尺寸較小的電子組件也僅需要使用較小型封裝即可，其中這些較小型封裝所需使用的區域較傳統的封裝更小。
就半導體元件的應用而言，近來所發展的一種較小型封裝技術為封裝層疊(package on package,PoP)，在一個單一封裝層疊(package on package)元件中，兩個或多個積體電路晶粒分別進行封裝，再將已完成封裝的積體電路晶粒接合在一 起。
本發明提供一種封裝元件之製法，包括以下步驟：形成複數個基板通孔(through-substrate vias,TSVs)於一中介層基板之中；凹蝕(recessing)該中介層基板或增加該些基板通孔之厚度，藉以暴露出該些複數個基板通孔的部份；以及耦合一導電球到每一個該些基板通孔的該暴露部份。
本發明另提供一種封裝元件，包括：一中介層基板；複數個基板通孔配置於該中介層基板中，其中該中介層基板凹蝕至低於該些基板通孔的頂部表面；以及一導電球耦合到每一個該些基板通孔。
本發明亦提供一種封裝元件之製法，包括以下步驟：提供一封裝基板，其中該封裝基板包括一中介層基板及複數個基板通孔配置於該中介層基板中；凹蝕該中介層基板或增加該些基板通孔之厚度，以暴露出該些基板通孔的部份；形成一晶種層於該些基板通孔的該些暴露部份之上；以及耦合一焊料球到位於每一個該些基板通孔的該暴露部份之上的該晶種層。
100‧‧‧封裝元件
102‧‧‧中介層基板
104‧‧‧基板通孔(TSV)
106‧‧‧中介層基板之第一側
108‧‧‧中介層基板之第二側
110‧‧‧重新分配層(RDL)
112‧‧‧線路
114‧‧‧絕緣材料
116‧‧‧第一導電材料
118‧‧‧第二導電材料
120‧‧‧接觸插塞
122‧‧‧暴露部份
123‧‧‧基板通孔之頂部表面
d1‧‧‧暴露部份向上突出延伸之尺寸(厚度)
126‧‧‧晶種層之第一層
128‧‧‧晶種層之第二層
130‧‧‧晶種層
140‧‧‧導電球
150‧‧‧模版材料
152‧‧‧導電膠
d2‧‧‧模版材料與導電膠之尺寸(厚度)
130’‧‧‧晶種層
160‧‧‧封裝元件之製造方法流程圖
162‧‧‧形成複數個基板通孔(TSVs)於中介層基板之中
164‧‧‧凹蝕中介層基板以暴露出基板通孔(TSVs)的部份
166‧‧‧耦合焊料到基板通孔(TSVs)的暴露部份
170‧‧‧導電凸塊
172‧‧‧積體電路晶粒
172a‧‧‧積體電路
172b‧‧‧積體電路晶粒
172c‧‧‧積體電路晶粒
174‧‧‧接觸插塞
176‧‧‧封裝半導體元件
178‧‧‧封裝半導體元件
180‧‧‧接觸插塞
182‧‧‧封裝
184‧‧‧焊料接點
186‧‧‧模造成型化合物
188‧‧‧基板通孔
192a‧‧‧第一重新分配層
192b‧‧‧第二重新分配層
194a‧‧‧線路接合
194b‧‧‧線路接合
196‧‧‧模造成型化合物
198‧‧‧封裝體層疊(package-on-package,PoP)元件
第1~6圖顯示封裝元件在不同製程階段的剖面圖，用以說明製造封裝元件的方法。
第7圖顯示封裝元件100之剖面圖，用以說明封裝元件之製造方法。
第8~10圖顯示封裝元件在不同製程階段的剖面圖，用以說明製造封裝元件的方法。
第11圖顯示流程圖，用以說明封裝元件的製造方法。
第12~13圖顯示剖面圖，用以說明接合積體電路晶至封裝元件的方法。
第14~15圖顯示剖面圖，用以說明利用本發明封裝元件製造封裝體層疊(package-on-package,PoP)元件的方法。
本發明所揭露之實施例係有關於應用於半導體元件的封裝元件與方法。本發明將描述新穎的封裝方法、封裝元件以及接合焊料球至封裝基板的方法。
依據本發明之部份實施例，第1圖到第6圖為封裝元件100在不同製程階段的剖面圖，用以說明製造封裝元件100的方法。
封裝元件100的製造方法包括，首先提供中介層基板(interposer substrate)102。需注意的是，在每一圖中僅包括一個封裝元件100，然而，複數個封裝元件100同時形成於一個中介層基板102的表面上，在之後的製程中，封裝元件100將個別被分割而分離。
如第1圖所示，中介層基板102包括複數個基板通孔(through-substrate vias,TSVs)104形成於其中。基板通孔104具有導電性，並且提供自中介層基板102之第一側106到中介層基板102之第二側108的電性連接，其中第二側108與第一側106分別位於中介層基板102相對的兩側。基板通孔104提供封裝元 件100垂直的連接。舉例而言，中介層基板102可包括矽或其他半導體材料。此外，中介層基板102亦可包括其他材料。
可藉由圖案化或鑽出複數個完全穿過中介層基板102的孔洞或縫隙，再填充導電材料於這些孔洞中，以形成基板通孔104。舉例而言，在本發明之部份實施例中，在中介層基板102的一側上形成未完全穿過基板的孔洞，填充導電材料於這些孔洞中，對中介層基板102的另一側進行薄化至到達基板通孔104為止，藉以使基板通孔104延伸而完全穿過中介層基板102。此外，亦可利用其他方法形成基板通孔104於中介層基板102中。
在本發明之部份實施例中，基板通孔104可包括一種或多種的襯層(liner)以及一填充材料(fill material)(未顯示於圖中)。舉例而言，基板通孔104可包括一種或多種的襯層，其中這些襯層可包括鉭(Ta)、氮化鉭(TaN)、鈦(Ti)、氮化鈦(TiN)、其他材料或上述材料之組合或多層結構。在本發明之部份實施例中，襯層可包括鉭/氮化鉭(Ta/TaN)或鈦/氮化鈦(Ti/TiN)的雙層結構。舉例而言，基板通孔104可包括填充材料沉積於襯層之上，其中填充材料可包括銅(Cu)。此外，基板通孔104可包括其他材料且可不包含襯層。舉例而言，在本發明之部份實施例中，襯層包括絕緣材料，此絕緣材料形成於將用於形成基板通孔104之孔洞的側壁上，其中絕緣材料的形成早於襯層與填充材料的沉積或形成。在其他實施例中，絕緣襯層並未包含於中介層基板102之中。舉例而言，從中介層基板102的俯視圖觀之，基板通孔104包括一直徑介於約10-20μm，此 外，基板通孔104可包括其他尺寸。
如第2圖所示，形成重新分配層(redistribution layer,RDL)110於中介層基板102之第二側108上。重新分配層110包括線路(wiring)112配置於絕緣材料114之中。舉例而言，線路112包括複數個由導電材料所形成的圖案(trace)，其中導電材料包括銅、鋁(Al)、其他材料或上述材料之組合或多層結構。舉例而言，絕緣材料114包括二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、其他絕緣材料或上述材料之組合或多層結構。此外，線路112與絕緣材料114可包括其他材料。至少部份的線路112耦合到基板通孔104，以提供封裝元件100之第二側108電性連接。舉例而言，在本發明之部份實施例中，為提供封裝元件100電性連接，部份的線路112可包括線路之扇骨狀展開區域(fan-out region)。
重新分配層110包括複數個接觸插塞(contact)120形成於其表面上。接觸插塞120包括第一導電材料116以及第二導電材料118配置於第一導電材料116之上。在本發明之部份實施例中，第一導電材料116包括銅且第二導電材料118包括錫(Sn)。此外，接觸插塞120、第一導電材料116與第二導電材料118可包括其他材料。在部份實施例中並未包括第二導電材料118。至少部份的接觸插塞120藉由絕緣材料114耦合到重新分配層110之線路112。重新分配層110提供封裝元件100水平方向之連接。
舉例而言，重新分配層110的不同部份，亦即，重新分配層110之線路112、絕緣材料114以及接觸插塞120可使用 蝕刻技術(etch techniques)、鑲嵌技術(damascene techniques)及/或其他方法形成。
依據本發明所揭露之部份實施例，如第3圖所示，凹蝕(recessed)中介層基板102，以暴露出複數個基板通孔104的部份122。基板通孔104的部份122在此亦稱為，例如，頂部部份122與暴露部份122。舉例而言，翻轉中介層基板102以使第一側106面向上方，利用蝕刻製程移除中介層基板102之頂部表面的一部份，且暴露出基板通孔104的頂部部份122。在本發明之其他實施例中，利用化學機械研磨(chemical-mechanical polish,CMP)製程移除中介層基板102之頂部表面的一部份，且暴露出基板通孔104的頂部部份122。舉例而言，亦可利用蝕刻製程與化學機械研磨製程結合的方法，凹蝕中介層基板102，以暴露出複數個基板通孔104的頂部部份122。
在本發明之其他實施例中，可藉由增加基板通孔104的厚度，以使中介層基板102之頂部表面被凹蝕至低於基板通孔104之頂部表面。舉例而言，可利用電鍍(plating)製程增加基板通孔104的厚度。如第3圖之虛線部份所示，起初基板通孔104之頂部表面123大致上與中介層基板102之頂部表面共平面。電鍍導電材料(例如銅)於起初共平面之頂部表面123上以形成基板通孔104之頂部部份122，其中頂部部份122自中介層基板102之頂部表面向上方延伸。在電鍍製程中，導電材料僅電鍍於導電性的基板通孔104之上，並未電鍍於中介層基板102之頂部表面上。在本發明之其他實施例中，可利用沉積(deposition)製程增加基板通孔104的厚度。舉例而言，可沉積額外的導電 材料於中介層基板102的第一側106之上，接著可利用微影製程(lithography)或直接圖案化(direct patterning)製程對該導電材料進行圖案化，藉以自中介層基板102的第一側106之上移除該導電材料，遺留下導電材料於基板通孔104之上，增加基板通孔104的厚度，因而使基板通孔104的暴露部份122自中介層基板102之頂部表面向上方延伸。亦可利用沉積製程與電鍍製程結合的方法，使基板通孔104之頂部部份122暴露於中介層基板102的第一側106之上。此外，亦可利用其他方法增加基板通孔104的厚度。
舉例而言，在本發明之部份實施例中，可利用本發明所描述之一種或多種方法，增加基板通孔104的厚度，並且使中介層基板102凹蝕，藉以暴露出基板通孔104的頂部部份122。
在使中介層基板102凹蝕及/或增加複數個基板通孔104的厚度之後，基板通孔104的暴露部份122自中介層基板102之頂部表面向上方延伸達到一尺寸d1，舉例而言，其中該尺寸d1包括介於約10-20μm。舉例而言，在本發明之部份實施例中，尺寸d1包括約30μm或更小。此外，尺寸d1可包括其他數值，其數值取決於各種因子，例如特定的應用領域、導電球140(未顯示於第3圖中；請參照第5圖)所需的尺寸、或所需的平衡高度(stand-off hight)(例如，在一終端應用中，距離導電球140最終貼合之表面的高度)，以及其他因子。在本發明之部份實施例中，基板通孔104包括暴露基板通孔(exposed TSVs,eTSVs)，暴露基板通孔(eTSVs)具有突出於中介層基板102之頂 部表面達到尺寸d1的端點，其中尺寸d1包括介於約10-20μm。
如第4圖所示，接著形成一晶種層(seed layer)130於基板通孔104的暴露部份122與中介層基板102的第一側106之上。需注意的是，當晶種層130形成於基板通孔104的暴露部份122上之後，基板通孔104將不再「暴露」；換言之，基板通孔104受到晶種層130的覆蓋。然而，為使在此所討論的內容前後一致，基板通孔104的暴露部份122在接下來的文章裡依然被稱為「暴露部份122」，因為這些部份早在先前的製程步驟中已被暴露出來。
在本發明之部份實施例中，如第4圖所示，晶種層130包括兩層：第一層126以及第二層128配置於第一層126之上。舉例而言，在本發明之部份實施例中，第一層126包括1,000-3,000Å的鈦(Ti)，且第二層128包括5,000-10,000Å的銅(Cu)。此外，晶種層130的第一層126以及第二層128亦可包括其他材料與尺寸。舉例而言，晶種層130亦可包括單一材料層或三層或三層以上的材料層。在本發明之部份實施例中，可利用濺鍍(sputter)製程形成晶種層130的一層或多層126或128。亦可利用其他方法形成晶種層130。舉例而言，在本發明之部份實施例中，晶種層130大致上為順應性(conformal)地覆蓋於中介層基板102之上，並且與基板通孔104之暴露部份122的表面形狀保持一致。此外，晶種層130亦可以是非順應性(non-conformal)，並未顯示於圖中。需注意的是，為了簡化圖式，在本發明接下來的圖式中，晶種層130僅以單一層狀構造表示。
如第5圖所示，複數個導電球140形成於位於基板通孔104之暴露部份122上方的晶種層130之上。舉例而言，可利用球滴製程(ball drop process)使導電球140耦合到位於基板通孔104之暴露部份122上方的晶種層130。舉例而言，可利用直接球滴製程(direct ball drop process)，此外，亦可利用其他方法使導電球140耦合到位於基板通孔104之暴露部份122上方的晶種層130。舉例而言，在本發明之部份實施例中，導電球140包括共熔(eutectic)材料，例如焊料。在本發明中，例如在部份專利範圍中，導電球140亦稱為焊料球(solder ball)。此外，導電球140亦可包括其他材料、其他共熔材料或上述材料之多層結構或其組合。接著，提升溫度至共熔材料的共熔點，使導電球140的共熔材料迴流，藉以使導電球140接合到位於基板通孔104之暴露部份122上方的晶種層130。舉例而言，在本發明之部份實施例中，舉例而言，在本發明之部份實施例中，其中導電球140包括焊料(solder)，導電球140的焊料材料之溫度提升至一波峰溫度為約260℃。此外，迴流製程亦可包括其他溫度。
如第6圖所示，在導電球140耦合到位於基板通孔104之暴露部份122上方的晶種層130之後，從中介層基板102之頂部表面上移除晶種層130。在本發明之部份實施例中，此方法的優點在於，導電球140可作為移除晶種層130時所使用的蝕刻罩幕(etch mask)，因此不需藉由微影製程(lithography process)移除晶種層130。舉例而言，在本發明之部份實施例中，可利用蝕刻製程，在蝕刻製程中使用導電球140作為蝕刻 罩幕，蝕刻晶種層130。
在如第1圖到第6圖所示之實施例中，利用球滴製程使導電球140耦合到中介層基板102。依據本發明之其他實施例，利用導電膠(conductive paste)152形成導電球140，如第7圖所示，且如第9圖所示。
依據本發明之其他實施例，第7圖為封裝元件100之剖面圖，其顯示封裝元件100之製造方法。形成如第4圖所示的晶種層130之後，導電膠152配置於模版材料(stencil material)150之間，並且形成於晶種層130之上，如第7圖所示。舉例而言，在本發明之部份實施例中，導電膠152包括焊料膠(solder paste)。在本發明之部份實施例中，模版材料150包括高分子、鋼、鋁合金、鎂合金或上述材料之組合或多層結構。此外，模版材料150與導電膠152亦可包括其他材料。在本發明之部份實施例中，模版材料150與導電膠152包括一尺寸d2，其中該尺寸d2包括介於約60-100μm。此外，模版材料150與導電膠152之尺寸d2亦可包括其他材料或尺寸。舉例而言，模版材料150包括犧牲材料(sacrificial material)，且模版材料150適合用於控制導電膠152的形狀與圖案。
移除模版材料150，導電膠152接著進行迴流製程，以使導電膠152的共熔材料迴流並且形成導電球140位於基板通孔104的暴露部份122之上(例如，位於暴露部份122上方的晶種層130之上)，留下如第5圖所示之結構。在本發明之部份實施例中，在後續大量(lot)或批次的(batch)封裝元件100製程中，可重複使用模版材料150。此外，亦可拋棄模版材料150。 在本發明之部份實施例中，在導電膠152進行迴流製程的期間移除模版材料150。在其他實施例中，利用獨立的蝕刻製程或移除製程移除模版材料150。接著利用導電球140作為蝕刻罩幕，自中介層基板102的頂部表面之上移除晶種層130，如同前述實施例所提及，且如第6圖所示。
依據本發明之其他實施例，第8圖到第10圖為封裝元件100在不同製程階段的剖面圖，用以說明製造封裝元件100的方法。本實施例並非如同前述實施例所提及，形成毯覆式(blanket)晶種層130於中介層基板102的頂部表面之上，而是在使中介層基板102凹蝕及/或增加複數個基板通孔104的厚度之後(如第3圖所示)，於基板通孔104的暴露部份122之上電鍍一層晶種層130’，如第8圖所示。此電鍍製程可使晶種層130’的形成僅發生於基板通孔104的暴露部份122之上。晶種層130’並未完全覆蓋於中介層基板102的頂部表面之上。舉例而言，在本發明之部份實施例中，晶種層130’包括10-20μm的銅(Cu)或鎳(Ni)，此外，晶種層130’亦可包括其他尺寸與材料。舉例而言，在本發明之部份實施例中，用以形成晶種層130’的電鍍製程包括無電電鍍(electro-less plating)。此外，亦可利用其他種類的電鍍製程形成晶種層130’。
導電膠152配置於模版材料(stencil material)150之間，並且形成於晶種層130’之上，如第9圖所示。利用迴流製程使導電膠152的共熔材料迴流並形成導電球140，如第10圖所示，並且移除模版材料150。此方法的優點在於，在這些實施例中，不需要進行獨立的蝕刻製程，自中介層基板102的頂部 表面上移除多餘的晶種層130’材料。
在其他實施例中，在電鍍晶種層130’於基板通孔104的暴露部份122上之後(如第8圖所示)，利用直接球滴製程使導電球140耦合到位於基板通孔104之暴露部份122上方的晶種層130’，如第10圖所示。
依據本發明之部分實施例，第11圖為一流程圖160，用以說明封裝元件100的製造方法。在製程步驟162中，形成基板通孔104於中介層基板102之中。在製程步驟164中，凹蝕中介層基板102，以暴露出基板通孔104的部份122。在製程步驟166中，焊料球140耦合到基板通孔104的暴露部份122。
依據本發明之其他實施例，第12圖及第13圖為剖面圖，用以說明接合積體電路晶粒172至本文所述之封裝元件100的方法。請參照第1圖到第10圖，利用本文所述之方法使導電球140形成於基板通孔104之暴露部份122上之後，在每一個位於中介層基板102之第二側108上的接觸插塞120上形成導電凸塊(conductive bump)170，如第12圖所示。舉例而言，藉由覆晶製程(flip chip)形成導電凸塊170，其中導電凸塊170接合至並取自於另一晶粒，並且藉由一迴流製程接合導電凸塊170至接觸插塞120。此外，亦可利用其他方法形成導電凸塊170。舉例而言，在本發明之部份實施例中，導電凸塊170包括覆晶接合(controlled collapse chip connection,C4)凸塊。在本發明之部份實施例中，導電凸塊170包括焊料。此外，導電凸塊170亦可包括其他種類的連接與材料。
接著使積體電路晶粒172耦合到位於封裝元件100 上的導電凸塊170，以形成封裝半導體元件176，如第13圖所示。將位於積體電路晶粒172上的接觸插塞174對準位於封裝元件100上的導電凸塊170，並將積體電路晶粒172上的接觸插塞174與導電凸塊170配置在相對應的位置。舉例而言，可利用迴流製程將導電凸塊170接合到位於積體電路晶粒172上的接觸插塞174。在本發明之部份實施例中，可施加底部填充材料(underfill material)(未顯示於圖中)在介於晶粒172與封裝元件100之間的空間，例如介於導電凸塊170之間。在本發明之部份實施例中，接著可藉由將導電凸塊140接合至一基板、印刷電路板(printed circuit board,PCB)、支撐物(support)或其他目標物，使封裝半導體元件176應用於終端用途。
在本發明之部份實施例中，第14圖所示，可將封裝半導體元件176接合至另一封裝半導體元件178，以形成封裝體層疊(package-on-package,PoP)元件198，其中第14圖為封裝體層疊元件198之剖面圖，其顯示使用本文所述之封裝元件100製造封裝體層疊元件198的方法。包含本文所述之新穎的封裝元件100封裝半導體元件176包括一第一封裝半導體元件或一底部封裝半導體元件。舉例而言，可將封裝半導體元件176接合至另一封裝半導體元件178，其中封裝半導體元件178包括一第二封裝半導體元件或一頂部封裝半導體元件。封裝半導體元件176與封裝半導體元件178藉由配置於封裝半導體元件176及178周圍的複數個焊料接點(solder joints)184接合在一起。配置於封裝半導體元件176及178之間的焊料接點184的排列方式為一排或多排。如本文先前所述，底部封裝半導體元件176包括 積體電路172a接合至導電凸塊170。頂部封裝半導體元件178包括積體電路晶粒172b。頂部封裝半導體元件178的封裝182包括複數個接觸插塞180配置於其底部表面周圍之上。焊料接點184將位於頂部封裝半導體元件178之上的接觸插塞180接合至位於底部封裝半導體元件176之上的接觸插塞120。
關於使用本文所述之新穎封裝元件所製造的封裝體層疊元件198更詳細的細節顯示第15圖的剖面圖中。在形成焊料接點184之後(例如介於底部封裝半導體元件176與頂部封裝半導體元件178之間)，包含絕緣材料之模造成型化合物(molding compound)186配置於封裝元件100之上。在本發明之部份實施例中，模造成型化合物186並未包含於封裝體層疊元件198之中。
在此顯示頂部封裝半導體元件178包含兩個積體電路晶粒172b與172c的示範例，其中積體電路晶粒172b與172c垂直堆疊於封裝182之上。此外，頂部封裝半導體元件178亦可僅包含一個積體電路晶粒172b或172c。封裝182包括基板190及複數個基板通孔188形成於其中，藉此提供頂部封裝半導體元件178垂直方向的連接。封裝182包括第一重新分配層(RDL)192a位於其底部表面上，以及第二重新分配層(RDL)192b位於其頂部表面上。重新分配層(RDL)192a及192b提供頂部封裝半導體元件178水平方向的連接。積體電路晶粒172b接合至封裝182的頂部表面。線路接合(wire bond)194a耦合位於封裝182上之接合墊(bond pad)至位於積體電路晶粒172b上之接合墊(bond pad)。積體電路晶粒172c接合至積體電路晶粒172b的 頂部表面。線路接合194b耦合位於封裝182上之接合墊至位於積體電路晶粒172c上之接合墊。模造成型化合物(molding compound)196形成於積體電路晶粒172c與封裝182之暴露部份之上。舉例而言，模造成型化合物(molding compound)196包括絕緣材料，藉以保護線路接合194a與194b。
舉例而言，在本發明之部份實施例中，積體電路晶粒172b及172c係利用覆晶晶圓級封裝(flip-chip wafer level packaging,WLP)技術以及線路接合製程(wire-bonding process)封裝於頂部封裝半導體元件178的基板182之上。此外，頂部封裝半導體元件178可包括一個或多個積體電路晶粒172b或172c，其中這些積體電路晶粒172b或172c係採用其他種類型的封裝系統或配置。
在本發明所顯示及前述之實施例中，每一個導電球140耦合到複數個基板通孔104。舉例而言，在第10圖中，導電球140耦合到三個基板通孔104之暴露部份122。在其他實施例中，每一個導電球140可耦合到兩個基板通孔104之暴露部份122，或耦合到四個或更多個基板通孔104之暴露部份122，未顯示於圖中。在其他實施例中，每一個導電球140耦合到僅一個基板通孔104之一個暴露部份122，如第15圖所示。
舉例而言，在本發明之部份實施例中，所揭露之導電球140係以球柵陣列(ball grid array,BGA)的排列方式進行排列。在本發明之部份實施例中，導電球140以完全分佈(fully populated)陣列或矩陣的排列方式排列於中介層基板102之第一側106上。此外，導電球140可僅排列於中介層基板102 之中心區域，或僅排列於中介層基板102之周圍區域之一或多列，或排列於中介層基板102之中心區域與周圍區域之結合。在本發明之部份實施例中，導電球140可排列成隨機圖案(random pattern)。此外，導電球140亦可排列成其他配置方式或圖案。
本發明所揭露之實施例包括製造封裝元件100的方法，同時也包括利用此方法所製造之封裝元件100。本發明所揭露之實施例亦包括使用在本文中所述之新穎封裝元件100進行封裝的封裝半導體元件176。本發明所揭露之實施例亦包括封裝體層疊元件198，其中封裝體層疊元件198包括在本文中所述之新穎封裝元件100。本發明所揭露之實施例尚包括將導電球140耦合至封裝基板的方法。
本發明所揭露之實施例的優點包括提供新穎的封裝元件100，其中封裝元件100不需要用以在其表面上形成焊料球的凸塊下方金屬化層(under-ball metallization,UBM)結構，因此能夠大幅地降低製造成本與時間，並且提供非常低成本的封裝元件100。使用於傳統封裝系統的凸塊下方金屬化層(UBM)結構製造成本高昂，且需要昂貴的製程步驟，例如對數層材料層進行微影製程(photolithography)、沉積製程及圖案化製程。本發明所提出用以耦合導電球140到封裝元件100之基板通孔104之暴露部份122的方法，其優點在於不需要使用微影製程步驟，因此能夠降低成本。由於封裝元件100之導電球140側不需要凸塊下方金屬化層(UBM)結構，封裝元件100的厚度可以降低，因此能夠製造整體厚度減少的封裝體層疊元件198，實現 節省空間的目的。
在本發明之部份實施例中，導電球140作為移除晶種層130時所使用的蝕刻罩幕，如此一來，在封裝元件100的製造流程中也可不必使用微影製程步驟。此外，此一新穎的封裝元件100結構以及其製造方法在製造流程中是易於實施的。
依據本發明所揭露之部份實施例，本發明提供一種封裝元件之製法，包括以下步驟：形成複數個基板通孔於一中介層基板之中。此一封裝元件之製法包括凹蝕(recessing)該中介層基板或增加該些基板通孔之厚度，藉以暴露出該些基板通孔的部份。耦合一導電球到每一個該些複數個基板通孔的暴露部份。
依據本發明所揭露之部份實施例，本發明提供一種封裝元件，包括一中介層基板及複數個基板通孔配置於該中介層基板中。凹蝕中介層基板至低於該些基板通孔的頂部表面。耦合一導電球到每一個該些基板通孔。
依據本發明所揭露之部份實施例，本發明提供一種將複數個焊料球耦合至一封裝基板之方法，包括以下步驟：提供一封裝基板，其中該封裝基板包括一中介層基板及複數個基板通孔配置於該中介層基板中。此方法尚包括凹蝕該中介層基板或增加該些基板通孔之厚度，藉以暴露出該些基板通孔的部份；以及形成一晶種層於該些基板通孔的該些暴露部份之上。耦合一焊料球到位於每一個該些基板通孔的該暴露部份之上的該晶種層。
雖然本發明已以數個較佳實施例揭露如上，然其 並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧封裝元件
102‧‧‧中介層基板
104‧‧‧基板通孔(TSV)
106‧‧‧中介層基板之第一側
108‧‧‧中介層基板之第二側
110‧‧‧重新分配層(RDL)
112‧‧‧線路
114‧‧‧絕緣材料
116‧‧‧第一導電材料
118‧‧‧第二導電材料
120‧‧‧接觸插塞
122‧‧‧暴露部份
130‧‧‧晶種層
140‧‧‧導電球

Claims (10)

  1. 一種封裝元件之製法，包括以下步驟：形成複數個基板通孔(through-substrate vias,TSVs)於一中介層基板之中；凹蝕(recessing)該中介層基板或增加該些基板通孔之厚度，藉以暴露出該些複數個基板通孔的部份；以及耦合一導電球到每一個該些基板通孔的該暴露部份。
  2. 如申請專利範圍第1項所述之封裝元件之製法，其中耦合該導電球到每一個該些基板通孔的該暴露部份包括利用一球滴製程(ball drop process)使該些導電球耦合到每一個該些基板通孔的該暴露部份，及迴流該些導電球之一共熔(eutectic)材料。
  3. 如申請專利範圍第1項所述之封裝元件之製法，其中耦合該導電球到每一個該些基板通孔的該暴露部份包括形成一導電膠配置於一模版材料(stencil material)之間並且位於該中介層基板及該些基板通孔的該暴露部份之上，移除該模版材料，及迴流該導電膠之一共熔材料。
  4. 如申請專利範圍第1項所述之封裝元件之製法，其中增加該些複數個基板通孔之厚度包括下列方法：電鍍製程、沉積製程或上述之組合。
  5. 如申請專利範圍第1項所述之封裝元件之製法，其中耦合該導電球包括耦合一個該導電球到複數個基板通孔或到每一個該些複數個基板通孔。
  6. 一種封裝元件，包括： 一中介層基板；複數個基板通孔配置於該中介層基板中，其中該中介層基板凹蝕至低於該些基板通孔的頂部表面；以及一導電球耦合到每一個該些基板通孔。
  7. 如申請專利範圍第6項所述之封裝元件，其中耦合到該些基板通孔的該導電球配置於中介層基板的一第一側上，其中該封裝元件尚包括一重新分配層(redistribution layer,RDL)於該中介層基板的一第二側上，且其中該重新分配層包括複數個接觸插塞配置於該重新分配層的一表面上。
  8. 如申請專利範圍第6項所述之封裝元件，其中該些複數個基板通孔包括暴露基板通孔(exposed TSVs,eTSVs)，其中該些暴露基板通孔突出於中介層基板之頂部表面約10-20μm。
  9. 一種封裝元件之製法，包括以下步驟：提供一封裝基板，其中該封裝基板包括一中介層基板及複數個基板通孔配置於該中介層基板中；凹蝕該中介層基板或增加該些基板通孔之厚度，以暴露出該些基板通孔的部份；形成一晶種層於該些基板通孔的該些暴露部份之上；以及耦合一焊料球到位於每一個該些基板通孔的該暴露部份之上的該晶種層。
  10. 如申請專利範圍第9項所述之封裝元件之製法，其中凹蝕該中介層基板包括下列方法：一蝕刻製程、一化學機械研磨(chemical-mechanical polish,CMP)製程及上述之組合。
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US20170250129A1 (en) 2017-08-31
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US9030010B2 (en) 2015-05-12

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