TW201413913A - 半導體封裝與其形成方法 - Google Patents

半導體封裝與其形成方法 Download PDF

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Publication number
TW201413913A
TW201413913A TW102129759A TW102129759A TW201413913A TW 201413913 A TW201413913 A TW 201413913A TW 102129759 A TW102129759 A TW 102129759A TW 102129759 A TW102129759 A TW 102129759A TW 201413913 A TW201413913 A TW 201413913A
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Taiwan
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die
rewiring
interposer
package
layer
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TW102129759A
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TWI541975B (zh
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Jing-Cheng Lin
Shang-Yun Hou
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201413913A publication Critical patent/TW201413913A/zh
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Abstract

本發明提供半導體封裝與其形成方法，其包含一或多個晶粒於中介晶粒上。上述方法形成第一再佈線結構於具有多個TSV的中介晶粒上，而連接至中介晶粒的晶粒其邊緣超出中介晶粒的邊緣。此外，可形成第二再佈線結構於中介晶粒的另一表面上，且另一表面與再佈線結構形成其上的表面對向。第二再佈線結構可重新排列接合結構，使其扇出式連接中介晶粒的外部連接物。

Description

半導體封裝與其形成方法
本發明係關於半導體元件，更特別關於其封裝結構。
半導體技術持續創新，使半導體晶片/晶粒的尺寸更小，並將更多功能整合至單一半導體晶粒中。綜上所述，半導體晶粒具有更多的輸出/輸入墊封裝於更小的面積中。如此一來，半導體晶粒的封裝更加重要，也更具有挑戰性。
本發明一實施例提供之半導體封裝，包括：具有多個穿透基板通孔的中介晶粒；第一封裝晶粒；以及第一再佈線結構，形成於中介晶粒的第一表面上，其中第一再佈線結構包括第一再佈線層以實施中介晶粒的扇出式連接，且其中第一封裝晶粒接合至第一再佈線層；以及其中第一封裝晶粒的邊緣超出中介晶粒最接近第一封裝晶粒的邊緣。
本發明一實施例提供之半導體封裝，包括：具有多個穿透基板通孔的中介晶粒；封裝晶粒；第一再佈線結構形成於中介晶粒的第一表面上，其中再佈線結構包括第一再佈線層以實施中介晶粒的扇出式連接，其中封裝晶粒接合至第一再佈線層，且其中封裝晶粒之邊緣超出中介晶粒最接近封裝晶粒 的邊緣；以及具有第二再佈線層之第二再佈線結構，覆蓋中介晶粒的第二表面，使中介晶粒扇出式連接外部連接物。
本發明一實施例提供之形成半導體封裝的方法，包括：提供第一載板，具有第一黏著層於其上；將具有多個穿透基板通孔之中介晶粒置於第一黏著層上，其中中介晶粒的第一表面具有多個連接結構並面向第一黏著層，且連接結構被保護層包圍；形成第一成型化合物於中介晶粒上；移除部份第一成型化合物與部份中介晶粒的基板，以露出穿透基板通孔；形成第一再佈線結構於中介晶粒之第二表面所露出的穿透基板通孔上，其中中介晶粒的第二表面與第一表面對向；形成多個凸塊結構於第一再佈線結構上；以及將封裝晶粒接合至第一再佈線結構上的凸塊結構，以形成封裝結構。
H1、H2‧‧‧寬度
T1、T1’、T2、T3、T4、T5‧‧‧厚度
100、100*、100’‧‧‧封裝
101‧‧‧基板
120A、120A*、120B、130‧‧‧半導體晶粒
125A、125A*、125B‧‧‧接合結構
131‧‧‧TSV
132‧‧‧再佈線結構
133‧‧‧內連線結構
134‧‧‧連接結構
135‧‧‧外部連接物
136、159、160‧‧‧金屬柱
137‧‧‧金屬墊
138‧‧‧凸塊結構
139‧‧‧表面
141、142‧‧‧成型化合物
143、143A、143B、154、156、157、158‧‧‧介電層
151、153、155‧‧‧金屬層
144‧‧‧底填物
145‧‧‧保護層
147、147’、147”‧‧‧凸塊下金屬化層
152‧‧‧通孔
154‧‧‧再佈線層
161‧‧‧接合焊料層
162‧‧‧再佈線層
301、303‧‧‧載板
302、304‧‧‧黏著層
305‧‧‧切割帶
第1A至1C圖係某些實施例中，封裝的剖視圖。
第2圖係某些實施例中，晶粒的剖視圖。
第3A至3J圖係某些實施例中，形成晶粒封裝的製程剖視圖。
第3K至3N圖係某些實施例中，形成內連線結構於封裝結構之連接結構上的製程剖視圖。
第4圖係某些實施例中，封裝的部份剖視圖。
下述內容為製作與使用本發明的實施例。可以理解的是，這些實施例提供許多可實施的發明概念，以應用於多 種特定方向。然而這些特定實施例僅用以說明而非侷限本發明範疇。
自從發明積體電路以來，不同電子構件如電晶體、二極體、電阻、電容、或類似物的積體密度持續改良，進而使半導體產業快速成長。大部份積體密度的改良為重複縮小結構的最小尺寸，使更多的構件整合至固定面積的元件中。
這些改良通常與二維(2D)有關，即積體構件所占的空間位於半導體晶圓的表面上。雖然改良的微影技術可大幅改善2D的積體電路密度，但二維的積體密度仍有其物理極限。物理極限之一為這些元件必然具有最小尺寸。此外，將越多元件置入單一晶片時，其設計越複雜。
三維積體電路(3D IC)的開發可解決上述限制。在某些3D IC的製程中，可形成各自包含積體電路的多個晶圓。接著將不同晶圓上的積體電路對準後接合晶圓。為了實施3D IC，穿透基板通孔(TSV，又稱為穿透矽通孔或穿透基板通孔)的出現率開始提升。一般應用於3D IC與堆疊晶粒的TSV，可提供電性連接及/或幫助散熱。如何形成TSV於3D IC與堆疊晶片中仍具挑戰性。
第1A圖係某些實施例中，封裝100的剖視圖。晶粒100包含兩個半導體晶粒120A與120B，且兩者接合至另一半導體晶粒130。在某些實施例中，每一半導體晶粒120A與120B包含的半導體基板可用以形成半導體積體電路，即半導體電路可形成於半導體基板上及/或中。半導體基板可為半導體材料，比如但不限於基體矽、半導體晶圓、絕緣層上矽(SOI)基板、 或矽鍺基板。此外，亦可採用其他半導體材料如III族元素、IV族元素、或V族元素。半導體基板可進一步包含多個隔離結構(未圖示)如淺溝槽隔離結構(STI)或局部氧化矽結構(LOCOS)。隔離結構可定義並隔離多種微電子單元(未圖示)，而微電子單元可為形成於半導體基板中的電晶體如金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極接面電晶體(BJT)、高電壓電晶體、高頻電晶體、p型及/或n型場效電晶體(PFET/NFET)、或其他電晶體，電阻，二極體，電容，電感，熔絲，或其他合適的微電子單元。
形成多種微電子單元的多種製程包含沉積、蝕刻、佈植、微影、回火、及/或其他合適步驟。微電子單元經內連線可形成積體電路元件如邏輯元件、記憶元件(如SRAM)、射頻元件、輸入/輸出(I/O)元件、系統單晶片(SoC)元件、上述之組合、或其他合適的元件種類。
半導體晶粒130包含TSV 131。半導體晶粒130可包含多種被動與主動微電子元件(未圖示)，比如電阻、電容、電感、二極體、金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極接面電晶體(BJT)、橫向擴散MOS(LDMOS)電晶體、高功率MOS電晶體、finFET電晶體、其他電晶體、及/或上述之組合。在某些實施例中，半導體晶粒130為中介物，以提供3D封裝系統電性連接及/或散熱輔助。具有主動元件的中介物可稱為主動中介物，而不具主動元件的中介物可稱為被動中介物。
第1A圖中的半導體晶粒130亦具有再佈線結構 132。再佈線結構132包含再佈線層(RDL，未圖示)以實施半導體晶粒130、120A、及/或120B的扇出式連接。如第1A圖所示，扇出式的半導體晶粒130與半導體晶粒120A及/或120B之邊緣，超出半導體晶粒130的邊緣。
再佈線結構132亦包含介電層以保護並隔離RDL。再佈線結構132的RDL使內連線延伸出半導體晶粒130、120A、及/或120B的邊緣。半導體晶粒120A與120B經由接合結構125A與125B接合至半導晶粒130的RDL，以連接至TSV 131。半導體晶粒130具有內連線結構133以提供晶粒130之元件(未圖示)、TSV 131、與連接結構134之間的電性連接，上述電性連接係連接至外部連接物135，且內連線結構133與再佈線結構132分別位於半導體晶粒130的相反兩側上。在某些實施例中，內連線結構133包含金屬線路與通孔。外部連接物135可接合至一基板如印刷電路板(PCB)或另一封裝結構。在某些實施例中，保護層145包圍連接結構134。在某些實施例中，保護層145之組成為高分子如聚醯亞胺、聚苯并噁唑(PBO)、或苯并環丁烯(BCB)。
再佈線結構132與接合結構125A與125B及其形成方法可參考2012年3月22日申請的美國專利申請號13/427,753(名稱為Bump Structures for Multi-Chip Packaging)，與2011年12月28日申請的美國專利申請號13/338,820(名稱為Packaged Semiconductor Device and Method of Packaging the Semiconductor Device)。上述兩申請案請參考附件。
成型化合物141覆蓋半導體晶粒120A與120B，而成型化合物142覆蓋半導體晶粒130。在某些實施例中，成型化合 物141與142包含環氧樹脂、矽、氧化矽填充物、及/或其他種類的高分子。在某些實施例中，成型化合物141與142可由相同材料組成。在某些實施例中，再每一半導體晶粒120A、120B、與130之間具有底填物。在某些實施例中，底填物144填入半導體晶粒120A與半導體晶粒130之再佈線結構132之間的空隙，如第1B圖所示。舉例來說，底填物144可為液態環氧樹脂，並以點膠法填滿上述空隙。底填物材料可避免熱應力造成的碎裂形成於接合結構125A之中或附近。在另一實施例中，形成於半導體晶粒120A與130之間的材料可為變形膠或矽橡膠，其形成方法可為注入法或其他方法。在後續製程中，變形膠或矽橡膠可緩解應力。此外，底填物144亦可形成於半導體晶粒120B與130之間。
在某些實施例中，每一半導體晶粒120A、120B、與130之間的空隙均填有成型化合物141。在這種情況下，成型化合物又稱作成型底填物(MUF)。在第1A圖中，兩個半導體晶粒120A與120B以TSV 131接合至半導體晶粒130。然而在某些實施例中，半導體晶粒120A*可接合至半導體晶粒130以形成封裝100*，如第1C圖所示。
第2圖係某些實施例中，接合至其他半導體晶粒前的半導體晶粒130之剖視圖。在第2圖中，半導體晶粒130具有TSV 131與連接結構134，以連接至外部連接物135如上述。TSV 131係形成於基板101中。在某些實施例中，連接結構134可包含金屬柱136於金屬墊137上，且彼此之間以介電層143絕緣。介電層143之組成可為高分子如聚醯亞胺，在某些實施例中亦 可稱為鈍化層。金屬柱136之組成可為銅、銅合金、其他種類的金屬、其他種類的金屬合金、或上述之組合。金屬墊137之組成可為鋁、鋁合金、銅、銅合金、其他種類的金屬、其他種類的合金、或上述之組合。在某些實施例中，在金屬墊137與金屬柱136之間具有凸塊下金屬化層(UBM，未圖示)。UBM除了可作為金屬墊137與金屬柱136的擴散阻障層外，亦可作為實施電鍍的層狀物。
連接結構134與其形成方法可參考2012年3月22日申請的美國專利申請號13/427,753(名稱為Bump Structures for Multi-Chip Packaging)，與2011年12月28日申請的美國專利申請號13/338,820(名稱為Packaged Semiconductor Device and Method of Packaging the Semiconductor Device)。上述兩申請案請參考附件。
在第2圖中，第1A圖的保護層145覆蓋金屬柱136，並覆蓋金屬柱136旁之半導體晶粒130所露出的表面。在某些實施例中，保護層145之組成為高分子如聚醯亞胺、聚苯并噁唑(PBO)、或苯并環丁烯(BCB)。然而保護層145亦可採用其他材料。
第3A至3J圖係某些實施例中，形成封裝100*之製程剖視圖。在第3A圖中，黏著層302位於載板301上。在某些實施例中，載板301之組成為玻璃。然而載板301亦可採用其他材料。在某些實施例中，黏著層302係以沉積或壓合等方式形成於載板301上。黏著層302亦可為膠體或由箔狀物形成的壓合層。在某些實施例中，接著將半導體晶粒130置於黏著層302 上，如第3B圖所示。在具有連接結構134的一側面向黏著層302後，將半導體晶粒130黏結至黏結層302。在某些實施例中，接著將成型化合物142形成於半導體晶粒130上，如第3C圖所示。
在某些實施例中，成型化合物142的形成方法係沉積液態成型化合物於黏著層302上，覆蓋半導體晶粒130後進行熱再流動製程。舉例來說，液態成型化合物可為單體或未完全交聯的高分子。熱再流動製程可讓液態成型化合物中的單體及/或未完全交聯的高分子，轉變為固態的成型化合物142。熱再流動製程亦可蒸發用以形成液態成型化合物的溶劑。
在某些實施例中，接著移除多餘的成型化合物142與部份基板101，以露出半導體晶粒130上的TSV 131，如第3D圖所示。上述移除製程可為研磨、拋光、或其他合適製程。某些實施例在移除多餘的成型化合物142後，形成再佈線結構132與凸塊結構138於露出的TSV 131之表面139上，如第3E圖所示。如上所述，再佈線結構132包含RDL以實施半導體晶粒130的扇出式連接，並晶粒接合至半導體晶粒130如半導體晶粒120A*。再佈線結構132亦包含介電層以保護並隔離RDL。凸塊結構138係形成於再佈線結構132上，使半導體晶粒130連接至其他半導體晶粒。凸塊結構138可為焊料凸塊、銅柱、或其他可行的凸塊結構。在某些實施例中，凸塊結構138係微米級凸塊，其寬度介於約5μm至約30μm之間。
凸塊結構138亦可參考2012年3月22日申請的美國專利申請號13/427,753(名稱為Bump Structures for Multi-Chip Packaging)，與2011年12月28日申請的美國專利申請號 13/338,820(名稱為Packaged Semiconductor Device and Method of Packaging th eSemiconductor Device)。上述兩申請案請參考附件。
在某些實施例中，形成再佈線結構132與凸塊結構138後，可將半導體晶粒120A*置於半導體晶粒130之再佈線結構132與凸塊結構138上，如第3F圖所示。半導體晶粒120A*之凸塊結構(未圖示)對準半導體晶粒130之凸塊結構138。某些實施例在將半導體晶粒120A*置於再佈線結構132與凸塊結構138上前，先施加助焊劑(未圖示)於再佈線結構132與凸塊結構138上。助焊劑可避免凸塊結構138氧化，亦有助於半導體晶粒120A*置於半導體晶粒130上。在某些實施例中，進行熱再流動製程以形成接合結構125A*於半導體晶粒120A*與130之間。接合結構125A*之形成方法，係接合半導體晶粒120A*之凸塊結構與半導體晶粒130之凸塊結構138。如第3F圖所示，半導體晶粒120A*之寬度大於半導體晶粒130之寬度。
若底填物144形成於半導體晶粒120A*與130之間的空隙中(見第1B圖)，則施加底填材料的步驟晚於形成接合結構125A*的步驟。接著熱硬化底填材料以形成底填物144。然而如前所述，可視情況形成或省略底填物144。
某些實施例在形成接合結構125A*或底填物144後，形成成型材料141以覆蓋半導體晶粒120A*，如第3G圖所示。成型化合物141與142的形成方法類似。某些實施例未採用底填物144，因此可省略形成接合結構125A*的再流動製程。用以硬化成型化合物141的熱製程，亦可用以形成接合結構 125A*。未採用底填物144之封裝100*所用之成型化合物141為成型底填(MUF)材料。在某些實施例中，成型化合物141形成於半導體晶粒120A*與再佈線結構132上，如第3G圖所示。
形成成型化合物141後移除載板301，以準備將封裝結構切割成個別的封裝100*。在某些實施例中，移除載板301後先翻轉封裝結構，再將其固定至切割帶305，如第3H圖所示。在某些實施例中，接著移除多餘的成型化合物142與覆蓋連接結構134的部份保護層145，以露出連接結構134如第3I圖所示。此移除製程可為研磨製程、拋光製程、或蝕刻製程。在某些實施例中，移除製程後剩餘的保護層145將圍繞連接結構，如第3I及1A圖所示。
在露出連接結構134後，將外部連接物135如焊料球置於連接結構134上。接著進行再流動製程，使外部連接物135接合至連接結構134。之後將整個封裝切割成個別的封裝100*。在某些實施例中，切割後的封裝100*貼合至切割帶305，如第3J圖所示。在切割製程後，可移除切割帶305以得封裝100*。封裝100*可為適當尺寸，比如封裝100*的低厚度。在某些實施例中，封裝100*的厚度T4介於約90μm至約500μm之間。在某些實施例中，半導體晶粒130的厚度T1介於約30μm至約100μm之間。在某些實施例中，半導體晶粒120A*的厚度T3介於約50μm至約300μm之間。在某些實施例中，再佈線結構132的厚度T2介於約3μm至約20μm之間。此外，形成封裝100*的製程簡易。
上述的第3A至3J圖中的製程與結構係用以形成第 1C圖之封裝100*。在某些實施例中，可形成額外內連線或再佈線結構於連接結構134或半導體晶粒130上，以形成其他應用所需的線路及接合。第3K至3N圖係本發明某些實施例中，形成內連線結構連接結構134或半導體晶粒130上，以形成封裝100’之製程剖視圖。第3K至3N圖依第3G圖之結構進行後續製程。如第3G圖所示，在形成成型材料141後，移除載板301與黏著層302。在某些實施例中，將第3G圖之封裝結構貼合至黏著層304，而黏著層304貼合至另一載板303，如第3K圖所示。在移除載板301與黏著層302後，即翻轉封裝結構並將其固定至黏著層304，如第3K圖所示。在某些實施例中，接著移除覆蓋連接結構134的部份保護層145以露出連接結構134，如第3L圖所示。上述步驟亦移除圍繞保護層145的部份成型材料142。移除製程可為研磨製程、拋光製程、或蝕刻製程。保留的部份保護層145將圍繞連接結構134。
在露出連接結構134後，形成再佈線結構140以覆蓋封裝的半導體晶粒130，如第3M圖所示。再佈線結構140包含再佈線層(RDL)以重新排列接合結構(未圖示，比如接合至外部連接物135如接點的焊墊)，亦可實施此表面(與再佈線結構132對向的表面)上每一半導體晶粒130之扇出式連接。再佈線結構140亦包含介電層，以保護並隔離再佈線層。某些實施例在形成再佈線結構140後，將外部連接物135置於再佈線結構140上的焊墊上，如第3M圖所示。
之後移除載板303與黏結層304，並將其貼合至切割帶305，再將封裝100’切割成個別的封裝。在某些實施例中， 切割後的封裝100’仍貼合至切割帶305，如第3N圖所示。在切割製程後，可移除切割帶146即形成封裝100’。在某些實施例中，半導體晶粒130與再佈線結構140之厚度T1’介於30μm至約100μm之間。在某些實施例中，再佈線結構140之厚度T5介於約3μm至約20μm之間。
第4圖係某些實施例中，封裝的部份剖視圖。第4圖為接合至半導體晶粒120A*的半導體晶粒130其邊緣部份。如第4圖所示，使半導體晶粒130接合至金屬柱136的外部連接物135如焊料凸塊，係經由凸塊下金屬化層(UBM)147接合至金屬墊137。在某些實施例中，金屬柱136的寬度H1介於約60μm至約320μm之間。在某些實施例中，金屬墊137、凸塊下金屬化層147、金屬柱136形成連接結構134，且彼此之間隔有介電層143A與143B。在某些實施例中，連接結構134埋置於保護層145中(或被保護層145包圍)。在某些實施例中，介電層143A與143B之組成為高分子。在第4圖中，內連線結構133係形成於半導體晶粒130的TSV 131上。內連線結構133包含金屬墊137、金屬層151與153、與通孔152，且上述單元以介電層154絕緣。第4圖中的內連線結構133僅用以舉例，並可進一步包含額外金屬墊與通孔。
在某些實施例中，凸塊下金屬化層147包含擴散阻障層與晶種層。在某些實施例中，擴散阻障層亦可作為黏著層。擴散阻障層之組成可為鉭、氮化鉭、鈦、氮化鈦、或上述之組合。晶種層之組成可實施金屬柱146的沉積製程。在某些實施例中，凸塊下金屬化層147包含鈦形成的擴散阻障層與銅 形成的晶種層。在某些實施例中，擴散阻障層如鈦與晶種層如銅的沉積方法均為物理氣相沉積法(PVD)或濺鍍法。
第4圖之再佈線結構132包括再佈線層162形成於金屬層155下，而金屬層155連接至TSV 131。再佈線層162實施半導體晶粒130的扇出式連接，即位於半導體晶粒130與120A*之間的接合結構125A*之一，超出半導體晶粒130的邊緣。在某些實施例中，每一接合結構125A*包含凸塊下金屬化層147’與147”、金屬柱159與160、及接合焊料層161。在某些實施例中，接合結構125A*之金屬柱159的寬度H2介於約5μm至約40μm之間。在某些實施例中，金屬柱159與160具有大致相同的寬度。
介電層156、157、與158使再佈線層154絕緣。在某些實施例中，介電層156、157、及158為高分子阻成的鈍化層。第4圖中的再佈線結構132僅用以舉例，並可進一步包含額外金屬層與介電層以實施內連線及扇出式連接。
封裝的半導體晶粒130可參考2012年9月14日申請的美國專利申請號13/619,877(名稱為3DIC Stacking Device and Method of Manufacture)。上述申請案請參考附件。
多種實施例已提供形成具有一或多個晶粒於中介晶粒上的封裝機制。藉由形成再佈線結構於具有TSV之中介晶粒上，接合至中介晶粒的晶粒邊緣可超出中介晶粒的邊緣。此外，可形成另一再佈線結構於中介晶粒的另一表面上(與再佈線結構之表面對向)。其他再佈線結構可重新排列接合結構，使其扇出式連接中介晶粒的外部連接物。
在某些實施例中，提供之半導體封裝包括：具有 多個穿透基板通孔(TSV)的中介晶粒，以及第一封裝晶粒。半導體封裝亦包括第一再佈線結構形成於中介晶粒的第一表面上，其中第一再佈線結構包括第一再佈線層以實施中介晶粒的扇出式連接，且其中第一封裝晶粒接合至第一再佈線層。第一封裝晶粒的邊緣超出中介晶粒最接近第一封裝晶粒的邊緣。
在某些實施例中，半導體封裝包括：具有多個穿透基板通孔(TSV)的中介晶粒與封裝晶粒。半導體封裝亦包括第一再佈線結構形成於中介晶粒的第一表面上，且再佈線結構包括第一再佈線層以實施中介晶粒的扇出式連接。封裝晶粒接合至第一再佈線層，且封裝晶粒之邊緣超出中介晶粒最接近封裝晶粒的邊緣。半導體封裝更包括具有第二再佈線層之第二再佈線結構，覆蓋中介晶粒的第二表面，使中介晶粒扇出式連接外部連接物。
在某些實施例中，形成半導體封裝的方法包括：提供第一載板，具有第一黏著層於其上；並將具有多個穿透基板通孔之中介晶粒置於第一黏著層上。中介晶粒的第一表面具有多個連接結構並面向第一黏著層，且連接結構被保護層包圍。上述方法亦包括形成第一成型化合物於中介晶粒上，並移除部份第一成型化合物與部份中介晶粒的基板，以露出穿透基板通孔。此外，上述方法亦形成第一再佈線結構於中介晶粒之第二表面所露出的穿透基板通孔上，其中中介晶粒的第二表面與第一表面對向。接著形成多個凸塊結構於第一再佈線結構上，並將封裝晶粒接合至第一再佈線結構上的凸塊結構，以形成封裝結構。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
H1、H2‧‧‧寬度
120A*、130‧‧‧半導體晶粒
125A*‧‧‧接合結構
131‧‧‧TSV
132‧‧‧再佈線結構
133‧‧‧內連線結構
134‧‧‧連接結構
135‧‧‧外部連接物
136、159、160‧‧‧金屬柱
137‧‧‧金屬墊
139‧‧‧表面
141、142‧‧‧成型化合物
143A、143B、154、156、157、158‧‧‧介電層
151、153、155‧‧‧金屬層
145‧‧‧保護層
147、147’、147”‧‧‧凸塊下金屬化層
152‧‧‧通孔
154‧‧‧再佈線層
161‧‧‧接合焊料層
162‧‧‧再佈線層

Claims (10)

  1. 一種半導體封裝，包括：具有多個穿透基板通孔的一中介晶粒；一第一封裝晶粒；以及一第一再佈線結構，形成於該中介晶粒的一第一表面上，其中該第一再佈線結構包括一第一再佈線層以實施該中介晶粒的扇出式連接，且其中該第一封裝晶粒接合至該第一再佈線層；其中該第一封裝晶粒的邊緣超出該中介晶粒最接近該第一封裝晶粒的邊緣。
  2. 如申請專利範圍第1項所述之半導體封裝，其中該中介晶粒具有與該第一表面對向的一第二表面，且該第二表面具有多個外部連接物。
  3. 如申請專利範圍第2項所述之半導體封裝，更包括：具有一第二再佈線層之一第二再佈線結構，覆蓋該中介晶粒的該第二表面，使該中介晶粒扇出式連接外部連接物。
  4. 如申請專利範圍第1項所述之半導體封裝，其中該第一再佈線層接合至一第二封裝晶粒。
  5. 一種半導體封裝，包括：具有多個穿透基板通孔的一中介晶粒；一封裝晶粒；一第一再佈線結構形成於該中介晶粒的一第一表面上，其中該再佈線結構包括一第一再佈線層以實施該中介晶粒的扇出式連接，其中該封裝晶粒接合至該第一再佈線層，且 其中該封裝晶粒之邊緣超出該中介晶粒最接近該封裝晶粒的邊緣；以及具有一第二再佈線層之一第二再佈線結構，覆蓋該中介晶粒的一第二表面，使該中介晶粒扇出式連接外部連接物。
  6. 一種形成半導體封裝的方法，包括：提供一第一載板，具有一第一黏著層於其上；將具有多個穿透基板通孔之一中介晶粒置於該第一黏著層上，其中該中介晶粒的一第一表面具有多個連接結構並面向該第一黏著層，且該些連接結構被一保護層包圍；形成一第一成型化合物於該中介晶粒上；移除部份該第一成型化合物與部份該中介晶粒的基板，以露出該些穿透基板通孔；形成一第一再佈線結構於該中介晶粒之一第二表面所露出的該些穿透基板通孔上，其中該中介晶粒的該第二表面與該第一表面對向；形成多個凸塊結構於該第一再佈線結構上；以及將一封裝晶粒接合至該第一再佈線結構上的該些凸塊結構，以形成一封裝結構。
  7. 如申請專利範圍第6項所述之形成半導體封裝的方法，更包括：形成一第二成型化合物於該封裝晶粒上；移除該第第一載板與該第一黏著層；將該封裝結構置於一切割帶上，並使封裝晶粒面向該切割帶； 移除部份該保護層以露出該中介晶粒的該些連接結構；以及形成多個外部連接物於該中介晶粒的該些連接結構上。
  8. 如申請專利範圍第6項所述之形成半導體封裝的方法，其中該第一再佈線結構包括一第一再佈線層，且該第一再佈線層使該中介晶粒扇出式連接該封裝晶粒。
  9. 如申請專利範圍第7項所述之形成半導體封裝的方法，更包括：在移除部份該保護層之後，且在形成該外部連接物於該中介晶粒的該些連接結構之前，形成具有第二再佈線層之一第二再佈線結構，其中該第二再佈線結構實施該中介晶粒扇出式連接至該外部連接物。
  10. 如申請專利範圍第7項所述之形成半導體封裝的方法，其中形成該第二再佈線結構之步驟包括：將該封裝結構置於該第二黏著層上，且該第二黏著層貼合至一第二載板，其中該封裝晶粒面向該第二黏著層；以及形成該第二再佈線結構於該中介晶粒上，其中該第一再佈線結構露出該中介晶粒的多個連接結構。
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US9502380B2 (en) 2016-11-22
US20190088620A1 (en) 2019-03-21
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