CN106548998A - 封装基材的制作方法 - Google Patents

封装基材的制作方法 Download PDF

Info

Publication number
CN106548998A
CN106548998A CN201610602076.0A CN201610602076A CN106548998A CN 106548998 A CN106548998 A CN 106548998A CN 201610602076 A CN201610602076 A CN 201610602076A CN 106548998 A CN106548998 A CN 106548998A
Authority
CN
China
Prior art keywords
metal
core base
circuit
upper strata
manufacture method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610602076.0A
Other languages
English (en)
Inventor
胡迪群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CN106548998A publication Critical patent/CN106548998A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种封装基材的制作方法，其步骤至少包括：准备核心基材；制作下层重新分配电路于核心基材的下表面；其中，下层重新分配电路埋设于下层介电层中，包含有复数个第一上层金属垫以及复数个第一下层金属垫；从核心基材的上层磨薄核心基材；从核心基材的上方制作复数个孔；每个孔的底部裸露出对应的第一上层金属垫的上表面；在每个孔的内部填充金属，形成复数个贯穿核心基材的金属柱；以及切割，获得复数个半成品。本发明能有效减少或是消除薄膜封装基材在制程中或是封装程序中产生皱褶(wrinkle)或是板翘(warpage)。

Description

封装基材的制作方法
技术领域
本发明涉及一种封装基材的制作方法，特别是一种减少或是消除薄膜封装基材(thin film package substrate)在制程中或是封装程序中可能产生皱褶(wrinkle)或是板翘(warpage)的一种封装基材的制作方法。
背景技术
随着技术的进步，半导体封装基材愈做愈薄，在制程中，基于各种不同材料的热膨胀系数(coefficient of thermal expansion；CTE)的不同，薄膜基材遭遇到的问题之一，便是皱褶或是板翘的问题，若是未能解决皱褶或是板翘的问题，在后续的电路「对位(registration)便会发生很大的困扰，所以，如何消除或是避免薄型电路产生皱褶或是板翘，是高密度薄膜封装基材必须解决的一大课题。
图1A～1E显示美国专利公开号US20150135527A1所揭露的一个先前技艺，其揭露一个封装基材的制程，包含下述步骤：
图1A显示：准备核心基材(core substrate)10；
图1B显示：由核心基材10的上方，制作复数个孔11，孔11的深度不大于基材10的厚度，孔10的底部并未贯通核心基材10；
图1C显示：填充金属于孔11中，制成复数条金属柱12；
图1D显示：制作电路重新分配层RDL于核心基材10上方；电路重新分配层RDL电性耦合于金属柱12。电路重新分配层RDL具有埋设于介电层13中的重新分配电路14；复数个上层焊垫141设置于重新分配电路14的上层；复数个下层焊垫142设置于重新分配电路14的下层；每一个下层焊垫142分别电性耦合至对应的金属柱12的上端。
图1E显示：由核心基材10的下方磨薄核心基材10，使得金属柱12的下端裸露出来，制成金属柱12贯通核心基材10的结构。
之后，再进行后面的制程，后面的制程包含在金属柱12下方制作下层电路重新分配层…等结构；本说明书在此省略后续制程的描述。此一先前技艺，先制作金属柱12的前段制程，然后制作电路重新分配层RDL于金属柱12上方；然后从下方开始磨薄核心基材10，使金属柱12呈现贯通核心基材10的状态。
此一先前技艺的缺点是：在含有金属柱12的核心基材10上方制作薄膜电路重新分配层RDL，因为有金属柱12与核心基材10混合材料做基础，混合材料的CTE相对较大，故制作薄膜电路重新分配层RDL的时候，基于CTE匹配问题，使得薄膜电路重新分配层RDL尺寸稳定度较差，后续制程在对位上，会有偏差可能，而发生产品可靠度问题。
发明内容
针对现有技术的上述不足，根据本发明的实施例，希望提供一种能有效减少或是消除薄膜封装基材在制程中或是封装程序中产生皱褶(wrinkle)或是板翘(warpage)的封装基材的制作方法。
根据实施例，本发明提供的一种封装基材的制作方法，其步骤至少包括：
准备核心基材；
制作下层重新分配电路于核心基材的下表面；其中，下层重新分配电路埋设于下层介电层中，包含有复数个第一上层金属垫以及复数个第一下层金属垫；
从核心基材的上层磨薄核心基材；
从核心基材的上方制作复数个孔；每个孔的底部裸露出对应的第一上层金属垫的上表面；
在每个孔的内部填充金属，形成复数个贯穿核心基材的金属柱；以及
切割，获得复数个半成品。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：
准备暂时性承载板，其中，暂时性承载板的上表面涂布有释放层；
安置复数个前述的半成品于释放层的上面；其中，每个半成品的设置以金属柱在上方、下层重新分配电路在下方的位置安置；
以第一封装胶体包裹封装每一半成品至少四个侧面周边；
在复数个金属柱的上面制作上层重新分配电路；其中，上层重新分配电路具有复数个第二上层金属垫以及复数个第二下层金属垫；其中，每个金属柱的上端分别电性耦合到对应的一个第二下层金属垫；
移除暂时性承载板；以及
从下层介电层的底面制作复数个底部开口，分别裸露对应的第一下层金属垫的下表面。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：在复数个第一下层金属垫的底表面设置至少一片芯片。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：在芯片和下层介电层的底表面之间的空间中填充下层填充材料。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：施加第二封装胶体，封装芯片。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：设置复数个焊锡球，每一个焊锡球设置于对应的一个第二上层金属垫的上表面。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：切割，获得复数个芯片封装单元。
根据实施例，本发明提供的另一种封装基材的制作方法，包括如下步骤：
准备核心基材；
制作下层重新分配电路于核心基材的底表面；其中，下层重新分配电路埋设于下层介电层中，具有复数个第一上层金属垫以及复数个第一下层金属垫；
从核心基材的上层磨薄核心基材；
从核心基材的上方制作复数个孔；每个孔的底部裸露出对应的第一上层金属垫的上表面；
在每个孔中填充金属，形成复数个贯穿核心基材的金属柱；
制作上层重新分配电路于复数个金属柱的上面；其中，上层重新分配电路埋设于上层介电层中，具有复数个第二上层金属垫，并且具有复数个第二下层金属垫；其中，每个金属柱的上端分别电性耦合到对应的第二下层金属垫的下表面；以及
从下层介电层的底面制作复数个底部开口，分别裸露对应的第一下层金属垫的下表面。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：在复数个第一下层金属垫的底表面上设置至少一片芯片。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：在芯片和下层介电层的底表面之间的空间中填充下层填充材料。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：施加封装胶体，封装芯片。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：从上层介电层的顶面制作复数个顶部开口，分别裸露对应的第二上层金属垫的上表面；以及设置复数个焊锡球，每一个焊锡球设置于对应的一个第二上层金属垫的上表面。
根据一个实施例，本发明前述封装基材的制作方法中，进一步包含如下步骤：切割，获得复数个芯片封装单元。
相对于现有技术，本发明先以单纯厚片核心基材(core substrate)当作基础，在厚片核心基材下方制作下层电路重新分配层RDL1，借着厚片核心基材的固有的坚固性与较低的CTE，可以获得尺寸稳定度较高的下层电路重新分配层RDL1；之后，再进行磨薄基材、挖孔、填充金属…等制作完成第一金属柱，呈现第一金属柱贯通核心基材的结构。本发明揭露的芯片用封装基材的制程中：首先，准备核心基材，形成底部电路重新分配层(RDL1)于核心基材下方；在底部重新分配层的制程中，底部重新分配层的任何可能的皱褶或是板翘，通过在核心基材的坚硬度所抑制，而不会发生皱褶或是板翘；然后制作多个第一金属柱，贯穿核心基材；最后，制作顶部电路重新分配层(RDL2)于核心基材上方。底部电路重新分配层(RDL1)的底表面适合芯片的安置，顶部电路重新分配层(RDL2)的上表面适合焊锡球的设置用以匹配片封装单元至系统电路板。
附图说明
图1A～1E是先前技艺之封装基材的制作过程示意图。
图2A～2E是本发明的一个半成品的制作过程示意图。
图3是本发明的一个半成品的结构示意图。
图4～9是本发明封装基材的第一制作过程示意图。
图10A～10E和图11～14是本发明封装基板的第二制作过程示意图。
其中：1B为第一下层金属垫；1T为第一上层金属垫；20为核心基材；200为半成品；21为孔；22为第一金属柱；231,232,233,234为介电层；23B为下层重新分配电路；23T为上层重新分配电路；24为第一封装胶体；25为底部开口；252为顶部开口；26为芯片；261为第二金属柱；262为底部填充材料；263为第二封装胶体；27为焊锡球；29为暂时承载板；291为释放层；2B为第二下层金属垫；2T为第二上层金属垫；RDL1为下层电路重新分配层；RDL2为上层电路重新分配层。
具体实施方式
下面结合附图和具体实施例，进一步阐述本发明。这些实施例应理解为仅用于说明本发明而不用于限制本发明的保护范围。在阅读了本发明记载的内容之后，本领域技术人员可以对本发明作各种改动或修改，这些等效变化和修改同样落入本发明权利要求所限定的范围。
本发明提供一个制作封装基材(package substrate)的制程，不同于先前技艺的制程。本发明先以单纯厚片核心基材(core substrate)当作基础，在厚片核心基材下方制作下层电路重新分配层RDL1，借着厚片核心基材的固有的坚固性与较低的CTE，可以获得尺寸稳定度较高的下层电路重新分配层RDL1；之后，再进行磨薄基材、挖孔、填充金属…等制作完成第一金属柱，呈现第一金属柱贯通核心基材的结构。
本发明揭露一种封装基材的制程，包含制作一个下层电路重新分配层(redistribution layer；RDL)于厚片核心基材下方，且是在第一金属柱(metal pillars)被制作之前制作完成下层电路重新分配层RDL1的。即是：如图2C所示，先制作下层电路重新分配层RDL1于厚片核心基材20下方；接着如图2D～2E所示，复数个第一金属柱22被制作使贯穿厚片核心基材20。其中，下层电路重新分配层RDL1于制程中，原本可能产生的皱褶或是板翘，都可以被起始作业所使用的厚片核心基材20的坚固性所压制，而不会发生皱褶或是板翘。厚片核心基材20系使用具有低的CTE的材料，例如：因瓦合金(Invar 1ppm)、氮化硅(Silicon Nitride 2.6ppm)、硅(Silicon 3ppm)、或是玻璃(Glass 4ppm)…等材料。
图2A～2E显示本发明的一个半成品的制作过程。
依据下述制程，可以制作得到复数个半成品200：
图2A显示：准备核心基材20；
图2B显示：制作下层电路重新分配层RDL1于核心基材20下方；下层电路重新分配层RDL1系包含下层重新分布电路(redistribution circuitry)23B埋设于下层介电材料层231,232中。复数个第一上层金属垫1T设置于下层重新分布电路23B的上方，复数个第一下层金属垫1B设置于下层重新分布电路23B的下方。厚片核心基材20的坚固性以及具有低的CTE的特性，可以压制下层电路重新分配层RDL1在制程中的尺寸变化，而不会发生皱褶或是板翘，可以保持下层重新分布电路23B的尺寸定性。
图2C显示：从核心基材20上方，磨薄核心基材20；
图2D显示：从核心基材20上方，制作复数个孔21；每一个孔21的底部，裸露对应的一个上层金属垫1T的上表面；
图2E显示：填充金属到每一个孔21中，制成复数个第一金属柱22，除去上方多余的材料(图中未表示)以后，呈现第一金属柱22贯通核心基材20的结构；图2E的结构，经过切割以后，可以获得复数个半成品200。
图3显示本发明的一个半成品。
图3显示本发明的一个半成品200，其具有复数个第一金属柱22，贯穿核心基材20。核心基材20底部设置有下层重新分配电路23B，复数个上层金属垫1T设置于下层重新分配电路23B的上方；复数个下层金属垫1B设置于下层重新分配电路23B的下方；每一个上层金属垫1T分别电性耦合于对应的一个第一金属柱22的下端。
图4～9显示本发明封装基材的第一制程。
图4显示：准备一片暂时承载板29；暂时承载板29的表面涂布有一层释放层(release layer)291；安置复数个半成品200于释放层291的上面；其中，每个半成品200以第一金属柱22在上、下层电路重新分配层RDL1在下的位置，放置于释放层291上面。
图5显示：用第一封装胶体(molding compound)24包裹封装半成品200的至少四个侧面；移除上方多余的材料，使得第一封装胶体24上表面与半成品200上表面，呈现共平面状。
图6显示：在复数个第一金属柱22与第一封装胶体24的上面，制作上层电路重新分配层RDL2；其中，上层电路重新分配层RDL2包含有上层重新分配电路23T埋设于介电层233,234,235中。复数个第二上层金属垫2T设置于上层重新分配电路23T的上方，复数个第二下层金属垫2B设置于上层重新分配电路23T的下方；其中，每个第一金属柱22具有一个上端，分别电性耦合至相对应的一个第二下层金属垫2B；接着，在介电层235的顶部，制作复数个顶部开口252，分别暴露一个对应的第二上层金属垫2T的上表面上；并移除临时承载板29。
图7显示：从下层介电层232的底部，制作复数个底部开口25，以分别暴露第一下层金属垫1B的底面。
图8显示：准备至少一片芯片26，安置于复数个第一下层金属垫1B的下方；芯片26利用复数个第二金属柱261电性耦合至第一下层金属垫1B；然后，在芯片26和下方介电层232之间的空间中，填充底部填充材料(underfill)262；接着，施加第二封装胶体263用以封装芯片26；设置复数个焊锡球27，每一个焊锡球27设置于对应的第二上层金属垫2T的上表面；最后，经由切割，获得复数个芯片封装单元。
图9显示：在单一芯片封装中，具有核心基材20，复数个金属柱22贯穿核心基材20；下层电路重新分配层RDL1设置于金属柱22的下方，上层电路重新分配层RDL2设置于金属柱22的上方；下层电路重新分配层RDL1与上层电路重新分配层RDL2经由金属柱22互相电性耦合；第一封装胶体24包裹核心基材20和下层电路重新分配层RDL1的至少四个侧面。芯片26经由复数个第二金属柱261电性耦合到第一下层金属垫1B的底面。
图10A～10E和图11～14显示本发明封装基板的第二制程。
第二制程与第一制程的不同点，在于第二制程省略了第一制程图3～图5的切割、安置、封装胶体等步骤。
图10A显示：准备一片核心基材20；
图10B显示：成在核心基材20的下表面，制作下层电路重新分配层RDL1；其中，下层电路重新分配层RDL1具有下层重新分配电路23B埋设于下层介电层231,232中，下层重新分配电路23B具有复数个第一上层金属垫1T设置于上方，也具有复数个第一下层金属垫1B设置于下方。
图10C显示：从核心基材20的顶部向下磨薄；
图10D显示：从核心基材20的上方，制作复数个孔21；每一个孔21的底部，裸露出对应的第一上层金属垫1T的上表面；
图10E显示：在每个孔21中，填充金属以形成复数个金属柱22；金属柱22贯穿核心基材20，下端电性耦合到下层重新分配电路23B。
图11显示：在复数个金属柱22的上面，制作上层电路重新分配层RDL2；其中，上层电路重新分配层RDL2具有上层重新分配电路23T埋设于上层介电层233,234,235中；复数个第二上层金属垫2T设置于上层重新分配电路23T的上方，复数个第二下层金属垫2B设置于上层重新分配电路23T的下方；其中，每个金属柱22具有一个顶部表面，电性耦合到对应的第二下层金属垫2B。从上层介电层235的上方，制作复数个开口252，分别暴露对应的第二上层金属垫2T的上表面。
图12显示：从底部介电层232的底部，制作复数个底部开口25，以分别暴露每个对应的第一下层金属垫1B的底面。
图13显示：至少一片芯片26，安置于复数个第一下层金属垫1B下方；芯片26借着第二金属柱261，与电性耦合至第一下层金属垫1B。下方介电层232的下表面与芯片26之间的空间中，填充底部填充材料(underfill)262；施加第二封装胶体263，包裹封装芯片26；设置复数个焊锡球27，每一个焊锡球27分别设置于对应的一个第二上层金属垫2T的上表面。
图14显示：切割获得复数个芯片封装单元。图14显示：在单一芯片封装中，包含有核心基材20，复数个金属柱22贯穿核心基材20；金属柱22的下端电性耦合至下层电路重新分配层RDL1；复数个金属柱22的上端电性耦合至上层电路重新分配层RDL2；复数个焊锡球27设置于顶部，每个焊锡球27分别设置于对应的一个第二上层金属垫2T的上表面。芯片26借着复数个第二金属柱261电性耦合至第一下层金属垫1B的底面，底部填充材料262填充于芯片26和下层电路重新分配层RDL1的下表面之间的空间中；第二封装胶体263包裹方装芯片26至少周围四边，芯片26的底面裸露提供散热用。

Claims (13)

1.一种封装基材的制作方法，其特征是，其步骤至少包括：
准备核心基材；
制作下层重新分配电路于核心基材的下表面；其中，下层重新分配电路埋设于下层介电层中，包含有复数个第一上层金属垫以及复数个第一下层金属垫；
从核心基材的上层磨薄核心基材；
从核心基材的上方制作复数个孔；每个孔的底部裸露出对应的第一上层金属垫的上表面；
在每个孔的内部填充金属，形成复数个贯穿核心基材的金属柱；以及
切割，获得复数个半成品。
2.如权利要求1所述的封装基材的制作方法，其特征是，进一步包含如下步骤：
准备暂时性承载板，其中，暂时性承载板的上表面涂布有释放层；
安置复数个前述的半成品于释放层的上面；其中，每个半成品的设置以金属柱在上方、下层重新分配电路在下方的位置安置；
以第一封装胶体包裹封装每一半成品至少四个侧面周边；
在复数个金属柱的上面，制作上层重新分配电路；其中，上层重新分配电路具有复数个第二上层金属垫以及复数个第二下层金属垫；其中，每个金属柱的上端分别电性耦合到对应的一个第二下层金属垫；
移除暂时性承载板；以及
从下层介电层的底面制作复数个底部开口，分别裸露对应的第一下层金属垫的下表面。
3.如权利要求2所述的封装基材的制作方法，其特征是，进一步包含如下步骤：在复数个第一下层金属垫的底表面设置至少一片芯片。
4.如权利要求3所述的封装基材的制作方法，其特征是，进一步包含如下步骤：在芯片和下层介电层的底表面之间的空间中填充下层填充材料。
5.如权利要求4所述的封装基材的制作方法，其特征是，进一步包含如下步骤：施加第二封装胶体，封装芯片。
6.如权利要求5所述的封装基材的制作方法，其特征是，进一步包含如下步骤：设置复数个焊锡球，每一个焊锡球设置于对应的一个第二上层金属垫的上表面。
7.如权利要求6所述的封装基材的制作方法，其特征是，进一步包含如下步骤：切割，获得复数个芯片封装单元。
8.一种封装基材的制作方法，其特征是，包括如下步骤：
准备核心基材；
制作下层重新分配电路于核心基材的底表面；其中，下层重新分配电路埋设于下层介电层中，具有复数个第一上层金属垫以及复数个第一下层金属垫；
从核心基材的上层磨薄核心基材；
从核心基材的上方制作复数个孔；每个孔的底部裸露出对应的第一上层金属垫的上表面；
在每个孔中填充金属，形成复数个贯穿核心基材的金属柱；
制作上层重新分配电路于复数个金属柱的上面；其中，上层重新分配电路埋设于上层介电层中，具有复数个第二上层金属垫，并且具有复数个第二下层金属垫；其中，每个金属柱的上端分别电性耦合到对应的第二下层金属垫的下表面；以及
从下层介电层的底面制作复数个底部开口，分别裸露对应的第一下层金属垫的下表面。
9.如权利要求8所述的封装基材的制作方法，其特征是，进一步包含如下步骤：在复数个第一下层金属垫的底表面上设置至少一片芯片。
10.如权利要求9所述的封装基材的制作方法，其特征是，进一步包含如下步骤：在芯片和下层介电层的底表面之间的空间中填充下层填充材料。
11.如权利要求10所述的封装基材的制作方法，其特征是，进一步包含如下步骤：施加封装胶体，封装芯片。
12.如权利要求11所述的封装基材的制作方法，其特征是，进一步包含如下步骤：从上层介电层的顶面制作复数个顶部开口，分别裸露对应的第二上层金属垫的上表面；以及设置复数个焊锡球，每一个焊锡球设置于对应的一个第二上层金属垫的上表面。
13.如权利要求12所述的封装基材的制作方法，其特征是，进一步包含如下步骤：切割，获得复数个芯片封装单元。
CN201610602076.0A 2015-09-17 2016-07-28 封装基材的制作方法 Pending CN106548998A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562219747P 2015-09-17 2015-09-17
US62/219,747 2015-09-17

Publications (1)

Publication Number Publication Date
CN106548998A true CN106548998A (zh) 2017-03-29

Family

ID=58283206

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610602076.0A Pending CN106548998A (zh) 2015-09-17 2016-07-28 封装基材的制作方法

Country Status (3)

Country Link
US (1) US9691717B2 (zh)
CN (1) CN106548998A (zh)
TW (1) TWI705507B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10276424B2 (en) 2017-06-30 2019-04-30 Applied Materials, Inc. Method and apparatus for wafer level packaging
KR102412613B1 (ko) 2017-07-24 2022-06-23 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US11049779B2 (en) * 2018-10-12 2021-06-29 Dyi-chung Hu Carrier for chip packaging and manufacturing method thereof
CN111799182A (zh) * 2019-04-09 2020-10-20 矽品精密工业股份有限公司 封装堆叠结构及其制法
US11862545B2 (en) * 2020-07-28 2024-01-02 Dyi-chung Hu Integrated substrate structure, electronic assembly, and manufacturing method thereof

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060088955A1 (en) * 2004-10-26 2006-04-27 Yu-Pin Tsai Chip package, chip packaging, chip carrier and process thereof
CN102157438A (zh) * 2011-01-31 2011-08-17 江阴长电先进封装有限公司 晶圆级转接板的制备方法
US20120086122A1 (en) * 2010-10-12 2012-04-12 Bin-Hong Cheng Semiconductor Device And Semiconductor Package Having The Same
CN102543927A (zh) * 2010-12-14 2012-07-04 欣兴电子股份有限公司 嵌埋穿孔中介层的封装基板及其制造方法
CN102810528A (zh) * 2011-06-03 2012-12-05 台湾积体电路制造股份有限公司 插入件测试结构和方法
CN202651107U (zh) * 2012-06-25 2013-01-02 欣兴电子股份有限公司 具中介层的封装基板及其封装结构
CN103094244A (zh) * 2011-10-31 2013-05-08 欣兴电子股份有限公司 嵌埋穿孔中介层的封装基板及其制法
US20140091473A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Novel three dimensional integrated circuits stacking approach
CN103779284A (zh) * 2012-10-22 2014-05-07 欣兴电子股份有限公司 封装载板与芯片封装结构
CN104427753A (zh) * 2013-08-31 2015-03-18 揖斐电株式会社 结合型印刷布线板及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8350377B2 (en) * 2008-09-25 2013-01-08 Wen-Kun Yang Semiconductor device package structure and method for the same
TWI543307B (zh) * 2012-09-27 2016-07-21 欣興電子股份有限公司 封裝載板與晶片封裝結構
US9431369B2 (en) * 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
US9502322B2 (en) * 2014-10-24 2016-11-22 Dyi-chung Hu Molding compound supported RDL for IC package
US9691661B2 (en) * 2015-03-26 2017-06-27 Dyi-chung Hu Low profile IC package
JP6566726B2 (ja) * 2015-05-28 2019-08-28 新光電気工業株式会社 配線基板、及び、配線基板の製造方法
US9837347B2 (en) * 2015-08-14 2017-12-05 Dyi-chung Hu Coaxial copper pillar

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060088955A1 (en) * 2004-10-26 2006-04-27 Yu-Pin Tsai Chip package, chip packaging, chip carrier and process thereof
US20120086122A1 (en) * 2010-10-12 2012-04-12 Bin-Hong Cheng Semiconductor Device And Semiconductor Package Having The Same
CN102543927A (zh) * 2010-12-14 2012-07-04 欣兴电子股份有限公司 嵌埋穿孔中介层的封装基板及其制造方法
CN102157438A (zh) * 2011-01-31 2011-08-17 江阴长电先进封装有限公司 晶圆级转接板的制备方法
CN102810528A (zh) * 2011-06-03 2012-12-05 台湾积体电路制造股份有限公司 插入件测试结构和方法
US20120305916A1 (en) * 2011-06-03 2012-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer Test Structures and Methods
CN103094244A (zh) * 2011-10-31 2013-05-08 欣兴电子股份有限公司 嵌埋穿孔中介层的封装基板及其制法
CN202651107U (zh) * 2012-06-25 2013-01-02 欣兴电子股份有限公司 具中介层的封装基板及其封装结构
US20140091473A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Novel three dimensional integrated circuits stacking approach
CN103779284A (zh) * 2012-10-22 2014-05-07 欣兴电子股份有限公司 封装载板与芯片封装结构
CN104427753A (zh) * 2013-08-31 2015-03-18 揖斐电株式会社 结合型印刷布线板及其制造方法

Also Published As

Publication number Publication date
US20170084548A1 (en) 2017-03-23
TW201721768A (zh) 2017-06-16
TWI705507B (zh) 2020-09-21
US9691717B2 (en) 2017-06-27

Similar Documents

Publication Publication Date Title
CN106548998A (zh) 封装基材的制作方法
US10304794B2 (en) Manufacturing method of integrated circuit package
US20140252572A1 (en) Structure and Method for 3D IC Package
CN106558573A (zh) 半导体封装结构及形成该半导体封装结构的方法
CN104733402B (zh) 半导体封装结构及其制法
CN107818956A (zh) 半导体封装、封装上封装及其制造方法
CN102177580A (zh) 具有封装剂保持结构的反转芯片半导体封装及条带
TW201533814A (zh) 封裝結構性元件
CN104952828A (zh) 覆晶堆叠封装结构及其制作方法
KR101151258B1 (ko) 기준점 인식용 다이를 이용한 반도체 패키지 및 그 제조 방법
US20150014864A1 (en) Semiconductor package and method of fabricating the same
CN113363166A (zh) 扇出型堆迭式半导体封装结构的多层模封方法
CN103681516B (zh) 制造半导体装置的方法
KR20140020506A (ko) 웨이퍼 레벨의 팬 아웃 패키지 및 그 제조 방법
CN104157619A (zh) 一种新型PoP堆叠封装结构及其制造方法
US20160013122A1 (en) Methods of fabricating qfn semiconductor package and metal plate
CN204011396U (zh) 一种新型PoP堆叠封装结构
US10276424B2 (en) Method and apparatus for wafer level packaging
US6821818B2 (en) Method of assembling a semiconductor device including sweeping (with a squeegee) encapsulant over the device repeatedly
CN106611747A (zh) 模封互连基板及其制造方法
CN109411367A (zh) 半导体封装结构及其形成方法
CN114420676B (zh) 一种降低翘曲的芯片级封装结构及其制备方法
CN104900547A (zh) 多元合金成分的微凸点制备工艺
US6514797B2 (en) Underfill applications using film technology
CN204348708U (zh) 一种扇出型圆片级芯片倒装封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170329

WD01 Invention patent application deemed withdrawn after publication