TW201533814A - 封裝結構性元件 - Google Patents

封裝結構性元件 Download PDF

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Publication number
TW201533814A
TW201533814A TW104116137A TW104116137A TW201533814A TW 201533814 A TW201533814 A TW 201533814A TW 104116137 A TW104116137 A TW 104116137A TW 104116137 A TW104116137 A TW 104116137A TW 201533814 A TW201533814 A TW 201533814A
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Taiwan
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die
package
rdl
structural component
disposed
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TW104116137A
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English (en)
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TWI573201B (zh
Inventor
Chin Hock Toh
Yi-Sheng Anthony Sun
xue-ren Zhang
Ravi Kanth Kolan
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United Test & Assembly Ct Lt
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Abstract

本發明揭示一種用於半導體封裝之結構性元件。該結構性元件包含複數個封裝區域以促進(例如)以一晶圓形式封裝晶粒。一封裝區域具有一由一周邊區域包圍之晶粒附接區域。一晶粒係附接於該晶粒附接區域。在一態樣中，該晶粒附接區域具有穿過該結構性元件之該等表面之用於容納一晶粒的開口。所設置之若干穿孔係於該周邊區域內。該結構性元件減少在固化用於囊封該等晶粒之該模製化合物期間可能發生的扭曲。在另一態樣中，該晶粒附接區域不具有一開口。在此等情況中，該結構性元件充當該晶粒與一基板之間之一插入件。

Description

封裝結構性元件
在半導體製造中，複數個矽晶粒一般是平行地形成於一共同基板上且經進一步處理以將該等晶粒囊封於模製化合物中。在完成處理該晶粒基板總成之後，其經切粒以將該總成分離或分成若干個別單元。
提供該囊封所面對的一挑戰在於，由於該模製化合物與該矽晶粒的熱膨脹係數(CTE)之一失配，可能會發生扭曲。當在安裝於諸如一晶圓形式之一共同基板上之矽晶粒之一陣列上實行該囊封時，此問題會變得嚴重，且當該等矽晶粒及該基板之厚度係減小時，此問題甚至會更為嚴重。此外，當被安裝於一共同基板上時，該等矽晶粒於模製期間可能移出其指定之位置。此外，此形式之總成面對的另一挑戰在於需使可安裝於該共同基板上的晶粒的數目最佳化，以便使空間節約量最大化。
基於前文之討論，該等封裝及/或封裝技術係解決上述諸缺點中的一或多者所需要的。
本發明揭示一種裝配裝置之方法。一實施例採取使用一結構性元件，該結構性元件係藉由一黏著劑而被配合於一暫時支撐載體之一第一表面。該結構性元件包含複數個晶粒封裝區域。一晶粒封裝區域具有一被周邊區域包圍之晶粒附接區域。該等晶粒是附接至該結構性元件之該晶粒附接區域。若干穿孔係設置於該結構性元件之該等封裝區 域中。該等穿孔包括一導電性材料且係電性耦合至該等晶粒之若干接合墊。
在另一實施例中揭示一半導體封裝。該封裝包含一具有第一與第二主表面之結構性元件。該結構性元件包含一被周邊區域包圍之晶粒附接區域。該晶粒附接區域容納一有待封裝之晶粒。至少一穿孔係設置於該結構性元件中。該等穿孔延伸穿過該結構性元件的該第一與第二表面。
在又一實施例中，揭示一種裝配一裝置之方法。一實施例採取使用一結構性元件，該結構性元件係藉由一黏著劑而被配合於一暫時支撐載體之一第一表面。該結構性元件包含一晶粒封裝區域。該晶粒封裝區域具有一被周邊區域包圍之晶粒附接區域。一晶粒是附接至該結構性元件之該晶粒附接區域。若干穿孔係設置於該結構性元件之該封裝區域中。該等穿孔包括一導電性材料且係電性耦合至該等晶粒之若干接合墊。
一晶粒附接區域可例如包括一延伸穿過該結構性元件之表面以容納一晶粒於該處之開口。該結構性元件可減少在固化用於囊封該晶粒的該模製化合物期間可發生的扭曲。
在其他實施例中，該晶粒附接區域並不具有一開口。在此情況中，該晶粒附接及周邊區域之頂面可共面。該晶粒是在晶粒附接區域附接至該結構性元件。若干穿孔係設置於該晶粒附接區域中，電性耦合該晶粒之若干接合墊。該結構性元件可充當一平衡該封裝的該等組件之CTE之插入件。
此外，其他態樣在該封裝之頂部與底部包含RDL層。該RDL層為該等表面之頂部與底部提供若干接觸墊。位於該等頂面與底面上的該等接觸墊是藉由該等穿孔而被耦合，其促進該等封裝之堆疊。
參考下述描述及該等隨附圖式，本文所揭示之此等及其他目的， 以及本發明之若干優點及特徵將將變得顯而易見。此外，應理解的是本文所描述之各種實施例之特徵並不互相排斥且可存在於各種組合及改變中。
200‧‧‧結構性元件
210‧‧‧框體
220‧‧‧軌道
230‧‧‧封裝區域
231‧‧‧晶粒附接區域
232‧‧‧周邊區域
340‧‧‧放大部分
350‧‧‧開口
360‧‧‧穿孔
365‧‧‧導電性材料
500‧‧‧半導體封裝
510‧‧‧晶粒
511‧‧‧活性表面
512‧‧‧非活性表面
516‧‧‧晶粒接合墊
525‧‧‧縫隙
535‧‧‧模製化合物
540‧‧‧放大部分
570‧‧‧暫時支撐載體
572‧‧‧黏著劑
580‧‧‧頂部RDL
581‧‧‧底部RDL
585‧‧‧RDL接觸墊
600‧‧‧製程
700‧‧‧製程
800‧‧‧製程
808‧‧‧晶片塊
809‧‧‧底部RDL接觸塊
833‧‧‧下填材料
834‧‧‧下填材料
843‧‧‧模製化合物
874‧‧‧基板
878‧‧‧封裝接觸件
900‧‧‧堆疊封裝
900N‧‧‧第二封裝
902‧‧‧裝置
908‧‧‧封裝接觸件
909‧‧‧晶片塊
1000‧‧‧堆疊體封裝
1100‧‧‧半導體封裝
9001‧‧‧第一封裝
圖1a至1b顯示一結構性元件的一實施例之俯視圖與側視圖；圖1c至1d顯示一結構性元件的另一實施例之俯視圖與側視圖；圖2a至2b顯示一結構性元件的放大部分之若干實施例；圖3a至3b顯示一結構性元件的放大部分之其他實施例；圖4a至4c顯示一採用一結構性元件之製程的一實施例；圖5a至5b至圖7a至7b顯示採用一結構性元件之其他製程；圖8a至8b顯示若干堆疊封裝之實施例；圖9顯示一堆疊封裝之另一實施例；及圖10a至10c顯示若干堆疊封裝之實施例。
在該等圖式中，類似參考字元一般是指貫穿該等不同視圖中的相同部分。同樣，該等圖式並非必須按比例繪製，而是重點一般在於闡釋本發明之原理。在下述描述中，參考下述圖式描述本發明之各種實施例。
若干實施例大體上係關於半導體裝置或積體電路(IC)，其等廣泛使用於諸如，微控制器、有線及無線資料網路連接、消費電子器件等等之應用。特定言之，若干實施例係關於一用於封裝該等IC之結構性元件。
圖1a及1b顯示一結構性元件200的一實施例之簡化俯視圖與側面圖。圖1c及1d顯示一結構性元件200的另一實施例之俯視圖與側面圖。參考圖1a至1d，該結構性元件200促進將複數個晶粒平行地封裝於一共同基板或載體上。該結構性元件200包括一框體210。如圖1a所 顯示，該框體210為一圓形，舉例而言，一晶圓形式。其他幾何形狀亦可有用。舉例而言，如圖1c所顯示，該框體210可具有一正方形或長方形形狀。提供一條形式或其他形式之框體亦可有用。
位於該框體內的是複數個封裝區域230。在一實施例中，一封裝區域包括一被一周邊區域232包圍之晶粒附接區域231。一晶粒附接區域231容納一晶粒。該晶粒附接區域231包括，舉例而言，一開口(舉例而言，參見圖2a及2b中之元件350)。在一實施例中，該開口延伸穿過該框體之頂面與底面。在一實施例中，該等待被封裝之晶粒是設置於該等開口內。該開口之大小及形狀應可容納該等晶粒。舉例而言，該等開口包括一長方形形狀並具有一足以容納該等晶粒之大小。提供非長方形形狀之開口亦可有用。較佳的，該結構性元件包括具有用於封裝相同類型晶粒之相同大小及/或相同形狀之開口。或者，該結構性元件可具有用於封裝不同類型晶粒大小及/或形狀之不同大小及/形狀之開口。
在其他實施例中，該晶粒附接區域231缺少一開口。該結構性元件，舉例而言，可包括一平面元件。對此應用而言，該晶粒是在該晶粒附接區域內附接至該結構性元件200。該結構性元件，舉例而言，充當一夾在一晶粒與一基板之間的一插入件。圖10a顯示該結構性元件200充當一插入件之例示性應用。
在一較佳實施例中，該封裝區域230是被配置成列及行以形成一陣列。該等列及行無需具有相同數量之晶粒附接區域。每列及/行之該等封裝區域數量可取決於例如該等封裝區域之大小、該框體之大小、該框體之形狀或其等之一組合。在一圓形框體之情況中，例如，該等接近於該框體邊緣之行及列的封裝區域之數量可小於此等接近於該框體之中心之數量。
該等封裝區域是藉由在第一與第二方向的軌道220被分離。舉例 而言，該等開口是藉由在該第一與第二方向的軌道220被分離。該第一與第二方向通常係彼此垂直。如所繪示，該x與y方向是彼此垂直。該等軌道220，舉例而言，係與該框體210整合。在一實施例中，該等封裝區域之周邊區域可設置於該等軌道中。應理解的是該等軌道無需為了形成一柵格而在實體上與該晶粒附接區域不同。舉例而言，該等軌道與晶粒附接區域可被整合以形成一平面結構性元件，諸如在該晶粒附接區域缺少開口之情況中。對準線(未顯示)可被提供在該等軌道上。該等對準線係在該第一與第二方向上。舉例而言，該等對準線充當鋸線或鋸道以將該等已封裝晶粒單數化成個別裝置。
多種類型材料可被應用於形成該框體210及該等軌道220。在一實施例中，該框體210包括基板核心材料，包含陶瓷基底材料諸如氧化鋁。其他類型材料，諸如模製化合物或有機材料，包含聚醯胺、雙馬來醯亞胺三氮雜苯(Bismaleimide Triazine，BT)樹脂或FR-4或FR-5材料，亦可有用。該結構性元件之材料，舉例而言，可被選定以平衡該封裝組件之CTE。
可使用各種技術來形成該框體。舉例而言，該框體可藉由加壓模製、層合或模版印刷而形成。亦可應用其他方法來形成該框體。舉例而言，該技術可取決於用於形成該框體之材料的類型。
該框體包括一厚度T。在一實施例中，T等於或大於該等待被囊封晶粒之一厚度。在另一實施例中，T小於該等待被囊封晶粒之厚度。藉由提供具有若干開口之若干晶粒附接區域(該等開口內設置有若干晶粒)，可減少或防止囊封期間該等晶粒之位移。
圖2a至2b顯示一結構性元件200之不同實施例的放大部分340。該放大部分340繪示該結構性元件200的兩個鄰接封裝區域230。一封裝區域230包括一被一周邊區域232包圍的晶粒附接區域231。如所繪示，該晶粒附接區域231包括一開口350。舉例而言，該開口延伸穿過 該結構性元件之表面。在一實施例中，該封裝區域230包括至少一穿孔360。通常，複數個穿孔係設置於該封裝區域內。在一實施例中，該等穿孔係設置於該封裝區域之周邊區域232內。該等穿孔360延伸穿過該框體210之頂面與底面。該等穿孔360可以任何配置被分配在該周邊區域232內。舉例而言，如所顯示，可於包圍該開口之周邊區域內將該等穿孔360配置成一線。穿孔之其他配置亦是有用的。
可藉由各種技術來形成該等穿孔360。此等技術可包含雷射鑽孔或深反應離子蝕刻(DRIE)。其他技術亦是有用的。在一實施例中，該等穿孔360被填充一導電性材料365。舉例而言，該等穿孔被填充銅或銅合金。用其他類型材料填充該等穿孔亦是有用的。在一實施例中，該等穿孔是藉由電鍍來填充。亦可使用其他填充技術來填充該等穿孔。如圖2a所顯示，該等穿孔係以一導電性材料365完全地填充。或者，如圖2b所顯示，該等穿孔係以一導電性材料365填襯。
圖3a至3b顯示一結構性元件200的其他實施例之放大部分440。該放大部分440繪示該結構性元件200之兩個鄰接封裝區域230。一封裝區域例如包括一由一周邊區域232包圍之晶粒附接區域231。在一實施例中，該晶粒附接區域不具有開口。舉例而言，該結構性元件包括一平面元件。
在一實施例中，一封裝區域230包括至少一穿孔360於其中。通常，複數個穿孔360是提供於該封裝區域230內。該等穿孔360可以任何組態被分配在封裝區域230內。舉例而言，該等穿孔360可被均勻的遍及該封裝區域(例如，晶粒附接區域231與周邊區域232兩者)而分配，如圖3a所顯示或者被配置在該周邊區域232內，如圖3b所顯示。以其他組態分配該穿孔360亦可有用。
該等穿孔可延伸穿過該框體210之頂面與底面。該等穿孔360可藉由各種技術被形成。此等技術可包含雷射鑽孔或深反應離子蝕刻 (DRIE)。其他技術亦可有用。
在一實施例中，該等穿孔360係以一導電性材料365填充。舉例而言，該等穿孔360是以銅或銅合金填充。用其他類型材料填充該等穿孔亦可有用。在一實施例中，該等穿孔360是藉由電鍍被填充。該等穿孔亦可使用其他填充技術被填充。如圖3a所顯示，該等穿孔係以一導電性材料365完全的填充。或者，如圖3b所顯示，該等穿孔360係以一導電性材料365填襯。
圖4a至4b繪示一用於裝配一半導體封裝500之製程的一實施例之橫剖面圖。圖4c顯示與該圖4a相對應的製程之一平面視圖。為簡化，該等圖形顯示一描繪兩個鄰接封裝區域230之部分540。
參考圖4a及4c，提供一暫時支撐載體570。該暫時支撐載體570，舉例而言，提供一共同載體，複數個晶粒510安裝至該共同載體以用於裝配。該暫時支撐載體570可由各種類型材料形成。舉例而言，該暫時支撐載體570包括銅、玻璃、矽、石英、藍寶石或任何其他足夠堅硬以承受進一步處理步驟之材料。可對該等晶粒提供機械支撐之其他類型的材料亦可有用。
該暫時支撐載體570之頂面塗覆有一黏著劑572。該黏著劑可為任何在經受一處理時可失去其黏著力之暫時黏著劑。在一實施例中，該黏著劑在被加熱到一臨限溫度時失去其黏著力。一結構性元件200是配合在該暫時支撐載體570之頂面。在一實施例中，該結構性元件200是藉由黏著劑暫時的配合在該頂面。一旦該黏著劑在處理後失去其黏著力，該支撐載體可自該結構性元件分離或去除。
該結構性元件200包括複數個封裝區域230。一封裝區域包含一晶粒附接區域231。該結構性元件促進例如以一晶圓形式封裝晶粒。該結構性元件亦可被組態以促進以其他形式裝配該等晶粒。在一實施例中，該晶粒附接區域包括開口350。提供以一導電性材料365(諸如銅 或銅合金)填充之若干穿孔360。在其他實施例中，該等穿孔之側壁塗覆有導電性材料365。該等穿孔，舉例而言，是設置於該開口350周圍的該結構性元件200(例如，周邊區域232)之軌道部分220內。在一實施例中，該結構性元件在配合至該基板之前是預製有開口及以一導電性材料填充或填襯之穿孔的。在其他實施例中，該等穿孔可在被配合至該基板之後被形成及填充。該等穿孔可在囊封之前或囊封之後被形成。
在一實施例中，晶粒510是設置於該結構性元件200之開口350內。該等晶粒510是藉由黏著劑572暫時地附接在該支撐載體570上。如所顯示，具有晶粒接合墊516設置於其上之該晶粒的活性表面511是被配合在該支撐載體570上。該結構性元件之厚度T，在一實施例中，係與該晶粒之高度相同或大體相同。此導致該結構性元件與晶粒之頂面大約共面。
由於該等晶粒小於該開口，縫隙525便存在於該等晶粒與該等開口側壁之間。在該等晶粒被配合在該支撐載體570表面之後，該等晶粒510是藉由為該等縫隙填充一模製化合物535而被囊封。在一實施例中，該模製化合物535之頂面與該晶粒510及結構性元件200之頂面齊平。該結構性元件，舉例而言，充當一用於填充該等縫隙之模版。該結構性元件200亦可減少囊封期間該等晶粒510之位移。在囊封之後，該模製化合物被固化。固化例如包括將該晶粒總成暴露加熱。
參考圖4c，一頂部再分配層(RDL)是形成於該總成上。舉例而言，該頂部RDL 580是形成於該框體210之頂面及該晶粒510之非活性表面上。該頂部RDL 580，舉例而言，包括導線。RDL接觸墊585是沿著該頂部RDL 580被形成。該導線耦合該RDL接觸墊585於該載該開口350周邊處的穿孔360上。該RDL接觸墊585之圖案舉例而言，與另一封裝之接觸墊或待被堆疊在該頂部RDL上之晶片之圖案相應。該 RDL可藉由各種技術被形成。舉例而言，該RDL可藉由電鍍而被形成。其他形成該RDL之技術亦可有用。
在一實施例中，該暫時支撐載體570在該頂部RDL形成之後自該總成上卸除。卸除可例如藉由加熱該黏著劑直至其失去其黏著力而使該支撐載體570能夠被去除而實現。移除支撐載體570會暴露該等晶粒510的活性表面511。在一實施例中，一底部RDL 581是形成於該總成的底表面。該底部RDL與該結構性元件200之底面以及該晶粒510的活性表面511接觸。該底部RDL 581耦合該晶粒接合墊516於該等穿孔360上，導致該等晶粒墊是被耦合在該頂部RDL 580與頂部RDL接觸墊585上。該頂部與底部RDL促進晶粒或其他封裝之堆疊以減少該裝置之總體底面積。
在該總成完成之後執行一單一化製程以分離該封裝成為個別封裝。在一實施例中，該單一化製程包括沿著鋸線或鋸道鋸切該框體以分離該等晶粒附接區域成為個別封裝。
有利地，該結構性元件200為一晶圓形式或其他形式的晶粒陣列提供結構完成性或機械支撐以防止在該總成處理期間及尤其該囊封與固化製程期間之扭曲。該結構性元件200亦可防止該等晶粒510在囊封期間移出其指定位置。該具有穿孔360之結構性元件200被併入該最終封裝並可充當經由該底部RDL 581、該等穿孔360、及該頂部RDL 580而連接該等晶粒510至該頂部RDL接觸墊585之一途徑。此其後可促進另外的封裝或晶粒堆疊至該封裝上。
圖5a至5b顯示用於裝配一半導體封裝的一製程600的另一實施例之橫剖面圖。該製程與圖4a至4b所描述之類似。不同之處在於該框體210包括一大於該等晶粒510的高度之厚度T。在一實施例中，該填充該等縫隙525之模製化合物535亦覆蓋該等晶粒510之非活性表面512使得該模製化合物535之頂面大約與該框體210之頂面共面。在囊封之 後，該製程如上所描述而繼續。舉例而言，該製程可藉由形成一頂部RDL層580、卸除該基板570、形成底部RDL層581及單一化該總成而繼續。
如所描述，該模製化合物與該框體之頂面齊平。在替換性實施例中，該模製化合物可覆蓋該框體與晶粒兩者。對於其中該模製化合物覆蓋該框體之應用而言，該等穿孔較佳的在囊封後形成。舉例而言，穿孔是穿過該模製化合物與該框體而形成。
圖6a至6b及圖7a至7b顯示用於裝配一半導體封裝的其他製程700與800的橫剖面圖。該等製程與圖4a至4b所描述之類似。不同之處在於該框體210包括一小於該等晶粒510的高度之厚度T。在一實施例中，該填充該等縫隙525之模製化合物535亦覆蓋該框體210使得該模製化合物之頂面大約與該等晶粒510之非活性或頂面共面，如圖6a至6b所顯示。或者，該模製化合物535同時覆蓋該框體210及該等晶粒510，如圖7a至7b所顯示。
對於其中該模製化合物覆蓋該框體之應用而言，該等穿孔360較佳的在囊封後形成。舉例而言，穿孔是穿過該模製化合物與該框體而形成。
在囊封之後，該製程如所描述而繼續。舉例而言，該製程可藉由形成一頂部RDL層580、卸除該基板570、形成底部RDL層581及單一化該總成而繼續。
在又其他實施例中，該結構性元件包括複數個無開口之晶粒附接區域230。舉例而言，該結構性元件200包括一平面元件。穿孔360可被提供在該晶粒附接區域230內以電性地耦合該晶粒510至一基板。
在涉及無開口之晶粒附接區域之應用內，該結構性元件200可充當該晶粒與該基板之間的一插入件以平衡該等元件之間之CTE失配。該結構性元件200亦可作為一分配途徑以耦合一具有特定斜度之晶粒 接合墊於一具有不同或相同斜度之基板接觸墊上。
圖8a至8b顯示堆疊封裝900之實施例。在一實施例中，一堆疊封裝包括複數個組態成一堆疊之晶粒封裝9001-N。如所顯示，該堆疊封裝包括一其上設置有一第二封裝900N(其中N=2)之第一封裝9001。該堆疊封裝可包括藉由上述描述之任何製程形成之若干封裝。舉例而言，該等封裝包含一結構性元件200，其中該模製化合物535填充在具有一晶粒510之該晶粒附接區域內之至少若干縫隙。該等封裝可包含具有穿孔360之頂部與底部RDL層580與581。
在一實施例中，該等封裝包括一與該晶粒具有相同高度之結構性元件。舉例而言，該填充材料具有一頂面，其與該結構性元件及晶粒之頂面齊平或共面。該結構性元件及該模製化合物，舉例而言，包括不同材料，如圖8a所顯示。或者，該結構性元件與該模製化合物包括相同材料，如圖8b所顯示。如所繪示，該堆疊體之若干封裝是為相同類型。在其他實施例中，該堆疊體之封裝可為不同類型之封裝。舉例而言，該等晶粒封裝可包括一上述描述之若干封裝組合，諸如具有不同高度之結構性元件。
圖9顯示一堆疊體封裝1000之另一實施例。如所顯示，該封裝包括一第一封裝900。該第一封裝可為一由上述描述之任何製程所形成。封裝接觸件908是提供在該第一封裝之底部RDL上。該等封裝接觸件，舉例而言，是形成於該底部RDL之接觸墊上。該等封裝接觸件可被組態成一球柵陣列。其他封裝接觸件組態亦可有用。或者，該第一封裝可為一封裝堆疊體，如圖8a至8b所描述。舉例而言，該第一封裝可為一包括N個封裝之封裝堆疊體。在一實施例中，一設置在該第一封裝上之裝置902包括一覆晶封裝。該覆晶包含晶片塊909在其活性表面上。該等晶片塊可被組態成一球柵陣列。晶片塊之其他組態亦可有用。該第一封裝之頂部RDL襯墊之圖案與該裝置的晶片塊之圖案相 應。
該第二封裝之晶片塊909是耦合於該第一封裝之頂部RDL 580。或者，替代一覆晶，該第二封裝可為另一封裝以形成一層疊封裝結構。
參考圖8至9，可理解的是該結構性元件200提供一通路，將該第一封裝內之晶粒耦合於堆疊其上之一第二封裝或晶粒上。在圖8中，該第一封裝9001內之晶粒經由該第一封裝之底部RDL 581、該第一封裝之穿孔360、該第一封裝之頂部RDL 580以及該與第二封裝內之晶粒耦合之第二封裝之底部RDL 581而與該第二封裝900N之晶粒相聯。同樣在圖10中，該結構性元件200自該第一封裝之晶粒提供一類似通路模式給堆疊於其上之裝置或覆晶。
圖10a至10c繪示一半導體封裝1100之其他實施例。參考圖10a，該封裝包括一基板874。舉例而言，該基板874可為一雙馬來醯亞胺三雜氮苯(BT)基板。該基板874包含頂面與底表面。該底表面具有封裝接觸件878。舉例而言，該等封裝接觸件878係組態成一球柵陣列。該等封裝接觸件之其他組態亦可能有用。舉例而言，該頂面包含基板墊，其(舉例而言)藉由內部導電性跡線與該等封裝接觸件耦合。
一晶片封裝800係安裝在該基板874上。在一實施例中，該晶片封裝包括一具有晶片塊808在其活性表面上的覆晶。該等晶片塊係電性地耦合於該等封裝接觸件。在其他實施例中，該晶片封裝可包括圖4a至4b至圖7a至7b所描述中之任何封裝。
根據一實施例，一結構性元件200係設置在該晶片封裝800與該基板874之間。該結構性元件200包括頂部與底部RDL。該頂部RDL包括頂部RDL接觸墊。該頂部RDL接觸墊之圖案(舉例而言)對應於該晶片封裝之晶片塊。該底部RDL包括底部RDL接觸塊809。該底部RDL接觸塊之圖案(舉例而言)對應於該基板墊。該頂部與底部RDL接觸墊係 藉由該穿孔360而耦合。
該晶片封裝係安裝在該結構性元件之頂面上。在該晶片塊與頂部RDL之間可提供一下填材料833。該結構性元件之底部與該基板之頂面耦合。藉由將該結構性元件設置於該基板與該晶片封裝之間，其充當一插入件。該插入件在該基板與該晶片封裝之間提供電連接。在一實施例中，如先前所描述，該結構性元件與晶片封裝可平行地裝配。
在一實施例中，該結構性元件之材料經適當地選定以平衡該晶片封裝、該填充穿孔及該基板之間的CTE失配。該結構性元件之材料可選自(舉例而言)基板核心材料、模製化合物、有機材料或其等之混合物。其他類型材料亦可能有用。
該半導體封裝1100，舉例而言，可藉由一模製化合物843而被囊封，如圖10b所顯示。在其他實施例中，該半導體封裝1100在該插入件與基板之間可具有下填材料834，如圖10c所顯示。
如所描述，該結構性元件之一實施例可由模製化合物材料製成。使用模製化合物作為該結構性元件材料之一優點在於設計該模製化合物特性之靈活度。當設計及選定具有適當的CTE及機械特性時，該模製化合物結構性元件將改善熱循環可靠度。
本發明在不偏離其精神或實質特徵情況下可以其他具體形式體現。因此，上述若干實施例，從各方面而言，應視為闡釋性而非限制本文描述之發明。本發明之範疇因此是藉由附加申請專利範圍而表示，而非藉由先前之描述表示，且所有在申請專利範圍的等效意義及範圍內所出現之變化，均希望包含在該申請專利範圍之內。
200‧‧‧結構性元件
360‧‧‧穿孔
510‧‧‧晶粒
535‧‧‧模製化合物
580‧‧‧頂部RDL
581‧‧‧底部RDL
900‧‧‧堆疊封裝
9001‧‧‧第一封裝
900N‧‧‧第二封裝
908‧‧‧封裝接觸件

Claims (25)

  1. 一種裝配裝置之方法，其包括：提供一具有第一表面及第二表面之暫時支撐載體，該第一表面係預備有一黏著劑；使具有第一及第二主表面之一結構性元件配合於該暫時支撐載體上，該結構性元件包括複數個晶粒封裝區域及設置於該等封裝區域中之若干穿孔，其中一封裝區域包括一由一周邊區域包圍之晶粒附接區域；該等穿孔從該結構性元件之該第一主表面延伸至該第二主表面，其中該等穿孔包含具有頂面及底面之導電性材料，該導電性材料之該頂面及該底面與該結構性元件之該第一及第二主表面共面；將若干晶粒附接於該結構性元件之該等晶粒附接區域；在該結構性元件之該第一主表面上形成一頂部RDL層；及於形成該頂部RDL層之後移除該暫時支撐載體。
  2. 如請求項1之方法，其中：該等晶粒附接區域包括延伸穿過該結構性元件之該等主表面之若干開口；附接該等晶粒包含將該等晶粒設置於該等開口中用於暫時地附接至該暫時支撐載體，其中介於該等晶粒及該等開口之複數個側壁之間存在複數個縫隙；及該等穿孔係設置於包圍該等晶粒附接區域之該等周邊區域中。
  3. 如請求項2之方法，其進一步包括：以一模製化合物囊封該等晶粒，其中該模製化合物填充介於該 等晶粒及該等開口之複數個側壁之間之該等縫隙。
  4. 如請求項3之方法，其中：該結構性元件之一厚度係約等於設置於該開口中之該晶粒之一厚度，其中該模製化合物、晶粒與結構性元件的頂面大約共面；或該結構性元件之一厚度大於設置於該開口中之該晶粒之一厚度，其中該模製化合物及結構性元件的頂面大約共面。
  5. 如請求項4之方法，其包括：在移除該暫時支撐載體之後，於該結構性元件之該第二主表面上形成一底部RDL層，其中該等RDL層及穿孔促進封裝之堆疊。
  6. 如請求項5之方法，其中該頂部及底部RDL層包含分別設置於該等穿孔之該頂面及底面之RDL接觸墊，其中該等頂部之RDL接觸墊藉由該等穿孔耦接至該等底部之RDL接觸墊，且其中該等頂部及底部RDL接觸墊及穿孔係分離且不同之連接特徵。
  7. 如請求項2之方法，其中該等穿孔係設置於複數個鄰近晶粒封裝區域之該等周邊區域中。
  8. 如請求項1之方法，其中：該等晶粒附接區域缺少開口使得該結構性元件之該第一及第二主表面為平面表面；及該等穿孔係設置於該晶粒附接區域及該封裝區域之周邊區域兩者中。
  9. 如請求項8之方法，其包括：在移除該暫時支撐載體之後，於該結構性元件之該第二主平面表面上形成一底部RDL層，其中該等RDL層及穿孔促進封裝之堆疊。
  10. 如請求項9之方法，其中該頂部及底部RDL層包含分別設置於該 等穿孔之該頂面及底面之RDL接觸墊，其中該等頂部之RDL接觸墊藉由該等穿孔耦接至該等底部之RDL接觸墊，且其中該等頂部及底部RDL接觸墊及穿孔係分離且不同之連接特徵。
  11. 如請求項10之方法，其中附接該等晶粒包括將該等晶粒設置於該結構性元件之該等晶粒附接區域之頂部且該結構性元件充當插入件。
  12. 如請求項1至11中任一項之方法，其中該結構性元件包括一用以平衡熱膨脹係數(CTE)之材料。
  13. 如請求項1至11中任一項之方法，其中該結構性元件包含一框體且該複數個晶粒封裝區域係設置於該框體中，該結構性元件促進以一晶圓形式裝配若干裝置。
  14. 一種半導體封裝，其包括：一具有第一及第二主表面之結構性元件，該結構性元件包含：一封裝區域，其具有被一周邊區域包圍之一晶粒附接區域，其中該晶粒附接區域容納一晶粒用於封裝；複數個設置於該封裝區域中且延伸穿過該結構性元件之該第一及第二主表面之穿孔，其中該等穿孔包含具有頂面及底面之導電性材料，該導電性材料之該頂面及該底面與該結構性元件之該第一及第二主表面共面；設置於該結構性元件之該晶粒附接區域中之一晶粒；及設置於該結構性元件之該第一主表面之一頂部RDL層。
  15. 如請求項14之半導體封裝，其中：該結構性元件之該晶粒附接區域包含一開口，該開口延伸穿過該結構性元件之該第一及第二主表面；該晶粒係設置於該開口中，其中介於該晶粒及該開口之側壁之間存在複數個縫隙；且 該等穿孔係設置於包圍該晶粒附接區域之該周邊區域中。
  16. 如請求項15之半導體封裝，其進一步包含一囊封劑，該囊封劑具有填充該等縫隙且囊封該晶粒之一模製化合物。
  17. 如請求項16之半導體封裝，其中該囊封劑及該結構性元件包含相同材料。
  18. 如請求項16之半導體封裝，其中：該結構性元件之一厚度係約等於設置於該開口中之該晶粒之一厚度，其中該模製化合物、晶粒與結構性元件的頂面大約共面；或該結構性元件之一厚度大於設置於該開口中之該晶粒之一厚度，其中該模製化合物及結構性元件的頂面大約共面。
  19. 如請求項18之半導體封裝，其包含：設置於該結構性元件之該第二主表面上之一底部RDL層，其中該頂部及底部RDL層及穿孔促進該半導體封裝之堆疊。
  20. 如請求項19之半導體封裝，其中該頂部及底部RDL層包含分別設置於該等穿孔之該頂面及底面之RDL接觸墊，其中該等頂部之RDL接觸墊藉由該等穿孔耦接至該等底部之RDL接觸墊，且其中該等頂部及底部RDL接觸墊及穿孔係分離且不同之連接特徵。
  21. 如請求項14之半導體封裝，其中：整個結構性元件係藉由一單一絕緣層形成且該晶粒附接區域缺少一開口，使得該結構性元件之該第一及第二主表面係平面表面；該結構性元件包含複數個設置於該第二主平面表面上之接觸塊；該晶粒包含複數個晶片塊，其中該晶粒於該晶粒附接區域中附接至該結構性元件之該第一主平面表面；且 該等穿孔係設置於該晶粒附接區域及該封裝區域之周邊區域兩者中。
  22. 如請求項21之半導體封裝，其包含設置於該結構性元件之該第二主平面表面上之一底部RDL層，其中該頂部及底部RDL層及穿孔促進該半導體封裝之堆疊。
  23. 如請求項22之半導體封裝，其中該頂部及底部RDL層包含分別設置於該等穿孔之該頂面及底面之RDL接觸墊，其中該等頂部之RDL接觸墊藉由該等穿孔耦接至該等底部之RDL接觸墊，且其中該等頂部及底部RDL接觸墊及穿孔係分離且不同之連接特徵。
  24. 如請求項23之半導體封裝，其包含：具有頂面及底面之一封裝基板，其中該底面包含複數個封裝接觸件，其中該結構性元件充當介於該晶粒及該基板之間之一插入件；及一囊封劑，其中該囊封劑覆蓋該結構性元件之該第二主平面表面及至少一部分側邊表面。
  25. 如請求項24之半導體封裝，其中該囊封劑係完全囊封該等接觸塊且填充介於該結構性元件及該封裝基板間一空隙且僅覆蓋該結構性元件之一部分側邊表面之一下填材料。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581676B (zh) * 2016-04-27 2017-05-01 矽品精密工業股份有限公司 電子封裝件及基板結構
TWI830470B (zh) * 2021-11-01 2024-01-21 美商美光科技公司 包括用於散熱之單片矽結構之半導體裝置總成及製造其之方法

Families Citing this family (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
WO2010106543A2 (en) * 2009-03-20 2010-09-23 Proarc Medical Ltd. Methods and devices for urethral treatment
US8803332B2 (en) * 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
US8772087B2 (en) * 2009-10-22 2014-07-08 Infineon Technologies Ag Method and apparatus for semiconductor device fabrication using a reconstituted wafer
TWI497679B (zh) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng 半導體封裝件及其製造方法
TWI401753B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8501544B2 (en) * 2010-08-31 2013-08-06 Stats Chippac, Ltd. Semiconductor device and method of forming adhesive material over semiconductor die and carrier to reduce die shifting during encapsulation
US20120068342A1 (en) * 2010-09-16 2012-03-22 Lee Kevin J Electrically conductive adhesive for temporary bonding
US8313982B2 (en) 2010-09-20 2012-11-20 Texas Instruments Incorporated Stacked die assemblies including TSV die
US8936966B2 (en) 2012-02-08 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8941222B2 (en) * 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US9142502B2 (en) * 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US9245773B2 (en) 2011-09-02 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packaging methods and structures thereof
US9418876B2 (en) 2011-09-02 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of three dimensional integrated circuit assembly
US9312214B2 (en) * 2011-09-22 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having polymer-containing substrates and methods of forming same
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8810024B2 (en) * 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9837303B2 (en) 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9070667B2 (en) * 2013-02-27 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Peripheral electrical connection of package on package
US8941244B1 (en) * 2013-07-03 2015-01-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US20150041993A1 (en) * 2013-08-06 2015-02-12 Infineon Technologies Ag Method for manufacturing a chip arrangement, and a chip arrangement
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US10446335B2 (en) * 2013-08-08 2019-10-15 Zhuhai Access Semiconductor Co., Ltd. Polymer frame for a chip, such that the frame comprises at least one via in series with a capacitor
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150296617A1 (en) * 2014-04-09 2015-10-15 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Interposer frame with polymer matrix and methods of fabrication
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10418298B2 (en) * 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package
US9209046B2 (en) * 2013-10-02 2015-12-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9209154B2 (en) * 2013-12-04 2015-12-08 Bridge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
KR102186203B1 (ko) 2014-01-23 2020-12-04 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US9735129B2 (en) * 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US20150279814A1 (en) * 2014-04-01 2015-10-01 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Embedded chips
CN104270885A (zh) * 2014-05-05 2015-01-07 珠海越亚封装基板技术股份有限公司 具有聚合物基质的插件框架及其制造方法
US20150340308A1 (en) * 2014-05-21 2015-11-26 Broadcom Corporation Reconstituted interposer semiconductor package
US9252138B2 (en) 2014-05-27 2016-02-02 General Electric Company Interconnect devices for electronic packaging assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9881857B2 (en) 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9396999B2 (en) * 2014-07-01 2016-07-19 Freescale Semiconductor, Inc. Wafer level packaging method
KR102108608B1 (ko) 2014-07-11 2020-05-07 인텔 코포레이션 스케일링가능한 패키지 아키텍처 및 연관된 기법과 구성
US9627285B2 (en) * 2014-07-25 2017-04-18 Dyi-chung Hu Package substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
KR102495916B1 (ko) 2015-08-13 2023-02-03 삼성전자 주식회사 반도체 패키지
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
KR101973427B1 (ko) 2015-11-18 2019-04-29 삼성전기주식회사 전자부품 패키지 및 이를 포함하는 전자기기
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
TWI567882B (zh) * 2015-12-15 2017-01-21 財團法人工業技術研究院 半導體元件及其製造方法
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9653391B1 (en) * 2016-06-30 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging structure and manufacturing method thereof
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9761547B1 (en) 2016-10-17 2017-09-12 Northrop Grumman Systems Corporation Crystalline tile
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN110024108A (zh) * 2016-12-31 2019-07-16 英特尔公司 具有加强件的电子封装组装件
CN109300794B (zh) * 2017-07-25 2021-02-02 中芯国际集成电路制造(上海)有限公司 封装结构及其形成方法
KR102525490B1 (ko) * 2017-10-24 2023-04-24 삼성전자주식회사 인쇄 회로 기판, 반도체 패키지 및 반도체 패키지의 제조 방법
EP3557608A1 (en) * 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
US10622321B2 (en) * 2018-05-30 2020-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures and methods of forming the same
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11450641B2 (en) * 2019-09-27 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structure
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
CN111430310A (zh) * 2020-04-02 2020-07-17 华天科技（昆山）电子有限公司 芯片内系统集成封装结构及其制作方法、立体堆叠器件
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JP3743925B2 (ja) * 1997-10-02 2006-02-08 株式会社ミヤコシ 用紙切断装置
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6191477B1 (en) * 1999-02-17 2001-02-20 Conexant Systems, Inc. Leadless chip carrier design and structure
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6489185B1 (en) * 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
KR100368025B1 (ko) * 2000-09-26 2003-01-15 삼성전자 주식회사 중심 지향성 솔더 볼 랜드 타입을 갖는 회로 기판 및 이를이용한 ｂｇａ 패키지
US6582979B2 (en) * 2000-11-15 2003-06-24 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless chip carrier with embedded antenna
US6664617B2 (en) * 2000-12-19 2003-12-16 Convergence Technologies, Ltd. Semiconductor package
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
US6512182B2 (en) * 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
US6916682B2 (en) * 2001-11-08 2005-07-12 Freescale Semiconductor, Inc. Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing
US6717066B2 (en) * 2001-11-30 2004-04-06 Intel Corporation Electronic packages having multiple-zone interconnects and methods of manufacture
FI115285B (fi) * 2002-01-31 2005-03-31 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi
US6861750B2 (en) * 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
AU2003244322A1 (en) * 2002-11-21 2004-06-15 Hitachi, Ltd. Electronic device
US6781242B1 (en) * 2002-12-02 2004-08-24 Asat, Ltd. Thin ball grid array package
TWI241700B (en) * 2003-01-22 2005-10-11 Siliconware Precision Industries Co Ltd Packaging assembly with integrated circuits redistribution routing semiconductor die and method for fabrication
EP1487019A1 (en) * 2003-06-12 2004-12-15 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing thereof
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
FR2861216B1 (fr) * 2003-10-21 2006-02-10 St Microelectronics Sa Boitier semi-conducteur a puce sur plaque-support
DE102004022884B4 (de) * 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
JP4343044B2 (ja) * 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
US7135781B2 (en) * 2004-08-10 2006-11-14 Texas Instruments Incorporated Low profile, chip-scale package and method of fabrication
TWI249796B (en) * 2004-11-08 2006-02-21 Siliconware Precision Industries Co Ltd Semiconductor device having flip chip package
TWI260056B (en) * 2005-02-01 2006-08-11 Phoenix Prec Technology Corp Module structure having an embedded chip
JP4473807B2 (ja) * 2005-10-27 2010-06-02 パナソニック株式会社 積層半導体装置及び積層半導体装置の下層モジュール
US20070212813A1 (en) * 2006-03-10 2007-09-13 Fay Owen R Perforated embedded plane package and method
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US20080157342A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
US20080157316A1 (en) 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
KR100923562B1 (ko) * 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US7868445B2 (en) * 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
CN103178032B (zh) * 2007-07-31 2017-06-20 英闻萨斯有限公司 使用穿透硅通道的半导体封装方法
SG152086A1 (en) * 2007-10-23 2009-05-29 Micron Technology Inc Packaged semiconductor assemblies and associated systems and methods
US7948095B2 (en) * 2008-02-12 2011-05-24 United Test And Assembly Center Ltd. Semiconductor package and method of making the same
US7838975B2 (en) * 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581676B (zh) * 2016-04-27 2017-05-01 矽品精密工業股份有限公司 電子封裝件及基板結構
TWI830470B (zh) * 2021-11-01 2024-01-21 美商美光科技公司 包括用於散熱之單片矽結構之半導體裝置總成及製造其之方法

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