TWI701796B - 半導體封裝結構及其製備方法 - Google Patents

半導體封裝結構及其製備方法 Download PDF

Info

Publication number
TWI701796B
TWI701796B TW108113782A TW108113782A TWI701796B TW I701796 B TWI701796 B TW I701796B TW 108113782 A TW108113782 A TW 108113782A TW 108113782 A TW108113782 A TW 108113782A TW I701796 B TWI701796 B TW I701796B
Authority
TW
Taiwan
Prior art keywords
die
barrier layer
front side
tsv
back side
Prior art date
Application number
TW108113782A
Other languages
English (en)
Other versions
TW202036831A (zh
Inventor
施信益
Original Assignee
南亞科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南亞科技股份有限公司 filed Critical 南亞科技股份有限公司
Application granted granted Critical
Publication of TWI701796B publication Critical patent/TWI701796B/zh
Publication of TW202036831A publication Critical patent/TW202036831A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08057—Shape in side view
    • H01L2224/08058—Shape in side view being non uniform along the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80359—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露提供一種半導體封裝結構。該半導體封裝結構包括一第一晶粒、一第二晶粒以及設置在該第一晶粒和該第二晶粒之間一混合接合結構。該第一晶粒包括一第一前側及相對於該第一前側的一第一背側。該第二晶粒包括一第二前側及相對於該第二前側的一第二背側。該混合接合結構設置在該第一晶粒的該第一背側和該第二晶粒的該第二前側之間。該第一晶粒和該第二晶粒透過該混合接合結構彼此接合。該混合接合結構包括彼此接合的一有機阻擋層和一無機阻擋層。

Description

半導體封裝結構及其製備方法
本申請案主張2019/03/21申請之美國正式申請案第16/360,619號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露關於一種半導體封裝結構及其製備方法，特別是關於一種三維晶片(3DIC)的半導體封裝結構及其製備方法。
半導體元件對於許多現代的應用是不可或缺的。隨著電子技術的進步，半導體元件的尺寸變得越來越小，同時具有更多的功能和更大量的積體電路。由於半導體元件的小型化，晶片對晶片(chip-on-chip)技術廣泛地用於半導體封裝的製造。
在一種方法中，使用至少兩個晶片(或晶粒)的堆疊，以三維(3D)封裝中的形態來形成例如一記憶體元件，如此，相較於其他半導體積體製程，可以生產具有兩倍記憶容量的的產品。除了增加記憶容量外，堆疊封裝也提供了改進的安裝密度和安裝區域的利用效率。由於這些優點，堆疊封裝技術的研究和開發更加速地進行。
半導體元件的製造變的更加複雜。半導體元件由不同的組 件組合在一起，包括具有不同熱特性的各種材料。因為組合了具有不同材料的組件，所以增加了半導體元件的製造複雜性。因此，需要持續改進半導體元件的製程並且解決上述的複雜性。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露提供一種半導體封裝結構，包括一第一晶粒、一第二晶粒以及設置在該第一晶粒和該第二晶粒之間一混合接合結構。該第一晶粒包括一第一前側及相對於該第一前側的一第一背側。該第二晶粒包括一第二前側及相對於該第二前側的一第二背側。該混合接合結構設置在該第一晶粒的該第一背側和該第二晶粒的該第二前側之間。該第一晶粒和該第二晶粒透過該混合接合結構彼此接合。該混合接合結構包括彼此接合的一有機阻擋層和一無機阻擋層。
在一些實施例中，該第一晶粒更包括透過該第一背側暴露的一第一穿矽通孔(TSV)結構和設置在該第一前表面上方的一第一互連結構。在一些實施例中，該第一TSV結構電連接到該第一互連結構。
在一些實施例中，該第一TSV結構包括一突起，延伸到該混合接合結構中。
在一些實施例中，該第一TSV結構的該突起的一高度在約1μm與約5μm之間。
在一些實施例中，該第二晶粒更包括透過該第二背側暴露的一第二穿矽通孔(TSV)結構、設置於該第二前表面上方的一第二互連結 構和透過該第二前側暴露的一接合墊。在一些實施例中，該第二互連結構電連接到第二穿矽通孔結構和該接合墊。
在一些實施例中，該第一晶粒的該第一TSV結構接合到該第二晶粒的該接合墊。
在一些實施例中，該半導體封裝結構更包括設置在該第二晶粒的該第二背側上方的一導電構件。在一些實施例中，該導電構件電連接到該第二TSV結構。
在一些實施例中，該混合接合結構的該有機阻擋層包括苯並環丁烯(BCB)、聚苯並噁唑(PBO)或聚酰亞胺(PI)。
在一些實施例中，該有機阻擋層的一厚度介於約1μm與約5μm之間。
在一些實施例中，該混合接合結構的該無機阻擋層包括氮化矽(SiN)、氮氧化矽(SiON)或碳氮化矽(SiCN)。
在一些實施例中，該無機阻擋層的一厚度介於約0.1μm和約2μm之間。
本揭露另提供一種半導體結構的製備方法，包括下列步驟：提供一第一晶粒，該第一晶粒具有一第一前側、與該第一前側相對的一第一背側和設置在該第一晶粒中的一第一TSV結構。在第一背側去除第一晶粒的一部分以暴露第一TSV結構。在該第一晶粒的該第一背面的上方設置有一機阻擋層。提供一第二晶粒，該第二晶粒具有一第二前側、與該第二前側相對的一第二背側和透過該第二晶粒的第二前側暴露的一接合墊，以及設置在該第二晶粒的該第二前側處上方的一無機阻擋層。接合該第一晶粒的該有機阻擋層和該第二晶粒的該無機阻擋層，接合該第一晶粒 的該第一TSV結構和該第二晶粒的該接合墊。
在一些實施例中，在去除該第一晶粒的該部分之後，該第一TSV結構的一突起從該第一晶粒的該第一背側突出。
在一些實施例中，該第一TSV結構的該突起的一高度在約1μm與約5μm之間。
在一些實施例中，該有機阻擋層的設置更包括步驟：設置該有機阻擋層以包圍第一TSV結構的該突起。在該有機阻擋層上進行一平坦化以暴露該突起的一端面。
在一些實施例中，在該平坦化之後，該突起的該端面和該有機阻擋層的一頂表面共面。
在一些實施例中，該有機阻擋層包含BCB、POB或PI。
在一些實施例中，該無機阻擋層包含SiN、SiON或SiCN。
在一些實施例中，該第二晶粒包括設置在其中的一第二TSV結構。
在一些實施例中，該製備方法更包括步驟：在該第二背側去除該第二晶粒的一部分以暴露該第二TSV結構。在該第二晶粒的該第二背側上設置一導電構件。在一些實施例中，該導電構件電連接到該第二TSV結構。
在本揭露中，提供一種半導體封裝結構的製備方法。根據該製備方法，第一晶粒和第二晶粒透過混合接合結構彼此接合。該混合接合結構包括一有機層和一無機層。值得注意的是，該有機層和該無機層都執行一金屬擴散防止的功能。因此，即使在第一晶粒的第一TSV結構和第二晶粒的接合墊之間出現未對準問題，也可以透過混合接合結構防止金屬 擴散。或者，在一些實施例中，當第一TSV結構與接合墊之間存在尺寸差異時，可透過混合接合結構防止金屬擴散。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:製備方法
101:步驟
102:步驟
103:步驟
104:步驟
105:步驟
200:半導體封裝結構
200':半導體封裝結構
210:第一晶粒
212:基底
214B:第一背側
214F:第一前側
216:第一互連結構
216D:介電層
216L:連接線
216V:連接通孔
218:接合墊
220:無機阻擋層
230:第一TSV結構
231:載體基底
232:突起
233:釋放膜
240:有機阻擋層
250:第二晶粒
250':第二晶粒
252:基底
254B:第二背側
254F:第二前側
256:第二互連結構
256D:介電層
256L:連接線
256V:連接通孔
258:接合墊
260:無機阻擋層
270:第二TSV結構
272:突起
280:混合接合結構
290:導電構件
H:高度
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。圖1是流程圖，例示本揭露一些實施例之半導體封裝結構的製備方法。
圖2A、圖2B、圖2C、圖2D、圖2E、圖2F、圖2G及2H是示意圖，例示本揭露的一些實施例之半導體封裝結構的製備方法的各種製造階段。
圖3A和圖3B是示意圖，例示本揭露的一些實施例之半導體封裝結構的製備方法的各種製造階段。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了實施方式之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於實施方式的內容，而是由申請專利範圍定義。
圖1是流程圖，例示本揭露第一實施例之半導體封裝結構的製備方法10。製備方法10包括步驟101：提供一第一晶粒，該第一晶粒具有一第一前側、與該第一前側相對的一第一背側和設置在該第一晶粒中的一第一TSV結構。製備方法10包括步驟102：在第一背側去除第一晶粒的一部分以暴露第一TSV結構。製備方法10更包括步驟103：在該第一晶粒的該第一背面的上方設置一機阻擋層。製備方法10更包括步驟104：提供一第二晶粒，該第二晶粒具有一第二前側、與該第二前側相對的一第二背側和透過該第二晶粒的第二前側暴露的一接合墊，以及設置在該第二晶粒的該第二前側上方的一無機阻擋層。製備方法10更包括步驟105：接合第一晶粒的有機阻擋層和該第二裸片的該無機阻擋層，結合該第一晶粒的該第一TSV結構和該第二晶粒的接合墊。根據一個或多個實施例，將更進一步描述此半導體封裝結構的製備方法10。
圖2A、圖2B、圖2C、圖2D、圖2E、圖2F、圖2G及2H是示意圖，例示本揭露的一些實施例之半導體封裝結構的製備方法的各種製造階段。參照圖2A，根據步驟101，提供一第一晶粒210。在一些實施例中，第一晶粒210包括基底212，其中基底212由光學微影製程製造預定的功能電路。在一些實施例中，第一晶粒210包括適用於特定應用的各種電路。在一些實施例中，電路包括各種元件，例如電晶體、電容器、電阻器、二極體等。在一些實施例中，第一晶粒210包括各種已知類型的半導體元件中的任一種，以形成加速處理單元(APU)、中央處理單元(CPU)、圖形處理單元(GPU)、微處理器、應用專用積體電路(ASIC)、數字訊號處理器(DSP)、記憶體、動態隨機存取記憶體(DRAM)、NAND快閃記憶體等。在一些實施例中，第一晶粒210包括第一前側214F和相對於第一前側214F的第一背側214B。在一些實施例中，上述的電路或電氣元件被設置在第一晶粒210的第一前側214上，因此第一前側214F被稱為主動側，同時背側214B被稱為非主動側，因為不存在電路或電氣元件。
在一些實施例中，該第一晶粒包括第一互連結構216設置在第一前側214F上。第一互連結構216可包括複數個連接線216L和設置在複數個介電層216D內的複數個連接通孔216V，其中複數個連接線216L透過複數個連接通孔216V電連接。此外，上述電路或電氣組件電連接到第一互連結構216。複數個連接線216L和複數個連接通孔216V可以包括鋁(Al)、銅(Cu)或鎢(W)，但是本揭露不限於此。在一些實施例中，擴散阻擋層(未示出)(例如但不限於氮化鈦(TiN)或氮化鉭(TaN))可設置在複數個連接線/連接通孔216L/216V和複數個介電層216D之間。 複數個電介質層的216D可以是，例如但不限於此，氧化矽(SiO)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)或低介質常數(k)的材料，例如氟矽酸鹽玻璃(FSG)、有機矽酸鹽玻璃(OSG)或其組合。
在一些實施例中，第一晶粒210包括接合墊218，設置在第一前側214F上方，並且電連接到連接線216L。接合墊218提供了更大的表面，做為與其他元件的電連接。在一些實施例中，第一晶粒210可以包括設置在第一正面214F上方的無機阻擋層220。值得注意的是，接合墊218透過無機阻擋層220暴露。在一些實施例中，無機阻擋層220包括氮化矽(SiN)、氮氧化矽(SiON)或碳氮化矽(SiCN)，但是本揭露不限於此。在一些實施例中，無機阻擋層220的厚度在約0.1μm和約2μm之間，但是本揭露不限於此。第一晶粒210A更包括設置在其中的第一TSV結構230。如圖2A所示，第一TSV結構230設置在基底212內並且電連接到該第一互連結構216。
參考圖2B，第一晶粒210可翻轉並且透過第一前側214F黏附載體基底231。在一些實施例中，第一晶粒210透過釋放膜233被臨時附接到載體基底231。在一些實施例中，釋放膜233可以是氟基膜、矽塗佈聚對苯二甲酸乙酯(silicon-coatedpolyethyleneterephthalate)膜、聚甲基戊烯(polymethylpentene)膜、聚丙烯膜(polypropylene)、或其它合適的材料，但是本揭露不限於此。在一些實施例中，載體基底231配置以做為支持一個晶粒、一個晶片或一個封裝。在一些實施例中，載體基底231是半導體基底或晶圓。在一些實施例中，載體基底231是矽晶圓、玻璃晶片等。
參考圖2C，根據步驟102，第一晶粒210的一部分在該第 一背面側214B除去。顯著地，基底212的一部分被移除，使得第一TSV結構的一部分230暴露。在一些實施例中，可以進行一平坦化，例如化學機械拋光(CMP)，並且隨後進行蝕刻製程以移除基底212的該部分。因此，第一TSV結構230的該部分如圖2C所示暴露出。在一些實施例中，第一TSV結構230的該部分從第一晶粒210的第一背側214B突出，該部分被稱為突起232。換句話說，在去除第一晶粒210的該部分之後，第一TSV結構230的突起232從第一晶粒210的第一背面214B突出。此外，第一TSV結構230的突起232的高度H在約1μm和約5μm之間，但是本揭露不限於此。在一些實施例中，第一TSV結構230的突起232的高度H約為3μm，但本揭露不限於此。
參照圖2D和圖2E，根據步驟103，有機阻擋層240設置在第一晶粒210的第一背面214B上。在一些實施例中，有機阻擋層240經設置以包圍第一TSV結構230的突出部232，如圖2D所示。有機阻擋層240的厚度大於第一TSV結構230的突起232的高度H。應當注意，在這樣的實施例中，有機阻擋層240足夠厚以完全包圍突起232。在一些實施例中，有機阻擋層240包括苯並環丁烯(BCB)、聚苯並噁唑(PBO)或聚酰亞胺(PI)，但是本揭露不限於此。參照圖2E，在有機阻擋層240上執行一平坦化以暴露突起232的一端面。值得注意的是，在平坦化之後，突起232的該端面和有機阻擋層240的一頂表面是共面，如圖2E所示。
參照圖2F，根據步驟104，提供一第二晶粒250。在一些實施例中，第二晶粒250包括基底252，其中基底252由光學微影製程製造預定的功能電路。在一些實施例中，第二晶粒250包括適用於特定應用的各種電路。在一些實施例中，電路包括各種元件，例如電晶體、電容器、電 阻器、二極體等。在一些實施例中，第二晶粒250包括各種已知類型的半導體元件中的任一種，形成加速處理單元(APU)、中央處理單元(CPU)、圖形處理單元(GPU)、微處理器、應用專用積體電路(ASIC)、數字訊號處理器(DSP)、記憶體、動態隨機存取記憶體(DRAM)、NAND快閃記憶體等。在一些實施例中第二晶粒250包括第二前側254F和與第二前側254F相對的第二背側254B。在一些實施例中，上述的電路或電氣元件被設置在第二晶粒250的第二前側254上，因此第二前側254F被稱為主動側，同時背側254B被稱為非主動側，因為不存在電路或電氣元件。
在一些實施例中，第二晶粒250包括設置在第二前側254F上第二互連結構256。第二互連結構256可包括複數個連接線256L和設置在複數個介電層256D內的複數個連接通孔256V，其中複數個連接線256L透過複數個連接通孔256V電連接。此外，上述電路或電氣組件電連接到第二互連結構256。用於形成複數個連接線/連接通孔256/256V和第二互連結構250的複數個介電層256D的材料，可以類似於用於形成複數個連接線/連接通孔216L/216V和第一互連結構216的複數個介電層216D的材料，因此為了簡潔起見省略了這些細節。
在一些實施例中，第二晶粒250包括設置在第二前側254F上方並且電連接到連接線256L的接合墊258。接合墊258提供了更大的表面，做為與其他元件的電連接。在一些實施例中，第二晶粒250包括設置在第二前側254F上方的無機阻擋層260。重要的是，接合墊258透過無機阻擋層260暴露。在一些實施例中，無機阻擋層260包括SiN、SiON或SiCN，但是本揭露不限於此。在一些實施例中，無機阻擋層260的厚度在 約01μm和約2μm之間，但是本揭露不限於此。第一晶粒250A更包括設置在其中的第二TSV結構270。如圖2F所示，第二TSV結構270設置在基底252內並且電連接到該第二互連結構256。
參照圖2G，根據步驟105，將第二晶粒250翻轉並接合到第一晶粒210。在一些實施例中，第一晶粒210的接合表面，即有機阻擋層240的頂表面和第一TSV結構230的突出部232的端面，是用電漿或濕式清潔進行預處理。在一些實施例中，第二晶粒250的結合表面，即無機阻擋層260的頂表面和結合墊258的頂表面，也是用電漿或濕式清潔進行預處理。如圖2G所示，第一晶粒210的第一背面214B接合到第二晶粒250的第二前側254F。重要的是，第一TSV結構230(即，第一TSV結構230的突起232)接合到接合墊258，並且有機阻擋層240接合到無機阻擋層260。在一些實施例中，黏合可以在室溫下進行。在其他實施例中，可以透過退火來執行接合。退火的溫度在約200℃和約350℃之間，但是本揭露不限於此。執行退火以加強有機阻擋層240和無機阻擋層260之間的結合。類似地，退火加強了第一TSV結構230的突起232與接合墊258之間的結合。因此，在第一晶粒210的第一背面214B和第二晶粒250的第二前側254F之間形成混合接合結構280，如圖2G所示。換句話說，第一晶粒210和第二晶粒250透過混合接合結構280彼此接合。
參考圖2H，在一些實施例中，去除第二背面254B處的第二晶粒250的一部分以暴露第二TSV結構270。導電構件290設置在第二晶粒250的第二背面254B上方。在一些實施例中，重佈層(RDL)(未示出)可以設置在第二晶粒250的第二背表面254B上，並且導電構件290設置在RDL上方。在一些實施例中，導電構件290是導電凸塊，其包括例如 鍚、銅(Cu)、鎳(Ni)或金(Au)的導電材料，但是本揭露不限於此。在一些實施例中，導電構件290是錫球、球柵陣列(ball grid array BGA)球、控制塌陷高度晶片連(C4)凸塊、微凸塊(micro bump)或柱(pillar)，但是本揭露限於此。在一些實施例中，導電構件290可具有球形、半球形或圓柱形，但是本揭露不限於此。在一些實施例中，第一晶粒210和第二晶粒250可以與載體基底231分離。
仍然參考圖2H，因此，如圖2H所示，獲得半導體封裝結構200。半導體封裝結構200包括透過混合接合結構280彼此接合的第一晶粒210和第二晶粒250。第一晶粒210具有做為主動側的第一前側214F和與第一前側214F相對的第一背側214B。第二晶粒250具有做為主動側的第二前側254F和與第二前側254F相對的第二背側254B。如上所述，第一晶粒210包括設置在第一前側214F上方的第一互連結構216和透過第一背面214B暴露的第一TSV結構230，其中第一TSV結構230電連接到第一互連結構216。類似地，第二晶粒250包括設置在第二前側254F上方的第二互連結構256和透過第二背面254B暴露的第二TSV結構270，其中第二TSV結構270電連接到第二互連結構256。在一些實施例中，第二互連結構256包括接合墊258，如圖2H所示。
仍然參考圖2H，混合接合結構280設置在第一晶粒210的第一背面214B和第二晶粒250的第二前側254F之間。如圖2H所示，混合接合結構280包括彼此接合的有機阻擋層240和無機阻擋層260，以及彼此接合的第一TSV結構230的突起232和接合墊258。有機阻擋層240和無機阻擋層260的材料和厚度可以與上面提到的相同，因此為了簡潔起見省略了這些細節。另外，第一TSV結構230的突出部232延伸到混合接合結構 280中，並且混合接合結構280內的突出部232的高度H在約1μm之間，大約5μm，但是本揭露不限於此。在一些實施例中，混合接合結構280內的突起232的高度H可以是大約3μm，但是本揭露不限於此。
仍然參考圖2H，半導體封裝結構200更包括設置在第二晶粒250的第二背面254B上方的導電構件290，其中導電構件290電連接到第二TSV結構270。形成導電構件290以提供與外部源的電連接。
根據本揭露提供的製備方法10，混合接合結構280形成在第一晶粒210和第二晶粒250之間。換句話說，透過形成混合接合結構280，第一晶粒210和第二晶粒250牢固地彼此接合。如圖2H所示，在一些實施例中，第一TSV結構230的突起232與接合墊258之間可存在面積差異，因此突起232或接合墊258可與阻擋層接觸。例如，由於未對準問題，突起232和/或接合墊258可以與阻擋層接觸。根據本揭露的實施例，突起232可以與接合墊258和無機阻擋層260接觸，並且可以透過無機阻擋層260防止金屬擴散。類似地，接合墊258可以與突起232和有機阻擋層240接觸，並且可以透過有機阻擋層240防止金屬擴散。
圖3A和圖3B是例示本揭露的一些實施例之半導體封裝結構的製備方法的各種製造階段的示意圖。應該理解的是，圖2A至圖2H和圖3A至圖3B中的類似特徵可以包括類似的材料和參數，因此為了簡潔起見省略了這些細節。
參照圖3A，在一些實施例中，可以在第二晶粒250上執行步驟102至步驟105。例如，根據步驟102，在第二背面254B移除第二晶粒250的一部分。重要的是，移除基底212的一部分，使得暴露第二TSV結構270的一部分。在一些實施例中，第二TSV結構272的一部分從第二晶 粒254B的第二背面254B突出，因此這種部分被稱為突起272。換句話說，在去除第二晶粒250的一部分之後，第二TSV結構270的突起272從第二晶粒250的第二背面254B突出。此外，第二TSV結構270的突起272的高度H在約1μm和約5μm之間，但是本揭露不限於此。在一些實施例中，第二TSV結構270的突起272的高度H約為3μm，但本揭露不限於此。
接下來，根據步驟103，在第二背面244B將有機阻擋層240設置在第二晶粒250上方。在一些實施例中，有機阻擋層240經設置以包圍第二TSV結構270的突起272。在平坦化之後，突起272的端表面和有機阻擋層240的頂表面是共面的，如圖3A所示。
在一些實施例中，可以根據步驟104提供另一個第二晶粒250'並且根據步驟105結合到第二晶粒250。第二晶粒250'可以是晶粒、晶片或封裝。應當理解，第二晶粒250'的元件可以與第一晶粒210或第二晶粒250的元件類似，因此為了簡潔起見省略了這些細節。
在一些實施例中，可以根據產品要求重複步驟102至步驟105。例如，如圖3B所示，可以形成半導體封裝結構200'。半導體封裝結構200'包括複數個晶粒210、250和250'。晶粒210、250和250'是前後黏合的。此外，晶粒210、250和250'透過混合接合結構280彼此接合。用於形成混合接合結構280的步驟可以與上述步驟類似，因此為了簡潔起見省略了這些細節。在一些實施例中，在堆疊和接合晶粒210,250和250'之後，移除第二背側254B處的最頂部第二晶粒250'的一部分以暴露第二TSV結構270，並且導電構件290設置在第二晶粒250'的第二背面254B上。因此，獲得半導體封裝結構200'。在一些實施例中，在形成導電構件290之後，半導體封裝結構200'可以與載體基底231分離。
根據本揭露提供的製備方法10，混合接合結構280形成在每對相鄰的晶粒210、250和250'之間。換句話說，透過形成混合接合結構280，晶粒210、250和250'彼此牢固地接合。根據本揭露的實施例，可以透過混合接合結構280的有機阻擋層240和無機阻擋層260來防止由於表面積差異和/或由於未對準引起的金屬擴散。
本揭露提供一種半導體封裝結構的製備方法。根據該製備方法，第一晶粒和第二晶粒透過混合接合結構彼此接合。該混合接合結構包括一有機層和一無機層。值得注意的是，該有機層和該無機層都執行一金屬擴散防止的功能。因此，即使在第一晶粒的第一TSV結構和第二晶粒的接合墊之間出現未對準問題，也可以透過混合接合結構防止金屬擴散。或者，在一些實施例中，當第一TSV結構與接合墊之間存在尺寸差異時，可透過混合接合結構防止金屬擴散。
本揭露提供一種半導體封裝結構，包括一第一晶粒、一第二晶粒以及設置在該第一晶粒和該第二晶粒之間一混合接合結構。該第一晶粒包括一第一前側及相對於該第一前側的一第一背側。該第二晶粒包括一第二前側及相對於該第二前側的一第二背側。該混合接合結構設置在該第一晶粒的該第一背側和該第二晶粒的該第二前側之間。該第一晶粒和該第二晶粒透過該混合接合結構彼此接合。該混合接合結構包括彼此接合的一有機阻擋層和一無機阻擋層。
本揭露另提供一種半導體結構的製備方法，包括下列步驟：提供一第一晶粒，該第一晶粒具有一第一前側、與該第一前側相對的一第一背側和設置在該第一晶粒中的一第一TSV結構。在第一背側去除第一晶粒的一部分以暴露第一TSV結構。在該第一晶粒的該第一背面的上方 設置有一機阻擋層。提供一第二晶粒，該第二晶粒具有一第二前側、與該第二前側相對的一第二背側和透過該第二晶粒的第二前側暴露的一接合墊，以及設置在該第二晶粒的該第二前側上方的一無機阻擋層。接合該第一晶粒的該有機阻擋層和該第二晶粒的該無機阻擋層，接合該第一晶粒的該第一TSV結構和該第二晶粒的該接合墊。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
200':半導體封裝結構
210:第一晶粒
214F:第一前側
231:載體基底
233:釋放膜
250:第二晶粒
250':第二晶粒
254B:第二背側
280:混合接合結構
290:導電構件

Claims (18)

  1. 一種半導體封裝結構，包括：一第一晶粒，包括一第一前側以及相對於該第一前側的一第一背側；一第二晶粒，包括一第二前側及相對於該第二前側的一第二背側；一混合接合結構，設置在該第一晶粒的該第一背側和該第二晶粒的該第二前側之間，其中該第一晶粒和該第二晶粒透過該混合接合結構彼此接合，並且該混合接合結構包括彼此接合的一有機阻擋層和一無機阻擋層；其中該第一晶粒更包括：一第一穿矽通孔(TSV)結構，透過該第一背側暴露，以及一第一互連結構，設置在該第一前側的上方，其中該第一TSV結構電連接到第一互連結構；其中該第一TSV結構包括一突起，延伸到該混合接合結構中。
  2. 如請求項1所述的半導體封裝結構，其中該第一TSV結構的該突起的一高度在約1微米(μm)與約5μm之間。
  3. 如請求項1所述的半導體封裝結構，其中該第二晶粒更包括：一第二穿矽通孔(TSV)結構，透過該第二背側暴露，以及一第二互連結構，設置在該第二前側的上方；以及一接合墊，透過該第二前側暴露， 其中該第二互連結構電連接到第二TSV結構和該接合墊。
  4. 如請求項3所述的半導體封裝結構，其中該第一晶粒的該第一TSV結構接合到該第二晶粒的該接合墊。
  5. 如請求項3所述的半導體封裝結構，更包括設置在該第二晶粒的該第二背面上方的一導電構件，該導電構件電連接到該第二TSV結構。
  6. 如請求項1所述的半導體封裝結構，其中該混合接合結構的該有機阻擋層包括苯並環丁烯(BCB)、聚苯並噁唑(PBO)或聚酰亞胺(PI)。
  7. 如請求項1所述的半導體封裝結構，其中該有機阻擋層的一厚度介於約1μm與約5μm之間。
  8. 如請求項1所述的半導體封裝結構，其中該混合接合結構的該無機阻擋層包括氮化矽(SiN)、氮氧化矽(SiON)或碳氮化矽(SiCN)。
  9. 如請求項1所述的半導體封裝結構，其中該有機阻擋層的一厚度介於約1μm與約5μm之間。
  10. 一種半導體封裝結構的製備方法，包括：提供一第一晶粒，該第一晶粒具有一第一前側、與該第一前側相對的一第一背側和設置在該第一晶粒中的一第一TSV結構； 在第一背側去除第一晶粒的一部分以暴露第一TSV結構；在該第一晶粒的該第一背面的上方設置一機阻擋層；提供一第二晶粒，該第二晶粒具有一第二前側、與該第二前側相對的一第二背側和透過該第二晶粒的第二前側暴露的一接合墊，以及設置在該第二晶粒的該第二前側上方的一無機阻擋層；以及接合該第一晶粒的該有機阻擋層和該第二晶粒的該無機阻擋層，接合該第一晶粒的該第一TSV結構和該第二晶粒的該接合墊。
  11. 如請求項10所述的製備方法，其中在去除該第一晶粒的該部分之後，該第一TSV結構的一突起從該第一晶粒的該第一背側突出。
  12. 如請求項11所述的製備方法，其中該第一TSV結構的該突起的一高度在約1微米(μm)與約5μm之間。
  13. 如請求項11所述的製備方法，其中該有機阻擋層的設置更包括：設置該有機阻擋層以包圍第一TSV結構的該突起；以及在該有機阻擋層上進行一平坦化以暴露該突起的一端面。
  14. 如請求項13所述的製備方法，其中在該平坦化之後，該突起的該端面和該有機阻擋層的一頂表面共面。
  15. 如請求項10所述的製備方法，其中該有機阻擋層包含BCB、POB或PI。
  16. 如請求項10所述的製備方法，其中該無機阻擋層包含SiN、SiON或SiCN。
  17. 如請求項10所述的製備方法，其中該第二晶粒包括設置在其中的一第二TSV結構。
  18. 如請求項17所述的製備方法，更包括：在該第二背側去除該第二晶粒的一部分以暴露該第二TSV結構；以及在該第二晶粒的該第二背側上方設置一導電構件，其中該導電構件電連接到該第二TSV結構。
TW108113782A 2019-03-21 2019-04-19 半導體封裝結構及其製備方法 TWI701796B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/360,619 2019-03-21
US16/360,619 US10910357B2 (en) 2019-03-21 2019-03-21 Semiconductor package including hybrid bonding structure and method for preparing the same

Publications (2)

Publication Number Publication Date
TWI701796B true TWI701796B (zh) 2020-08-11
TW202036831A TW202036831A (zh) 2020-10-01

Family

ID=72513979

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108113782A TWI701796B (zh) 2019-03-21 2019-04-19 半導體封裝結構及其製備方法

Country Status (3)

Country Link
US (1) US10910357B2 (zh)
CN (1) CN111725147A (zh)
TW (1) TWI701796B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10903142B2 (en) * 2018-07-31 2021-01-26 Intel Corporation Micro through-silicon via for transistor density scaling
US11417628B2 (en) 2018-12-26 2022-08-16 Ap Memory Technology Corporation Method for manufacturing semiconductor structure
US11189563B2 (en) * 2019-08-01 2021-11-30 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US11410929B2 (en) * 2019-09-17 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11239238B2 (en) 2019-10-29 2022-02-01 Intel Corporation Thin film transistor based memory cells on both sides of a layer of logic devices
KR20230013278A (ko) * 2020-09-02 2023-01-26 양쯔 메모리 테크놀로지스 씨오., 엘티디. Xtacking 아키텍처의 패드 아웃 구조
US11817442B2 (en) * 2020-12-08 2023-11-14 Intel Corporation Hybrid manufacturing for integrated circuit devices and assemblies
US11756886B2 (en) 2020-12-08 2023-09-12 Intel Corporation Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures
CN113510538A (zh) * 2021-06-23 2021-10-19 闳康技术检测(上海)有限公司 一种多层rdl去层工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201320298A (zh) * 2011-10-07 2013-05-16 Freescale Semiconductor Inc 堆疊半導體裝置
TW201413913A (zh) * 2012-09-28 2014-04-01 Taiwan Semiconductor Mfg Co Ltd 半導體封裝與其形成方法
TW201519383A (zh) * 2013-11-07 2015-05-16 Sk Hynix Inc 半導體裝置，製造其之方法，包含其之記憶卡以及包含其之電子系統

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2460180B1 (en) * 2009-07-30 2020-02-19 QUALCOMM Incorporated System-in packages
US8159060B2 (en) * 2009-10-29 2012-04-17 International Business Machines Corporation Hybrid bonding interface for 3-dimensional chip integration
EP2605273A3 (en) * 2011-12-16 2017-08-09 Imec Method for forming isolation trenches in micro-bump interconnect structures and devices obtained thereof
US9142517B2 (en) * 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US10163864B1 (en) * 2017-08-16 2018-12-25 Globalfoundries Inc. Vertically stacked wafers and methods of forming same
KR102541564B1 (ko) * 2018-10-04 2023-06-08 삼성전자주식회사 반도체 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201320298A (zh) * 2011-10-07 2013-05-16 Freescale Semiconductor Inc 堆疊半導體裝置
TW201413913A (zh) * 2012-09-28 2014-04-01 Taiwan Semiconductor Mfg Co Ltd 半導體封裝與其形成方法
TW201519383A (zh) * 2013-11-07 2015-05-16 Sk Hynix Inc 半導體裝置，製造其之方法，包含其之記憶卡以及包含其之電子系統

Also Published As

Publication number Publication date
US10910357B2 (en) 2021-02-02
US20200303361A1 (en) 2020-09-24
TW202036831A (zh) 2020-10-01
CN111725147A (zh) 2020-09-29

Similar Documents

Publication Publication Date Title
TWI701796B (zh) 半導體封裝結構及其製備方法
US10971371B2 (en) Multi-chip structure and method of forming same
TWI681466B (zh) 半導體結構及積體電路封裝的形成方法
US20210125968A1 (en) 3DIC Formation with Dies Bonded to Formed RDLs
US9520333B1 (en) Wafer level package and fabrication method thereof
TWI437679B (zh) 半導體裝置及其製造方法
TWI741538B (zh) 半導體元件及其形成方法
US20210305214A1 (en) Package
TWI695432B (zh) 封裝及其形成方法
US11309289B2 (en) Integrated circuit package having heat dissipation structure
US9190345B1 (en) Semiconductor devices and methods of manufacture thereof
TW201715674A (zh) 半導體元件的形成方法
TW202013658A (zh) 積體電路封裝及其形成方法
US11658069B2 (en) Method for manufacturing a semiconductor device having an interconnect structure over a substrate
TW201725670A (zh) 扇出晶圓級封裝及其製作方法
US20190244919A1 (en) Semiconductor Devices and Methods of Manufacture Thereof
TWI744071B (zh) 積體電路裝置及積體電路裝置的封裝方法
US20220375793A1 (en) Semiconductor Device and Method
TW202310219A (zh) 半導體封裝
TW202213686A (zh) 具有中介物之半導體封裝
TW202412231A (zh) 晶粒結構及其形成方法
TW202412230A (zh) 晶粒結構及其形成方法
US20230260941A1 (en) Semiconductor Device and Method
TWI776646B (zh) 積體電路封裝體及其形成方法
TWI750069B (zh) 具有在凸塊墊下方之緩衝件的半導體結構與其製備方法