TW201519383A - 半導體裝置，製造其之方法，包含其之記憶卡以及包含其之電子系統 - Google Patents

半導體裝置，製造其之方法，包含其之記憶卡以及包含其之電子系統 Download PDF

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Publication number
TW201519383A
TW201519383A TW103112486A TW103112486A TW201519383A TW 201519383 A TW201519383 A TW 201519383A TW 103112486 A TW103112486 A TW 103112486A TW 103112486 A TW103112486 A TW 103112486A TW 201519383 A TW201519383 A TW 201519383A
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Taiwan
Prior art keywords
electrode
substrate
layer
semiconductor device
plug
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TW103112486A
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English (en)
Inventor
Sung-Su Park
Jong-Kyu Moon
Wan-Choon Park
Bae-Yong Kim
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Sk Hynix Inc
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Publication of TW201519383A publication Critical patent/TW201519383A/zh

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Abstract

本發明提供一種半導體裝置。所述半導體裝置包括：直通電極，其穿透基板，使得所述直通電極的端部從基板的表面突出；鈍化層，其覆蓋所述基板的表面並且定義了暴露所述直通電極的端部的插插塞洞；以及阻障插塞，其填充所述插插塞洞。本發明進一步提供了相關的方法、相關的記憶卡及相關電子系統。

Description

半導體裝置，製造其之方法，包含其之記憶卡以及包含其之電子系統 【相關申請案的交叉參考】
本申請案基於35 U.S.C 119(a)主張2013年11月7日於韓國知識產權局所提申的韓國申請案第10-2013-0134855號的優先權，其通過全文引用將其整體併入本文中。
本發明的實施例涉及封裝技術，並且更具體地為，具有通孔結構的半導體裝置、製造其之方法、包含其之記憶卡以及包含其之電子系統。
在電子系統中採用的半導體裝置可以包括各種電子電路元件，並且所述電子電路元件可以被整合於半導體基板中及/或半導體基板上以構成半導體裝置(也稱為半導體晶片或半導體晶粒)。記憶體半導體晶片可以採用在電子系統中。在包括記憶體半導體晶片的半導體裝置被採用在電子系統中之前，半導體裝置可以被囊封以具有封裝形式。這些半導體封裝也可以採用在電子系統中，例如，電腦、行動通訊系統或數據存儲介質。
隨著諸如智慧型手機的行動系統變得更輕且更小，在形成通 訊系統中使用的半導體封裝也在不斷地縮小。此外，大電容的半導體封裝隨著多功能行動通訊系統的發展而漸增地需要。在這方面，已經嘗試許多努力而把多個半導體裝置投入在單一個封裝中，以提供諸如堆疊封裝的大電容的半導體封裝。此外，穿透半導體晶片的直通矽晶穿孔(through silicon via，TSV)電極已被提出以實現互連結構，其讓半導體晶片在單一個堆疊封裝中彼此電連接。
各個實施例指向具有通孔結構的半導體裝置、製造其之方法、包含其之記憶卡以及包含其之電子系統。
根據一些實施例，一種半導體裝置包括：通過穿透電極的基板，使得所述直通電極的端部從基板的表面突出，覆蓋所述基板的表面，並提供一個插塞的鈍化層，其所公開的直通電極的端部，並且一個阻障插塞子充填插塞。直通電極的端部的頂表面對應於插塞的底面。
根據進一步的實施例中，一種半導體裝置包括：第一電極，通過穿透第一基板，使得所述第一通電極的端部從所述第一基板上，覆蓋所述第一基板的表面上的鈍化層的表面突出，並提供了直通電極露出的第一端部的插塞，阻障插塞子充填插塞，第二基板層疊在所述第一基板上，並且連接到所述第二基板並與所述阻障插塞的連接端子。第一通電極的端部的頂表面對應於所述火花插塞的底面。
根據進一步的實施例中，一種半導體裝置包括：第一電極，通過穿透第一基板，使得所述第一通電極的端部從所述第一基板上，覆蓋所述第一基板的表面上的鈍化層的表面突出，並提供了所公開的第一直通 電極，阻障插塞子充填插塞，第二基板層疊在所述第一基板上，並且連接到所述第二基板的連接端子的端部的頂面上，結合阻障層的插塞插塞。在鈍化層的厚度大於所述第一通電極的端部的高度。該鈍化層包括覆蓋所述第一基板的表面，並直通電極和阻障插塞的側壁延伸到所述第一端部的側壁上的絕緣層。
根據進一步的實施例中，一種製造半導體裝置的方法包括：形成直通電極穿透基板，使得所述直通電極的端部從基板的表面突出，形成覆蓋的表面上的鈍化層基板，並提供一個插塞露出的直通電極的端部，並且形成阻障插塞子充填插塞。直通電極的端部的頂表面對應於插塞的底面。
根據進一步的實施例中，記憶卡包括一個半導體裝置。該半導體裝置包括一個直通電極穿透基板，使得所述直通電極的端部從基板的表面突出，覆蓋所述基板的表面，並提供一個公開的直通電極的端部的插塞孔的鈍化層和阻障插塞子充填插塞。直通電極的端部的頂表面對應於插塞的底面。
根據進一步的實施例中，記憶卡包括一個半導體裝置。該半導體裝置包括：第一，穿透的第一基底上，使得第一通電極的端部從所述第一基板上，覆蓋所述第一基板的表面，並提供一個公開的一端的插塞孔的鈍化層的表面突出第一直通電極的一部分，阻障插塞子充填插塞，第二基板層疊在所述第一基板上，並且連接到所述第二基板並與所述阻障插塞的連接端子。第一通電極的端部的頂表面對應於所述火花插塞的底面。
根據進一步的實施例中，記憶卡包括一個半導體裝置。該半 導體裝置包括：第一，直通電極穿透的第一基底上，使得第一通電極的端部從所述第一基板上，覆蓋所述第一基板的表面，並提供一個公開的頂插塞的鈍化層的表面突出第一直通電極，阻障插塞子充填插塞，第二基板層疊在所述第一基板上，並且連接到所述第二基板並與所述阻障插塞的連接端子的端部的表面上。在鈍化層的厚度大於所述第一通電極的端部的高度。該鈍化層包括覆蓋所述第一基板的表面，並直通電極和阻障插塞的側壁延伸到所述第一端部的側壁上的絕緣層。
根據進一步的實施例中，一種電子系統包括一個半導體裝置。該半導體裝置包括一個直通電極穿透基板，使得所述直通電極的端部從基板的表面突出，覆蓋所述基板的表面，並提供一個公開的直通電極的端部的插塞孔的鈍化層和阻障插塞子充填插塞。直通電極的端部的頂表面對應於插塞的底面。
根據進一步的實施例中，一種電子系統包括一個半導體裝置。該半導體裝置包括：第一，直通電極穿透的第一基底上，使得第一通電極的端部從所述第一基板上，覆蓋所述第一基板的表面，並提供一個公開的一端的插塞孔的鈍化層的表面突出第一直通電極的一部分，阻障插塞子充填插塞，第二基板層疊在所述第一基板上，並且連接到所述第二基板並與所述阻障插塞的連接端子。第一通電極的端部的頂表面對應於所述火花插塞的底面。
根據進一步的實施例中，一種電子系統包括一個半導體裝置。該半導體裝置包括：第一，直通電極穿透的第一基底上，使得第一通電極的端部從所述第一基板上，覆蓋所述第一基板的表面，並提供一個公 開的頂插塞的鈍化層的表面突出第一直通電極，阻障插塞子充填插塞，第二基板層疊在所述第一基板上，並且連接到所述第二基板並與所述阻障插塞的連接端子的端部的表面上。在鈍化層的厚度大於所述第一通電極的端部的高度。該鈍化層包括覆蓋所述第一基板的表面，並直通電極和阻障插塞的側壁延伸到所述第一端部的側壁上的絕緣層。
10‧‧‧半導體裝置
11‧‧‧部分
12‧‧‧互連結構
13‧‧‧半導體晶片
14‧‧‧半導體晶片
15‧‧‧半導體晶片
16‧‧‧半導體晶片
20‧‧‧半導體裝置
100‧‧‧半導體基板
101‧‧‧第二表面
102‧‧‧第二半導體基板
103‧‧‧第一表面
104‧‧‧第三表面
110‧‧‧電晶體
130‧‧‧層間絕緣層
140‧‧‧內部互連結構
150‧‧‧連接襯墊
200‧‧‧直通電極
202‧‧‧第二直通電極
210‧‧‧絕緣層
220‧‧‧背側端部
221‧‧‧頂表面
223‧‧‧最初頂表面
240‧‧‧背側端部
241‧‧‧頂表面
300‧‧‧第一鈍化層
301‧‧‧孔洞
400‧‧‧導電凸塊
401‧‧‧導電凸塊
410‧‧‧界面層
411‧‧‧界面層
430‧‧‧導電黏著層
431‧‧‧導電黏著層
450‧‧‧連接端子
500‧‧‧第二鈍化層
501‧‧‧頂表面
505‧‧‧插塞孔洞
510‧‧‧第一絕緣層
511‧‧‧保護環部
530‧‧‧第二絕緣層
600‧‧‧阻障插塞
610‧‧‧第一金屬層
630‧‧‧第二金屬層
700‧‧‧黏著絕緣層
800‧‧‧黏著劑
900‧‧‧載體基板
1800‧‧‧記憶卡
1810‧‧‧記憶體
1820‧‧‧記憶體控制器
1830‧‧‧主機
2710‧‧‧電子系統
2711‧‧‧控制器
2712‧‧‧輸入/輸出單元
2713‧‧‧記憶體
2714‧‧‧介面
2715‧‧‧匯排流
本發明的具體實施例將在所附圖式和伴隨的詳細描述中變得更加顯而易見，其中：圖1是說明根據本發明的一些實施例的半導體裝置的橫截面視圖；圖2是說明圖1的部分“11”的放大橫截面視圖；圖3是說明根據本發明的一些實施例的半導體裝置之間的互連結構的放大橫截面視圖；圖4是說明根據本發明的一些實施例的半導體裝置的疊層結構的橫截面視圖；圖5至圖11是說明根據本發明的一些實施例的製造半導體裝置的方法的橫截面視圖；圖12是說明根據本發明的一些實施例的半導體裝置的直通電極的橫截面視圖；圖13是說明採用包括根據一實施例的半導體裝置的記憶卡的電子系統的一範例的方塊圖；以及圖14是說明包括根據一實施例的半導體裝置的一種電子系 統的一範例的方塊圖。
應當理解的是，雖然術語第一、第二、第三等可以用於本文來描述各種元件，但這些元件不應該受這些術語的限制。這些術語僅用於區別一個元件與另一個元件。因此，在一些實施例中，第一元件可以在其它實施例中被稱為第二元件而不脫離本發明概念的教導。
還應當理解的是，當一個元件被稱為在另一元件“上”、“上方”、“下”或者“下方”時，它可以直接在另一元件之“上”、“上方”、“下”或者“下方”，或者中間元件也可以存在。因此，諸如“上”，“上方”，“下方”，或在本文中所用的術語“上”、“上方”、“下”或者“下方”僅用於描述具體實施例的目的，並非旨在限制本公開的範圍。
應當進一步理解的是，當元件被稱為“連接”或“耦合”到另一元件時，它可以直接連接或耦合到另一元件或者可以有中間元件存在。與此相反地，當元件被稱為“直接連接”或“直接耦合”到另一元件時，不存在中間元件。用於描述元件或層之間的關係的其它詞語應該以類似的方式來解釋。半導體基板可以具有對應於其中的電晶體和構成電子電路的內部互連線所整合的一區域中的主動層，以及半導體晶片可以藉由使用晶粒切割製程而將具有晶片的半導體基板分離成多個片塊所得到。
半導體晶片可以對應於記憶體晶片或邏輯晶片。記憶體晶片可以包括整合在半導體基板上及/或中的動態隨機存取記憶體(DRAM)電路、靜態隨機存取記憶體(SRAM)電路、快閃電路、磁性隨機存取記憶體(MRAM)電路、電阻性隨機存取記憶體(ReRAM)電路、鐵電隨機存取 記憶體(FeRAM)電路或相變隨機存取記憶體(PcRAM)電路。邏輯晶片可以包括與半導體基版整合的邏輯電路。在一些情況下，本文所用的術語“半導體基板”可以被理解為半導體晶片或者有積體電路被形成於其中的半導體晶粒。
參考圖1所示，半導體裝置10可以包括半導體基板100以及垂直穿透半導體基板100的直通電極200。直通電極200的背側端部220可以延伸以自所述半導體基板100的第一表面103突出。直通電極200可以對應於通過矽晶穿孔(TSV)。也就是說，每個直通電極200可以是導電通孔，其從半導體基板100的第一表面103朝向半導體基板100的第二表面101延伸。第二表面101可以對應於半導體基板100的前側表面並且第一表面103可以對應於半導體基板100的背側表面。半導體基板100可以由諸如矽的半導體材料所製成。半導體基板100可以是晶圓或從晶圓分離的個別的晶片。
半導體基板100的第二表面101可以是相鄰於積體電路所形成的主動層的表面，並且第一表面103可以是相對於第二表面101的表面。電路元件，構成積體電路的諸如電晶體110的電路元件可以形成在主動層中及/或上，以及層間絕緣層130個內部互連結構140可以被佈置在第二表面101上。內部互連結構140可以具有多層結構。電晶體110可以形成以作為在半導體裝置10是記憶體裝置的實施例中的用於記憶體單元的單元電晶體來運作，或者作為在半導體裝置10是諸如邏輯裝置的非記憶體裝置的實施例中的構成邏輯電路的電路元件來運作。
內部互連結構140可以包括互連線和連接通孔，以提供電連接結構。內部互連結構140可以被電連接到設置在或層間絕緣層130中或上的 連接襯墊150，以及作為外部連接端子的導電凸塊400可以設置在各自的連接襯墊150上。換句話說，在一個實施例中，導電凸塊400是連接堆疊的基板的連接端子450的元件。連接端子450的其它組件可以包括界面層410和導電黏著層430。在其它實施例中，連接端子的其他配置是可能的。
導電凸塊400可以對應於電連接到直通電極200的正面凸塊。對應於絕緣層的第一鈍化層300可以被佈置在相對於半導體基板100的層間絕緣層130的表面上。第一鈍化層300可以包括多個孔洞301，其暴露了連接襯墊150，並且導電凸塊400可以通過孔洞301而連接到連接襯墊150。
直通電極200可以通過內部互連結構140而電連接到導電凸塊400，如圖1所示。然而，實施例不限於此。在一些實施例中，直通電極200可以直接連接到導電凸塊400，或者每個電極200和對應的凸塊400可以構成單一的統一的主體而沒有任何異質接面於其間。導電凸塊400可以包括金屬材料，諸如銅材料或含有銅的合金材料。
導電黏著層430可以設置在各自的導電凸塊400上，以改善導電凸塊400和外部端子之間的接觸可靠性。導電黏著層430可以形成以包括含有錫(Sn)材料的焊料層。界面層410可以額外地設置在導電黏著層430和導電凸塊400之間。界面層410可以作為抑制污染或導電性凸塊400的氧化的潤濕層或阻障層來運作。界面層410可以包含鎳材料、金材料或它們的組合。
直通電極200可以使用術用於形成TSV製程來製造。直通電極200可以銅材料或含有銅的合金材料所形成。在一些實施例中，直通電極200可以形成以包括鎵(Ga)、銦(In)、錫(Sn)、銀(Ag)、汞(Hg)、鉍(Bi)、鉛(Pb)、金(Au)、鋅(Zn)、鋁(Al)或者包含這些材料中的至 少一種的合金。每個直通電極200可以穿透半導體基板100以具有通孔形狀，並且直通電極200的背側端部220可以從半導體基板100的第一表面103突出。電極絕緣層210可以包圍直通電極200的側壁，以將半導體基板100與直通電極200電絕緣。電極絕緣層210可以防止在直通電極200中的銅離子擴散或遷移到半導體基板100。
參考圖1和2，直通電極200的背側端部220可以從半導體基板100的第一表面103突出而插入到覆蓋半導體基板100的第一表面103的第二鈍化層500。如圖2所示的對應於部分“11”的放大視圖。如圖1所示，每個直通電極200的背側端部220的頂表面221可以較第二鈍化層500的頂表面501下面。背側端部220的頂表面221和第二鈍化層500的頂表面501之間的水平差值D可以是與設置在背側端部220的頂表面221上的阻障插塞600的垂直厚度一致。
阻障插塞600可以穿透第二鈍化層500以與直通電極200的背側端部220接觸。阻障插塞600可以填充插塞孔洞505，其穿透第二鈍化層500以暴露直通電極200的背側端部220。也就是說，阻障插塞600可以形成以覆蓋直通電極200的背側端部220的頂表面221。結果，直通電極200的背側端部220可以藉由阻障插塞600所隔絕。阻障層600的頂表面可以與第二鈍化層500的頂表面501基本上共面的。第二鈍化層500可以圍繞阻障插塞600的側壁並且暴露出阻障插塞600的頂表面。因此，當阻障插塞600電連接到外部裝置時，阻障插塞600的頂表面可以作為接觸表面來使用。因此，當執行半導體裝置電連接到外部裝置的製程時，直通電極200的背側端部220可以由於阻障插塞600的存在而物理地保護。
參考圖2和3，當半導體裝置10電連接到另一個半導體裝置時，其他的半導體裝置的導電凸塊401可以通過作為導電黏著層431的焊料層而被電連接到半導體裝置10的阻障插塞600。界面層411可以被佈置在導電凸塊401及導電黏著層431之間。也就是說，當另一基板層疊在半導體基板100上時，另一基板可以使用通過加壓步驟和加熱步驟(或超聲波步驟)進行的焊接製程而電性和機械地結合半導體基板100。因此，用於將半導體裝置10電連接到其它半導體裝置的互連結構12可以被實現，如圖3所示。
隨著半導體裝置10結合另一半導體裝置，包含在直通電極200(即，直通電極200的背側端部220)中的銅原子或銅離子可以被激發或活化以具有足夠的能量以待直通電極200的擴散。然而，根據實施例，直通電極200的背側端部220的頂表面221可以阻障插塞600所覆蓋，並且直通電極200的背側端部220的側壁可以藉由第二鈍化層500所包圍。因此，在進行焊接製程已將半導體裝置10結合其它半導體裝置之後，阻障插塞600和第二鈍化層500可以防止包含在通電極200的背側端部220的銅原子或銅離子被擴散出來。也就是說，即使直通電極200的背側端部220中的銅原子或銅離子被充分地激發以具有可擴散性能量，阻障插塞600阻擋銅原子或銅離子的遷移或擴散。
此外，阻障插塞600可以防止在導電黏著層431中的錫(Sn)原子被擴散到直通電極200。因此，阻障插塞600可以防止在導電黏著層431中的錫(Sn)原子和在直通電極200中的銅(Cu)原子之間的化學反應以免發生金屬間化合物材料的形成。即，當直通電極200電連接到其它半導體裝置的導電凸塊401來實現互連結構12時，阻障插塞600可以抑制降解互連結構 的可靠性的金屬間化合物材料12的形成。結果，阻障插塞600的存在可以改善互連結構12的可靠性。
在一個實施例中，阻障插塞600的唯一頂表面可以是經暴露的第二鈍化層500。阻障插塞600可以與直通電極200的各自的背側端部220垂直對齊。即，阻障插塞600可以是與背側端部220共軸的。此外，各個阻障插塞600的直徑可以是大致相等每個背側端部220的直徑。結果，由於阻障插塞600可以形成以具有與直通電極200的背側端部220基本上相同的間距尺寸，互連結構12還可以實現以具有精細間距尺寸。互連結構12可以實現，即使不使用配置在具有比背側端部220還大的尺寸的各自的阻障凸塊600上的任何背側端部220。因此，互連結構12可以應用於需要精細間距尺寸的晶圓級封裝(WLP)。
再次參考圖2，阻障插塞600可以形成以包括能夠阻擋銅原子擴散的導電材料。阻障插塞600可以形成以包括彼此不同的第一金屬層610和第二金屬層630。第一金屬層610可以被配置在背側端部220和第二金屬層630之間。此外，第一金屬層610可以延伸以覆蓋第二金屬層630的側壁。結果，第一金屬層610可以覆蓋第二金屬層630的底表面和側壁。
第二金屬層630可以使用電鍍製程以形成在第一金屬層610上。第一金屬層610可以包括在使用於電鍍製程中的晶種層或阻障金屬層。可替換地，第一金屬層610可以具有包括晶種層和設置在晶種層之下的阻障金屬層的多層結構。在一些實施例中，第一金屬層610可以形成以包括鈦(Ti)層或含鈦的合金層(Ti)。在一些實施例中，第一金屬層610可以形成以包括鈦(Ti)層和沉積在鈦(Ti)層上的銅(Cu)層。在沒有銅背側凸塊被設置 在直通電極200的實施例中，用於形成銅背側凸塊的銅電鍍製程可以不進行。在這種實施例中，用於形成構成第一金屬層610的銅(Cu)層的製程可被省略。
第二金屬層630可以包括能夠阻斷包含在導電黏著層431中的錫(Sn)原子的擴散而免於擴散到直通電極200的金屬材料。例如，第二金屬層630可以包括鎳(Ni)材料、鈀(Pd)材料、鈷(Co)材料、鉻(Cr)材料和銠(Rh)材料中的至少一種。
第二金屬層630可以包括鎳(Ni)層，以提供防止錫原子或錫離子的擴散的擴散阻障層。第二金屬層630的鎳(Ni)層可以作為濕潤層來運作，以提供導電黏著層(圖3中的431)和在圖3中所示的互連結構12的阻障插塞600的可靠結合。阻障插塞600進一步可以包括沉積在鎳(Ni)層上的金(Au)層。在這種情況的實施例中，金(Au)層可以作為抗氧化層。阻障插塞600可以填充插塞孔洞505，以具有厚度為足以防止錫和銅原子或離子的擴散。
第一金屬層610可以覆蓋藉由插塞孔洞505所暴露的直通電極200的頂表面221並且可以延伸以覆蓋藉由插塞孔洞505所暴露的第二鈍化層500的側壁。因此，第一金屬層610可以具有凹形狀，其具有中間的空間的“U”型橫截面。第二金屬層630可以填充在具有凹形狀的第一金屬層610的中間的空間。
再次參考圖1和2，第二鈍化層500可以覆蓋半導體基板100的第一表面103(即，背側表面)。第二鈍化層500的厚度可以具有大於自半導體基板100的第一表面103突出的背側端部220的高度。第二鈍化層500可以包 括例如聚合物材料的有機材料。例如，第二鈍化層500可以包括聚醯亞胺材料。或者，第二鈍化層500可以包括無機材料，諸如氧化矽(SiO2)層、氮化矽(Si3N4)層或氮氧化矽(SiON)層。
第二鈍化層500可以具有包括具有不同介電常數的多個電介質層的多層結構。例如，第二鈍化層500可以包括第一絕緣層510和第二絕緣層530。第一絕緣層510可以覆蓋半導體基板100的第一表面103和可以延伸到背側端部220和阻障插塞600的側壁。在這樣的實施例中，包圍背側端部220和阻障插塞600的第一絕緣層510的側壁部分可以對應於保護環部511。
第二絕緣層530可以被佈置在第一絕緣層510上。第一絕緣層510可以是保形裡襯層。第二絕緣層530可被配置在第一絕緣層510上，並且可以填充配置在阻障插塞600的側壁和背側端部220上方的第一絕緣層510的部分之間的空間。此外，第二絕緣層530可以作為緩衝層來運作以提供橫跨第二鈍化層500的頂部的平坦表面。即，第二絕緣層530可以提供第二鈍化層500的頂表面501的平整度，並且可以減輕施加在第二鈍化層500的應力。因此，即使當應力在形成互連結構(圖3中的12)期間施加到第二鈍化層500，第二絕緣層530可以防止互連結構12的機械可靠性的劣化。第二絕緣層530可以包括氧化矽(SiO2)層。第一絕緣層510可以作為擴散阻障層來運作，以阻擋包含在直通電極200的背側端部220中的銅離子的橫向擴散或橫向遷移。第一絕緣層510可以包括氮化矽(Si3N4)層或氮氧化矽(SiON)層，以有效地阻止金屬離子的擴散或遷移。如果包含在直通電極200中的銅離子擴散到半導體基板100的第一表面103，銅離子可以與包含在該半導體基板100的矽原子發生化學反應以生成銅-矽複合材料。此外，如果包含在直通電極 200中的銅離子擴散到半導體基板100，銅離子可能會降低形成在半導體基板100中的積體電路的電路元件(如電晶體)的特性。例如，銅離子可以降低閾值電壓特性或電晶體的漏電流的特性以造成不良刷新特性或記憶體裝置的不良待機電流特性。然而，根據實施例，絕緣層210和第一絕緣層510可以防止包含在直通電極200的銅離子被擴散到半導體基板100。因此，絕緣層210和第一絕緣層510可以降低半導體基板100的銅污染。
第二鈍化層500可以進一步包括擴散阻障層或設置在第一和第二絕緣層510和530上的應力緩衝層。在一個實施例中，擴散阻障層可以包括氮化矽(Si3N4)層或氮氧化矽(SiON)層，以及應力緩衝層可以包括氧化矽(SiO2)層。在一些實施例中，第二鈍化層500可以只由第一絕緣層510所形成，而不是第二絕緣層530，使得當互連結構12實現時，第一絕緣層510的保護環部511具有凸出的形狀。在這種情況下，第一絕緣層510可以由包括氮化矽層(或氮氧化矽層)和依次沉積的氧化矽層的結合層保形地形成。
參考圖1和4，根據一些實施例的半導體裝置20可以包括依次堆疊的多個晶片的堆疊封裝的形式來實現。在這樣一個實施例中，每個多個晶片可以對應於圖1所示的半導體裝置10。也就是說，半導體裝置20可以包括依序堆疊的多個半導體晶片13、14、15和16，並且每個半導體晶片13、14、15和16可以具有與參照圖1描述的半導體裝置10大致相同的配置。在一些實施例中，最上層半導體晶片16也可以不具備直通電極200、阻障插塞600和第二鈍化層500。
第一半導體晶片，例如，在堆疊的半導體晶片13、14、15和16之間的第二個最下面的半導體晶片14可以包括第一半導體基板100、穿 透第一半導體基板100的第一直通電極200以及包圍直通電極200的背側端部220阻障插塞600，如參考圖1描述。第二半導體晶片，例如，堆疊在第一半導體晶片14上的最上面的第二半導體晶片15可以包括第二半導體基板102、穿透第二半導體基板102的第二直通電極202以及電連接到第二直通電極202的導電凸塊401，如參照圖1和3描述。
第二半導體晶片15的導電凸塊401和第一半導體晶片14的直通電極200的背側端部220可以構成互連結構(圖3中的12)，如參考圖3描述，以提供第一和第二半導體晶片14和15之間的機械和電氣互連結構。例如，對應於焊料層的導電黏著層431可與阻障插塞600結合以將第一半導體晶片14第二半導體晶片15電連接和物理連接。黏著絕緣層700可以被佈置在半導體晶片13、14、15和16之間以將半導體晶片13、14、15和16之間彼此接合。
雖然附圖中未示出，在一個實施例中，半導體晶片13、14、15和16可以被安裝並堆疊在印刷電路板(PCB)或插入器中。可選地，半導體晶片13、14、15和16可以被嵌入在一基板中。另外，半導體晶片13、14、15和16可以藉由環氧模塑化合物(EMC)材料(未示出)覆蓋且封裝。
參考圖5，直通電極200可以從半導體基板100的第二表面101(對應於前側表面)朝向半導體基板100的第三表面104(對應於最初的背側表面)延伸。直通電極200可以使用用於形成晶片級的直通矽晶穿孔(TSV)的製程來形成。絕緣層210可以形成在直通電極200和半導體基板100之間，以將直通電極200與半導體基板100電絕緣。
凹槽製程R可以被施加到半導體基板100的第三表面104，以形成暴露直通電極200的背側端部220的第一表面103。更詳細地說，半導體 基板100可以使用黏著劑800附著到載體基板900，並且半導體基板100的背部的預定厚度可以被去除。半導體基板100的背部可以利用乾式蝕刻製程、濕式蝕刻製程和背面研磨製程中至少一者而除去。在一些實施例中，額外的第二刻蝕製程可以另外進行，使得直通電極200的所有的背側端部220從半導體基板100的第一表面103突出。
參考圖6所示，第二鈍化層500可以形成在半導體基板100的第一表面103上以覆蓋直通電極200的背側端部220。第二鈍化層500可以形成以包括第一絕緣層510和第二絕緣層530。第二鈍化層500可以形成以包括有機材料層或無機材料層。
參考圖7，平坦化製程P可以被應用到第二鈍化層500，以暴露直通電極200的背側端部220的最初頂表面223。在第二鈍化層500被形成以包括例如聚合物層的有機材料層的實施例中，背側端部220的最初頂表面223可以藉由使用表面處理製程或者乾式蝕刻製程去除在直通電極200的背側端部220上的第二鈍化層500的一部分而暴露。可選地，當第二鈍化層500被形成以包括無機材料層時，背側端部220的最初頂表面223可以藉由使用諸如化學機械拋光(CMP)製程的平坦化製程而平坦化第二鈍化層500。
參考圖8，蝕刻製程E可以被選擇性地施加到背側端部220的最初頂表面223以形成背側端部220的凹型表面221。結果，藉由第二鈍化層500所包圍的插塞孔洞505可以在各自的背側端部220上形成。插塞孔洞505可以藉由選擇性地蝕刻背側端部220來形成。因此，插塞孔洞505可以與直通電極200的餘下的背側端部220對齊，並且每個插塞孔洞505可以具有與餘下的背側端部220大致相同的直徑。如果直通電極200由銅材料形成，蝕刻製程 E可以使用濕式蝕刻製程而去除銅材料來進行。
參考圖9，作為晶種層運作的第一金屬層610可以保形地形成以覆蓋背側端部220的凹型表面221並且延伸到第二鈍化層500的表面上。
參考圖10，第二金屬層630可以形成於第一金屬層610上以填充插塞孔洞505。第一和第二金屬層610和630可以構成作為阻障插塞600的層。
參考圖11，作為阻障插塞600的層可以被平坦化，以暴露第二鈍化層500的頂表面並且在各自的插塞孔洞505中形成阻障插塞600。作為阻障插塞600的層可以使用化學機械拋光(CMP)製程被平面化。
圖12是說明根據本發明的一些實施例的半導體裝置的直通電極的橫截面視圖。
參考圖12，直通電極200的背側端部240可以具有錐形配置或凸型表面。直通電極200的背側端部240可以藉由適當地改變參考圖8所描述的蝕刻製程E的蝕刻配方而形成，以在第二鈍化層500和直通電極200之間相對於中心部分的蝕刻速率而增加界面區域B中的蝕刻速率。也就是說，當直通電極200的背側端部240是凹型的，蝕刻製程E的蝕刻配方可以適當地改變，使得界面區域B中的蝕刻速率比直通電極200的背側端部240的中央區域的蝕刻速率還高。結果，背側端部240的中心區域可以比背側端部240的邊緣區域更凹。由此，背側端部240可以為凹陷以具有如上所述的錐形配置或凸型表面。
具有錐形配置或凸型表面的背側端部240可以藉由阻障插塞605所封閉，其中阻障插塞605填充藉由第二鈍化層500所包圍的插塞孔洞。 阻障插塞605可以具有底表面輪廓，其具有與背側端部240的頂表面241的拓撲結構一致。例如，由於阻障插塞605的第二金屬層630的中心厚度T1小於第二金屬層630的邊緣厚度T2，阻障插塞605可以具有凹型底表面。如果第二金屬層630的邊緣厚度T2大於第二金屬層630的中心厚度T1，阻障插塞605可以更有效地防止在直通電極200中的銅離子被擴散出去。這是因為諸如銅離子的金屬離子更容易沿著兩個不同材料層之間的界面擴散或遷移。然而，根據一些實施例，相鄰魚界面區域B的第二金屬層630的部分的邊緣厚度T2可大於第二金屬層630的中心厚度T1。因此，阻障插塞605可有效地阻擋包含在直通電極200中的銅離子向外擴散。
根據實施例，可以提供用於將半導體裝置的直通電極電連接到外部裝的可靠的互連結構以及製造可靠的互連結構的方法。施加到半導體基板的背側表面的製程數目也可以藉由形成晶片級的直通電極而降低。因此，半導體裝置的製造成本可降低。此外，構成可靠的互連結構的直通電極的背側端部可以電連接到外部裝置，而不使用任何背側凸塊。因此，可靠的互連結構可以實現以具有約20微米至約30微米的精細間距大小。
此外，可靠的互連結構可以實現以具有阻障插塞，其防止在直通電極中的銅離子被擴散出去。此外，阻障插塞可以阻止外部裝置的外部端子和直通電極中的銅離子之間的化學反應，以降低金屬間化合物材料的形成。結果，互連結構的電性和機械地可靠性可以得到改進。
參考圖13，根據本發明的實施例的半導體裝置可以設在記憶卡1800的形式。例如，記憶卡1800可以包括記憶體1810，例如諸如非揮發性記憶體裝置和記憶體控制器1820。記憶體1810和記憶體控制器1820可以存儲 數據或讀出存儲的數據。
記憶體1810可以包括用於本發明的實施例的技術應用的所述至少一個非揮發性記憶體裝置。記憶體控制器1820可以控制記憶體1810，使得響應於來自主機1830的讀/寫請求，存儲的數據被讀出或者數據被存儲。
參考圖14，根據一個實施例的半導體裝置可以應用於電子系統2710。電子系統2710可以包括控制器2711、輸入/輸出單元2712和記憶體2713。控制器2711、輸入/輸出單元2712和記憶體2713可以通過提供數據傳輸路徑的匯排流2715彼此耦合。
舉例來說，控制器2711可以包括至少一個微處理器、至少一個數位訊號處理器、至少一個微控制器或能夠執行與這些組件相同功能的邏輯裝置。控制器2711或記憶體2713可以根據本發明的實施例包括至少一個半導體裝置。輸入/輸出單元2712可以包括至袖珍鍵盤、鍵盤、顯示裝置、觸控螢幕等等之中的至少一者。記憶體2713是一種用於存儲數據的裝置。記憶體裝置2713可以存儲數據及/或命令以藉由控制器2711在其他類似物所執行。
記憶體2713可以包括揮發性記憶體裝置，諸如DRAM，及/或非揮發性記憶體裝置，諸如快閃記憶體。例如，快閃記憶體可以被安裝到資訊處理系統，諸如移動終端或桌上型電腦。快閃記憶體可以構成固態磁盤(solid state disk，SSD)。在這個情況下，電子系統2710可以在快閃記憶體系統中穩定地存儲大量數據。
電子系統2710可以進一步包括介面2714，配置成從通信網絡發送和接收數據以及發送和接收數據至通信網絡。介面2714可以是有線或無 線型介面。例如介面2714可以包括天線或有線或無線收發器。
電子系統2710可以移動系統或裝置、個人電腦或膝上型電腦、工業電腦或伺服器，或任何其他邏輯或計算系統來實現。例如，移動系統或裝置可以是個人數位助理(PDA)、便攜式電腦、平板式電腦、行動電話、智慧型手機、無線手機、膝上型電腦、記憶卡、數位音樂系統以及資訊發送/接收系統中的任何一者。
在電子系統2710包括能夠執行無線通訊的設備的實施例中，電子系統2710可以使用在通信系統中，諸如CDMA(code division multiple access，分碼多重進接)、GSM(global system for mobile communications，全球行動通訊系統)、NADC(North American Digital Cellular，北美數位行動電話)、E-TDMA(enhanced-time division multiple access，增強分時多重進接)、WCDMA(wideband code division multiple access，寬頻分碼多工接取)、CDMA2000、LTE(long term evolution，長期演進技術)及/或Wibro(wireless broadband internet，無線寬頻網路)。
本發明的實施例已於上文披露以供說明之用。本領域技術人士將會理解各種調整、添加和替換都是可能的，而不脫離在所附的申請專利範圍書中所揭露的本發明的概念的範圍和精神。
10‧‧‧半導體裝置
11‧‧‧部分
100‧‧‧半導體基板
101‧‧‧第二表面
110‧‧‧電晶體
130‧‧‧層間絕緣層
140‧‧‧內部互連結構
150‧‧‧連接襯墊
200‧‧‧直通電極
210‧‧‧絕緣層
220‧‧‧背側端部
221‧‧‧頂表面
300‧‧‧第一鈍化層
301‧‧‧孔洞
400‧‧‧導電凸塊
410‧‧‧界面層
430‧‧‧導電黏著層
450‧‧‧連接端子
500‧‧‧第二鈍化層
510‧‧‧第一絕緣層
511‧‧‧保護環部
530‧‧‧第二絕緣層
600‧‧‧阻障插塞
610‧‧‧第一金屬層
630‧‧‧第二金屬層

Claims (20)

  1. 一種半導體裝置，包括：直通電極，其穿透基板，使得所述直通電極的端部從基板的表面突出；鈍化層，其覆蓋所述基板的表面並且定義了暴露所述直通電極的端部的插塞孔洞，所述直通電極的端部的頂表面對應於所述插塞孔洞的底面的的底表面；以及阻障插塞，其填充所述插塞孔洞。
  2. 根據申請專利範圍第1項的半導體裝置，其中所述鈍化層的厚度大於所述直通電極的端部從所述基板的表面突出的一個距離。
  3. 根據申請專利範圍第2項的半導體裝置，其中所述鈍化層包括第一絕緣層，其覆蓋所述基板的表面並且在所述直通電極的端部的側壁和所述阻障插塞的側壁的上方延伸。
  4. 根據申請專利範圍第3項的半導體裝置，其中所述鈍化層進一步包括設置在所述第一絕緣層上的第二絕緣層，以提供平坦的表面。
  5. 根據申請專利範圍第4項的半導體裝置，其中，所述第一絕緣層包括氮氧化矽層或氮化矽層；以及其中，所述第二絕緣層包括氧化矽層。
  6. 根據申請專利範圍第3項的半導體裝置，其中所述阻障插塞具有頂部表面，其與所述鈍化層的頂部表面為基本上共面的。
  7. 根據申請專利範圍第3項的半導體裝置，其中所述阻障插塞包括金屬層，其防止包含在所述直通電極中的元素被擴散出來。
  8. 根據申請專利範圍第3項的半導體裝置，其中所述阻障插塞包括第一金屬層和第二金屬層，所述第一金屬層的材料不同於所述第二金屬層的材料。
  9. 根據申請專利範圍第8項的半導體裝置，其中，所述第二金屬層包括電鍍層，以及其中，所述第一金屬層包括在電鍍製程中使用的晶種層，以用於形成所述第二金屬層。
  10. 根據申請專利範圍第8項的半導體裝置，其中，所述第二金屬層包括鎳層；以及其中，所述第一金屬層包括鈦層或銅層。
  11. 根據申請專利範圍第8項的半導體裝置，其中所述第一金屬層覆蓋藉由所述插塞孔洞所暴露的所述直通電極的端部的頂部表面，並且在藉由所述插塞孔洞所暴露的所述鈍化層的側壁上方延伸以具有凹的形狀。
  12. 根據申請專利範圍第2項的半導體裝置，其中所述阻障插塞與所述直通電極的端部對齊，並且具有與所述直通電極大致相同的直徑。
  13. 根據申請專利範圍第2項的半導體裝置，其中，所述直通電極的端部具有錐形結構或凸的頂表面，使得所述直通電極的端部的邊緣區域比所述直通電極的端部的中心區域還低；以及其中，所述阻障插塞具有凹的底表面，使得所述阻障插塞的底表面的邊緣區域比所述阻障插塞的底表面的中心區域還低。
  14. 根據申請專利範圍第2項的半導體裝置，其中所述鈍化層包括有機材料層或無機材料層。
  15. 一種半導體裝置，包括：第一直通電極，其穿透第一基板，使得所述第一直通電極的端部從所述第一基板的表面突出；鈍化層，其覆蓋所述第一基板的表面並且定義了暴露所述第一直通電極的端部的插塞孔洞，所述第一直通電極的端部的頂部表面對應於所述插塞孔洞的底部表面；阻障插塞，其填充所述插塞孔洞；第二基板，其層疊在所述第一基板上；以及連接端子，其連接到所述第二基板並且耦接所述阻障插塞。
  16. 根據申請專利範圍第15項的半導體裝置，其中所述鈍化層的厚度大於所述第一直通電極的端部從所述第一基板的表面突出的一個距離。
  17. 根據申請專利範圍第16項的半導體裝置，其中所述鈍化層包括第一絕緣層，其覆蓋所述第一基板的表面，並且在所述第一直通電極的端部的側壁和所述阻障插塞的側壁上方延伸。
  18. 根據申請專利範圍第15項的半導體裝置，其中所述連接端子包括具有直徑大於所述阻障插塞的直徑的導電凸塊。
  19. 根據申請專利範圍第15項的半導體裝置，其中所述導電凸塊電連接穿透所述第二基板的第二直通電極。
  20. 一種半導體裝置，包括：第一直通電極，其穿透第一基板，使得所述第一直通電極的端部從所述第一基板的表面突出；鈍化層，其覆蓋所述第一基板的表面，並且定義了暴露所述第一直通電極的端部的頂表面的插塞孔洞；阻障插塞，其填充所述插塞孔洞；第二基板，其層疊在所述第一基板上；以及連接端子，其連接到所述第二基板並且耦接所述阻障插塞， 其中，所述鈍化層的厚度大於所述第一直通電極的端部的高度，以及其中，所述鈍化層包括絕緣層，其覆蓋所述第一基板的表面，並且在所述第一直通電極的端部的側壁和所述阻障插塞的側壁上方延伸。
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US10910357B2 (en) 2019-03-21 2021-02-02 Nanya Technology Corporation Semiconductor package including hybrid bonding structure and method for preparing the same

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