TW201719775A - 封裝結構及其形成方法 - Google Patents
封裝結構及其形成方法 Download PDFInfo
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Abstract
一實施例為一種方法,其包括形成一第一封裝。該形成該第一封裝:包括鄰近於一第一晶粒而形成一貫穿通路;藉由一包封物來至少側向地包封該第一晶粒及該貫穿通路;及在該第一晶粒、該貫穿通路及該包封物上方形成一第一重佈結構。該形成該第一重佈結構包括:在該貫穿通路上形成一第一通路;及在該第一通路上形成一第一金屬化圖案,該第一金屬化圖案之至少一個側壁直接地覆蓋該貫穿通路。
Description
本申請案主張2015年8月21日申請之美國臨時申請案第62/208,436號之權益,該美國臨時申請案係特此以引用之方式併入本文中。
本揭露係關於一種封裝結構及其形成方法。
半導體裝置用於多種電子應用中,諸如(作為實例)個人電腦、蜂巢式電話、數位攝影機及其他電子設備。通常藉由在半導體基板上方依序地沈積絕緣材料層或介電材料層、導電材料層及半導電材料層且使用微影來圖案化該各種材料層以在其上形成電路組件及元件而製造半導體裝置。通常在單一半導體晶圓上製造數十或數百個積體電路。藉由沿著切割道鋸割積體電路而單粒化個別晶粒。接著(例如)以多晶片模組或以其他類型之封裝來分離地封裝個別晶粒。
半導體工業藉由連續地縮減最小構件大小而不斷地改良各種電子組件(例如,電晶體、二極體、電阻器、電容器等等)之整合密度,該等縮減允許將較多組件整合至給定區域中。在一些應用中,諸如積體電路晶粒之此等較小電子組件亦可需要相較於過去的封裝利用較少區域之較小封裝。
一實施例為一種方法,其包括形成一第一封裝。該形成該第一封裝包括鄰近於一第一晶粒而形成一貫穿通路,藉由一包封物來至少側向地包封該第一晶粒及該貫穿通路,及在該第一晶粒、該貫穿通路及該包封物上方形成一第一重佈結構。該形成該第一重佈結構包括在該貫穿通路上形成一第一通路,及在該第一通路上形成一第一金屬化圖案,該第一金屬化圖案之至少一個側壁直接地覆蓋該貫穿通路。
另一實施例為一種方法,其包括形成一第一封裝。該形成該第一封裝包括:鄰近於一第一晶粒而形成一第一貫穿通路及一第二貫穿通路,該第一貫穿通路及該第二貫穿通路之鄰近側壁被分離達一第一距離;藉由一包封物來至少側向地包封該第一晶粒、該第一貫穿通路及該第二貫穿通路;及在該第一晶粒、該第一貫穿通路、該第二貫穿通路及該包封物上方形成一第一重佈結構。該形成該第一重佈結構包括在該第一貫穿通路上形成一第一通路,在該第二貫穿通路上形成一第二通路,在該第一通路上形成一第一金屬化圖案,及在該第二通路上形成一第二金屬化圖案,該第一金屬化圖案及該第二金屬化圖案之鄰近側壁被分離達一第二距離,該第二距離大於該第一距離。
一另外實施例為一種結構,其包括:鄰近於一第一晶粒之一第一貫穿通路及一第二貫穿通路,該第一貫穿通路及該第二貫穿通路之鄰近側壁被分離達一第一距離;至少側向地環繞該第一晶粒、該第一貫穿通路及該第二貫穿通路之一包封物;在該第一貫穿通路上之一第一通路;在該第二貫穿通路上之一第二通路;在該第一通路上之一第一金屬化圖案;及在該第二通路上之一第二金屬化圖案,該第一金屬化圖案及該第二金屬化圖案之鄰近側壁被分離達一第二距離,該第二距離大於該第一距離。
100‧‧‧載體基板
102‧‧‧離型層
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧組件/半導體基板
122‧‧‧組件/墊
124‧‧‧組件/鈍化膜
126‧‧‧組件/晶粒連接器
128‧‧‧組件/介電材料
130‧‧‧包封物
132‧‧‧晶種層
134‧‧‧光阻劑
134A‧‧‧光阻劑
134B‧‧‧光阻劑
136‧‧‧導電構件/貫穿通路/貫穿成型通路
136A‧‧‧第一部分/導電構件
136B‧‧‧第二部分/導電構件
138‧‧‧積體電路晶粒
140‧‧‧黏著劑
142‧‧‧組件
144‧‧‧組件
146‧‧‧組件
148‧‧‧組件/晶粒連接器
150‧‧‧組件
152‧‧‧包封物
154‧‧‧介電層
156‧‧‧通路
158‧‧‧金屬化圖案
160‧‧‧金屬化圖案/佈線
162‧‧‧介電層
164‧‧‧金屬化圖案
166‧‧‧介電層
168‧‧‧金屬化圖案
170‧‧‧介電層
172‧‧‧前側重佈結構
174‧‧‧墊
176‧‧‧外部電連接器
180‧‧‧光阻劑
190‧‧‧導電構件/重佈層
192‧‧‧導電構件
198‧‧‧重佈層/導電構件
S1‧‧‧間距
S2‧‧‧間距
當結合附圖進行閱讀時,自以下【實施方式】最佳地理解本揭露之態樣。應注意,根據行業慣例,各種構件未按比例繪製。事實上,可出於論述清楚起見而任意地增加或縮減各種構件之尺寸。
圖1至圖11、圖12A至圖12B、圖13至圖22為在用於形成根據一些實施例之封裝結構的製程期間之中間步驟的視圖。
圖23至圖28、圖29A至圖29B及圖30為在用於形成根據另一實施例之封裝結構的製程期間之中間步驟的視圖。
圖31至圖37、圖38A至圖38B及圖39為在用於形成根據另一實施例之封裝結構的製程期間之中間步驟的視圖。
圖40至圖43、圖44A至圖44B及圖45為在用於形成根據另一實施例之封裝結構的製程期間之中間步驟的視圖。
圖46A至圖46C為根據一些實施例之輸入/輸出組態的俯視圖。
以下揭露提供用於實施所提供之主題之不同構件的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然,此等者僅僅為實例且並不意欲為限制性的。舉例而言,在以下描述中將第一構件形成於第二構件上方或上可包括將第一構件及第二構件形成為進行直接接觸的實施例,且亦可包括可將額外構件形成於第一構件與第二構件之間使得第一構件及第二構件可不進行直接接觸的實施例。另外,本揭露可在各種實例中重複參考數字及/或字母。此重複係出於簡單及清楚之目的,且本身並不規定所論述之各種實施例及/或組態之間的關係。
另外,諸如「之下」、「下方」、「下部」、「上方」、「上部」及其類似者之空間相對術語可在本文中出於描述簡易起見而使用以描述如諸圖所說明的一個元件或構件與另一(另外)元件或構件之關係。相似地,諸如「前側」及「後側」之術語可在本文中用以較容易地識別各
種組件,且可識別出彼等組件係(例如)在另一組件之對置側上。除了諸圖所描繪之定向以外,空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式而定向(旋轉90度或處於其他定向),且本文中所使用之空間相對描述詞可同樣相應地予以解譯。
可在特定上下文(即,封裝結構)中論述本文中所論述之實施例。封裝結構可包括扇出封裝或扇入封裝。其他實施例預期其他應用,諸如對於一般熟習此項技術者而言在閱讀本揭露後就將易於顯而易見之不同封裝類型或不同組態。應注意,本文中所論述之實施例可未必說明可存在於一結構中之每一組件或構件。舉例而言,諸如當一個組件之論述可足以傳達實施例之態樣時,可自圖省略多個組件。另外,可將本文中所論述之方法實施例論述為以特定次序而執行;然而,其他方法實施例可以任何邏輯次序而執行。
圖1至圖11、圖12A至圖12B及圖13至圖22說明在用於形成根據一些實施例之封裝結構的製程期間之中間步驟的視圖。圖1至圖11、圖12A及圖13至圖22說明剖面圖,其中圖12B為俯視圖。圖1說明載體基板100及形成於載體基板100上之離型層(release layer)102。
載體基板100可為玻璃載體基板、陶瓷載體基板或其類似者。載體基板100可為晶圓,使得多個封裝可同時地形成於載體基板100上。離型層102可由聚合物基材料形成,其可連同載體基板100一起自將在後續步驟中形成之上覆結構予以移除。在一些實施例中,離型層102為在被加熱時失去其黏著性質之環氧樹脂基熱離型材料,諸如光/熱轉換(LTHC)離型塗層。在其他實施例中,離型層102可為在曝光於紫外線(UV)光時失去其黏著性質之UV黏膠。離型層102可被施配為液體且固化、可為層壓至載體基板100上之層壓膜,或可為其類似者。離型層102之頂部表面可被調平,且可具有高度共面性。
在圖2中,由黏著劑116將積體電路晶粒114黏著至離型層102。如
圖2所說明,一個積體電路晶粒114黏著於載體基板100上方,且在其他實施例中,較多或較少積體電路晶粒可黏著於載體基板100上方。
在將積體電路晶粒114黏著至離型層102之前,可根據適用製造製程來處理積體電路晶粒114以在積體電路晶粒114中形成積體電路。舉例而言,積體電路晶粒114各自包含一半導體基板118(諸如經摻雜或未經摻雜矽),或一絕緣體上半導體(SOI)基板之一主動層。半導體基板可包括:其他半導體材料,諸如鍺;合成半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。亦可使用其他基板,諸如多層或梯度基板。諸如電晶體、二極體、電容器、電阻器等等之裝置可形成於半導體基板118中及/或上,且可由(例如)半導體基板118上之一或多個介電層中之金屬化圖案所形成的互連結構(未圖示)互連以形成積體電路。
積體電路晶粒114進一步包含耦接至互連結構之墊122,諸如鋁墊。墊122允許對積體電路晶粒114進行外部連接。墊122係在可被稱作積體電路晶粒114之各別主動側的側上。鈍化膜124係在積體電路晶粒114上及在墊122之部分上。開口係通過鈍化膜124而至墊122。諸如導電柱之晶粒連接器126係在通過鈍化膜124之開口中,且機械及電耦接至各別墊122。晶粒連接器126可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。晶粒連接器126可包含金屬,比如銅、鈦、鎢、鋁或其類似者。晶粒連接器126電耦接積體電路晶粒114之各別積體電路。
介電材料128係在積體電路晶粒114之主動側上,諸如在鈍化膜124及晶粒連接器126上。介電材料128側向地包封晶粒連接器126,且介電材料128係與各別積體電路晶粒114側向地共端。介電材料128可由聚合物製成,諸如聚苯并唑(PBO)、聚醯亞胺、苯并環丁烯
(BCB)或其類似者。在其他實施例中,介電層104係由以下各者形成:氮化物,諸如氮化矽;氧化物,諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG)或其類似者;或其類似者。介電層104可藉由任何可接受的沈積製程而形成,諸如旋塗、化學氣相沈積(CVD)、層壓、其類似者或其組合。
黏著劑116係在積體電路晶粒114之後側上,且將積體電路晶粒114黏著至載體基板100,諸如說明中之離型層102。黏著劑116可為任何合適黏著劑、環氧樹脂、晶粒附接膜(DAF)或其類似者。黏著劑116可施加至積體電路晶粒114之後側(諸如施加至各別半導體晶圓之後側),或可施加於載體基板100之表面上方。可諸如藉由鋸割或切割而單粒化積體電路晶粒114,且使用(例如)取置型工具而由黏著劑116將積體電路晶粒114黏著至介電層108。
積體電路晶粒114可為邏輯晶粒(例如,中央處理單元、微控制器等等)、記憶體晶粒(例如,動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等等)、功率管理晶粒(例如,功率管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如,數位訊號處理(DSP)晶粒)、前端晶粒(例如,類比前端(AFE)晶粒)、其類似者或其組合。
在圖3中,將包封物130形成於各種組件上。包封物130可為模塑料、環氧樹脂或其類似者,且可藉由壓縮成型、轉注成型或其類似者予以施加。在固化之後,包封物130可經歷研磨製程(例如,化學機械拋光(CMP)製程)以曝光晶粒連接器126。晶粒連接器126及包封物130之頂部表面在研磨製程之後共面。在一些實施例中,可(例如)在晶粒連接器126已經被曝光的情況下省略研磨。
在圖4中,將晶種層132形成於各種組件上。晶種層132可形成於介電層128、晶粒連接器126及包封物130上方。在一些實施例中,晶
種層132為金屬層,其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中,晶種層132包含鈦層及在鈦層上方之銅層。可使用(例如)物理氣相沈積(PVD)或其類似者來形成晶種層132。
在圖5中,接著在晶種層132上形成及圖案化光阻劑134。光阻劑134可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑134之圖案對應於晶粒連接器126。圖案化形成通過光阻劑134之開口以曝光在晶粒連接器126上方之晶種層132。
在圖6中,將導電材料形成於光阻劑134之開口中及晶種層132之經曝光部分上以形成導電構件136。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。
在圖7中,移除光阻劑134及未形成有導電材料的晶種層132之部分。可藉由可接受的灰化或剝離製程來移除光阻劑134,諸如使用氧電漿或其類似者。一旦移除光阻劑134,就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層132之經曝光部分。晶種層132之剩餘部分及導電材料形成導電構件136。導電構件136可被稱作貫穿通路136或貫穿成型通路(TMV)136。後續諸圖未說明晶種層132。如圖7所說明,四個貫穿通路136形成於積體電路晶粒114上方且耦接至積體電路晶粒114,且在其他實施例中,較多或較少貫穿通路136可形成於積體電路晶粒114上方且耦接至積體電路晶粒114。
在圖8中,將積體電路晶粒138黏著於積體電路晶粒114上方,例如,黏著至積體電路晶粒114之介電層128。積體電路晶粒138可由黏著劑140黏著,黏著劑140可相似於上文所描述之黏著劑116且在本文中不重複描述。如圖8所說明,一個積體電路晶粒138黏著於積體電路晶粒114上方,且在其他實施例中,較多或較少積體電路晶粒可黏著
於積體電路晶粒114上方。
積體電路晶粒138可相似於上文所描述之積體電路晶粒114且在本文中不重複描述,但積體電路晶粒114及138無需相同。積體電路晶粒138之組件142、144、146、148及150可相似於上文所描述之積體電路晶粒114之組件118、122、124、126及128且在本文中不重複描述,但積體電路晶粒114及138之組件無需相同。
在圖9中,將包封物152形成於各種組件上。包封物152可為模塑料、環氧樹脂或其類似者,且可藉由壓縮成型、轉注成型或其類似者予以施加。在固化之後,包封物152可經歷研磨製程以曝光貫穿通路136及晶粒連接器148。貫穿通路136、晶粒連接器148及包封物152之頂部表面在研磨製程之後共面。在一些實施例中,可(例如)在貫穿通路136及晶粒連接器126已經被曝光的情況下省略研磨。
在圖10至圖20中,形成前側重佈結構172。如將在圖20中所說明,前側重佈結構172包括介電層154、162、166及170以及金屬化圖案158、160、164及168。
在圖10中,將介電層154沈積於包封物152、貫穿通路136及晶粒連接器148上。在一些實施例中,介電層154係由聚合物形成,其可為可使用微影遮罩而圖案化之光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層154係由以下各者形成:氮化物,諸如氮化矽;氧化物,諸如氧化矽、PSG、BSG、BPSG;或其類似者。介電層154可藉由旋塗、層壓、CVD、其類似者或其組合而形成。
在圖11中,接著圖案化介電層154。圖案化形成開口以曝光貫穿通路136及晶粒連接器148之部分。圖案化可藉由可接受的製程,諸如藉由當介電層154為光敏材料時將介電層154曝光於光,或藉由使用(例如)非等向性蝕刻進行蝕刻。若介電層154為光敏材料,則可在曝
光之後顯影介電層154。
在圖12A中,將具有通路之金屬化圖案158及160形成於介電層154上。作為用以形成金屬化圖案158及160之實例,將晶種層(未圖示)形成於介電層154上方及通過介電層154之開口中。在一些實施例中,晶種層為金屬層,其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中,晶種層包含鈦層及在鈦層上方之銅層。可使用(例如)PVD或其類似者來形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑之圖案對應於金屬化圖案158及160。圖案化形成通過光阻劑之開口以曝光晶種層。導電材料形成於光阻劑之開口中及晶種層之經曝光部分上。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。接著,移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝離製程來移除光阻劑,諸如使用氧電漿或其類似者。一旦移除光阻劑,就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之經曝光部分。晶種層之剩餘部分及導電材料形成金屬化圖案158及160以及通路。通路形成於通過介電層154而至(例如)貫穿通路136及/或晶粒連接器148之開口中。
圖12B為圖12A中之結構的俯視圖,其中圖12A中之結構係沿著圖12B之線A-A。金屬化圖案160可被稱作佈線160。在一些實施例中,佈線160通過鄰近金屬化圖案158之間,鄰近金屬化圖案158耦接至鄰近貫穿通路136。
在一些實施例中,鄰近貫穿通路136之側壁被分離達間距S1且對應鄰近金屬化圖案158之側壁被分離達間距S2,其中間距S2大於間距S1。換言之,金屬化圖案158小於(至少在自貫穿通路136之中心起的直徑方面)貫穿通路136(參見圖12B)。藉由具有較大間距S2,存在較
多空間以供佈線160通過鄰近金屬化圖案158之間。此可允許較多及/或較寬佈線160通過鄰近金屬化圖案158之間。
在圖13中,將介電層162沈積於金屬化圖案158及160以及介電層154上。在一些實施例中,介電層62係由聚合物形成,其可為可使用微影遮罩而圖案化之光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層162係由以下各者形成:氮化物,諸如氮化矽;氧化物,諸如氧化矽、PSG、BSG、BPSG;或其類似者。介電層162可藉由旋塗、層壓、CVD、其類似者或其組合而形成。
在圖14中,接著圖案化介電層162。圖案化形成開口以曝光金屬化圖案158之部分。圖案化可藉由可接受的製程,諸如藉由當介電層為光敏材料時將介電層162曝光於光,或藉由使用(例如)非等向性蝕刻進行蝕刻。若介電層162為光敏材料,則可在曝光之後顯影介電層162。
在圖15中,將具有通路之金屬化圖案164形成於介電層162上。作為用以形成金屬化圖案164之實例,將晶種層(未圖示)形成於介電層162上方及通過介電層162之開口中。在一些實施例中,晶種層為金屬層,其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中,晶種層包含鈦層及在鈦層上方之銅層。可使用(例如)PVD或其類似者來形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑之圖案對應於金屬化圖案164。圖案化形成通過光阻劑之開口以曝光晶種層。導電材料形成於光阻劑之開口中及晶種層之經曝光部分上。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。接著,移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝離製程來移除光阻劑,諸如使用氧電漿或其類似者。一旦
移除光阻劑,就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之經曝光部分。晶種層之剩餘部分及導電材料形成金屬化圖案164及通路。通路形成於通過介電層162而至(例如)金屬化圖案158之部分的開口中。
在圖16中,將介電層166沈積於金屬化圖案164及介電層162上。在一些實施例中,介電層166係由聚合物形成,其可為可使用微影遮罩而圖案化之光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層166係由以下各者形成:氮化物,諸如氮化矽;氧化物,諸如氧化矽、PSG、BSG、BPSG;或其類似者。介電層166可藉由旋塗、層壓、CVD、其類似者或其組合而形成。
在圖17中,接著圖案化介電層166。圖案化形成開口以曝光金屬化圖案164之部分。圖案化可藉由可接受的製程,諸如藉由當介電層為光敏材料時將介電層166曝光於光,或藉由使用(例如)非等向性蝕刻進行蝕刻。若介電層166為光敏材料,則可在曝光之後顯影介電層166。
在圖18中,將具有通路之金屬化圖案168形成於介電層166上。作為用以形成金屬化圖案168之實例,將晶種層(未圖示)形成於介電層166上方及通過介電層166之開口中。在一些實施例中,晶種層為金屬層,其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中,晶種層包含鈦層及在鈦層上方之銅層。可使用(例如)PVD或其類似者來形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑之圖案對應於金屬化圖案168。圖案化形成通過光阻劑之開口以曝光晶種層。導電材料形成於光阻劑之開口中及晶種層之經曝光部分上。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。接
著,移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝離製程來移除光阻劑,諸如使用氧電漿或其類似者。一旦移除光阻劑,就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之經曝光部分。晶種層之剩餘部分及導電材料形成金屬化圖案168及通路。通路形成於通過介電層166而至(例如)金屬化圖案164之部分的開口中。
在圖19中,將介電層170沈積於金屬化圖案168及介電層166上。在一些實施例中,介電層170係由聚合物形成,其可為可使用微影遮罩而圖案化之光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層170係由以下各者形成:氮化物,諸如氮化矽;氧化物,諸如氧化矽、PSG、BSG、BPSG;或其類似者。介電層170可藉由旋塗、層壓、CVD、其類似者或其組合而形成。
在圖20中,接著圖案化介電層170。圖案化形成開口以曝光金屬化圖案168之部分。圖案化可藉由可接受的製程,諸如藉由當介電層為光敏材料時將介電層170曝光於光,或藉由使用(例如)非等向性蝕刻進行蝕刻。若介電層170為光敏材料,則可在曝光之後顯影介電層170。
前側重佈結構172被展示為一實例。較多或較少介電層及金屬化圖案可形成於前側重佈結構172中。若將形成較少介電層及金屬化圖案,則可省略上文所論述之步驟及製程。若將形成較多介電層及金屬化圖案,則可重複上文所論述之步驟及製程。一般熟習此項技術者將易於理解哪些步驟及製程將被省略或重複。
在圖21中,將可被稱作凸塊下金屬(UBM)之墊174形成於前側重佈結構172之外部側上。在所說明之實施例中,貫穿通過介電層170而至金屬化圖案168之開口形成墊174。作為用以形成墊174之實例,將晶種層(未圖示)形成於介電層170上方。在一些實施例中,晶種層為
金屬層,其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中,晶種層包含鈦層及在鈦層上方之銅層。可使用(例如)PVD或其類似者來形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑之圖案對應於墊174。圖案化形成通過光阻劑之開口以曝光晶種層。導電材料形成於光阻劑之開口中及晶種層之經曝光部分上。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。接著,移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝離製程來移除光阻劑,諸如使用氧電漿或其類似者。一旦移除光阻劑,就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之經曝光部分。晶種層之剩餘部分及導電材料形成墊174。
在圖22中,將諸如比如球狀柵格陣列(BGA)球之焊球的外部電連接器176形成於墊174上。外部電連接器176可包括諸如焊料之低溫可回焊材料,其可無鉛或含鉛。可藉由使用適當植球製程來形成外部電連接器176。在一些實施例中,可省略墊174,且外部電連接器176可貫穿通過介電層170之開口直接地形成於金屬化圖案168上。
在圖22之後,可執行載體基板脫接以使載體基板100自封裝結構拆離(脫接)。根據一些實施例,脫接包括將諸如雷射光或UV光之光投影於離型層102上,使得離型層102在光之熱下分解且可移除載體基板100。
結構可進一步經歷藉由沿著切割道區(例如,在鄰近封裝結構之間)鋸割進行之單粒化製程。在載體脫接及可選單粒化之後的所得封裝結構可被稱作整合式扇出(InFO)封裝。
圖23至圖28、圖29A至圖29B及圖30為在用於形成根據另一實施
例之封裝結構的製程期間之中間步驟的視圖。此實施例相似於圖1至圖11、圖12A至圖12B及圖13至圖22之先前實施例,惟如下情形除外:在此實施例中,貫穿通路136具有第一部分136A及第二部分136B,其中第二部分相較於第一部分136A具有較小寬度。另外,此實施例之視圖僅展示正形成的封裝結構之部分(例如,封裝結構之左邊部分且下方排除載體基板),但可鄰近於此結構形成相似製程及結構,其將引起相似於圖22之先前實施例中所說明之結構的整體結構。在本文中將不重複相似於針對先前描述之實施例之細節的關於此實施例之細節。
圖23處於與上文所描述之圖4相似的處理點,且在本文中不重複直至此點所執行之製程及步驟。圖23包括積體電路晶粒114、晶粒連接器126、介電材料128、包封物130及晶種層132。
在圖24中,接著在晶種層132上形成及圖案化光阻劑134A。光阻劑134A可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑134A之圖案對應於晶粒連接器126。圖案化形成通過光阻劑134A之開口以曝光在晶粒連接器126上方之晶種層132。
在圖25中,將導電材料形成於光阻劑134A之開口中及晶種層132之經曝光部分上以形成導電構件136A。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。
在圖26中,接著在光阻劑134A及導電構件136A上形成及圖案化光阻劑134B。光阻劑134B可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑134B之圖案對應於導電構件136A。圖案化形成通過光阻劑134B之開口以曝光導電構件136A。
在圖27中,將導電材料形成於光阻劑134B之開口中及導電構件136A之經曝光部分上以形成導電構件136B。導電材料可藉由鍍覆而
形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。導電構件136A及136B一起形成導電構件136(貫穿通路136)。在此實施例中,貫穿通路136之第一部分136A寬於貫穿通路136之第二部分136B。貫穿通路136之此較小第二部分(上部部分)136B允許鄰近第二部分136B之側壁之間的較大間距S1(參見圖29B),此亦實現對應鄰近金屬化圖案158之側壁之間的較大間距S2。如圖27所說明,兩個貫穿通路136形成於積體電路晶粒114上方且耦接至積體電路晶粒114,且在其他實施例中,較多或較少貫穿通路136可形成於積體電路晶粒114上方且耦接至積體電路晶粒114。
在圖28中,已如上文在圖8及圖9中所描述而附接及形成積體電路晶粒138及包封物152,且在本文中不重複描述。在圖29A及圖29B中,如上文參考圖10、圖11及圖12A至圖12B所描述而形成介電層154、金屬化圖案158、通路156及佈線160,惟如下情形除外:在此實施例中,歸因於貫穿通路136之第二部分136B的較小寬度,間距S1及S2可大於圖12A至圖12B中之間距S1及S2。因此,在此實施例中,歸因於增加的間距S1及S2,在鄰近金屬化圖案158之間可存在較多佈線160。
在圖30中,處理繼續形成前側重佈結構172、墊174及連接器176。用以形成前側重佈結構172、墊174及連接器176之步驟及製程可相似於上文在圖13至圖22中所描述之步驟及製程,且在本文中不重複描述。
圖31至圖37、圖38A至圖38B及圖39為在用於形成根據另一實施例之封裝結構的製程期間之中間步驟的視圖。此實施例相似於先前實施例,惟如下情形除外:在此實施例中,貫穿通路136中之至少一者形成於重佈層(參見圖37中之190)上。另外,如在先前實施例中,此
實施例之視圖僅展示正形成的封裝結構之部分(例如,封裝結構之左邊部分,而下方無載體基板),但可鄰近於此結構形成相似製程及結構,其將引起相似於圖22之先前實施例中所說明之結構的整體結構。在本文中將不重複相似於針對先前描述之實施例之細節的關於此實施例之細節。
圖31處於與上文所描述之圖4相似的處理點,且在本文中不重複直至此點所執行之製程及步驟。圖31包括積體電路晶粒114、晶粒連接器126、介電材料128、包封物130及晶種層132。
在圖32中,接著在晶種層132上形成及圖案化光阻劑180。光阻劑180可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑180之圖案對應於晶粒連接器126,其中開口中之至少一者寬於開口中之至少一個其他者以對應於隨後形成之重佈層190。圖案化形成通過光阻劑180之開口以曝光在晶粒連接器126上方之晶種層132。
在圖33中,將導電材料形成於光阻劑180之開口中及晶種層132之經曝光部分上以形成導電構件190及192。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。在一些實施例中,導電構件190相較於導電構件192較大(例如,在圖33之剖面圖中較寬及/或具有較大頂部表面區域)。導電構件190形成重佈層190以允許隨後形成之對應貫穿通路136側向地移動且在鄰近貫穿通路136之間提供較多空間,此允許較大間距S1及S2(參見圖38A至圖38B)。
在圖34中,移除光阻劑180。可藉由可接受的灰化或剝離製程來移除光阻劑180,諸如使用氧電漿或其類似者。
在圖35中,接著在導電構件190及192上形成及圖案化光阻劑134。光阻劑134可藉由旋塗或其類似者而形成,且可曝光於光以供圖案化。光阻劑134之圖案對應於導電構件190及192。圖案化形成通過
光阻劑134之開口以曝光導電構件190及192。
在圖36中,將導電材料形成於光阻劑134之開口中及導電構件190及192之經曝光部分上以形成貫穿通路136。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。
在圖37中,移除光阻劑134及未形成有導電構件190及192的晶種層132之部分。可藉由可接受的灰化或剝離製程來移除光阻劑134,諸如使用氧電漿或其類似者。一旦移除光阻劑134,就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層132之經曝光部分。晶種層132之剩餘部分及導電材料形成貫穿通路136以及導電構件190及192。如圖37所說明,兩個貫穿通路136及一個重佈層190形成於積體電路晶粒114上方且耦接至積體電路晶粒114,且在其他實施例中,較多或較少貫穿通路136及/或重佈層190可形成於積體電路晶粒114上方且耦接至積體電路晶粒114。
導電構件190形成重佈層190以允許對應貫穿通路136側向地移動且在鄰近貫穿通路136之間提供較多空間。鄰近貫穿通路136之間的此較大空間允許鄰近貫穿通路136之側壁之間的較大間距S1(參見圖38B),此亦實現對應鄰近金屬化圖案158之側壁之間的較大間距S2。另外,在此實施例中,重佈層190可用以重佈某一輸入/輸出(I/O),諸如電力線及接地線(參見(例如)圖46A至圖46C)。
在圖38A及圖38B中,已如上文在圖8及圖9中所描述而附接及形成積體電路晶粒138及包封物152,且在本文中不重複描述。另外,如上文參考圖10、圖11及圖12A至圖12B所描述而形成介電層154、金屬化圖案158、通路156及佈線160,惟如下情形除外:在此實施例中,歸因於重佈層190側向地移動貫穿通路136中之至少一者,間距S1及S2可大於圖12A至圖12B中之間距S1及S2。因此,在此實施例中,歸因
於增加的間距S1及S2,在鄰近金屬化圖案158之間可存在較多佈線160。
在圖39中,處理繼續形成前側重佈結構172、墊174及連接器176。用以形成前側重佈結構172、墊174及連接器176之步驟及製程可相似於上文在圖13至圖22中所描述之步驟及製程,且在本文中不重複描述。
圖40至圖43、圖44A至圖44B及圖45為在用於形成根據另一實施例之封裝結構的製程期間之中間步驟的視圖。此實施例相似於先前實施例,惟如下情形除外:在此實施例中,晶粒連接器126中之至少一者被形成為重佈層(參見圖40中之198)。另外,如在先前實施例中,此實施例之視圖僅展示正形成的封裝結構之部分(例如,封裝結構之左邊部分且下方排除載體基板),但可鄰近於此結構形成相似製程及結構,其將引起相似於圖22之先前實施例中所說明之結構的整體結構。在本文中將不重複相似於針對先前描述之實施例之細節的關於此實施例之細節。
圖40處於與上文所描述之圖2相似的處理點,且在本文中不重複直至此點所執行之製程及步驟。圖40包括半導體基板118、墊122、晶粒連接器126及鈍化膜124。如所說明,晶粒連接器126中之一者包括與晶粒連接器126同時地形成之導電構件198。可藉由在鈍化膜124之開口中及在墊122之經曝光部分上形成導電材料而形成晶粒連接器126及導電構件198。導電材料可藉由鍍覆而形成,諸如電鍍或無電式電鍍或其類似者。導電材料可包含金屬,比如銅、鈦、鎢、鋁或其類似者。在一些實施例中,導電構件198相較於不包括導電構件198之晶粒連接器126較大(例如,在圖40之剖面圖中較寬及/或具有較大頂部表面區域)。導電構件198形成重佈層198以允許隨後形成之對應貫穿通路136側向地移動且在鄰近貫穿通路136之間提供較多空間,此允許較
大間距S1及S2(參見圖44A至圖44B)。
在圖41中,將介電材料128形成於積體電路晶粒114之主動側上,諸如形成於鈍化膜124、晶粒連接器126及重佈層198上。
在圖42中,在形成介電材料128之後,可諸如藉由鋸割或切割而單粒化積體電路晶粒114,且使用(例如)取置型工具將積體電路晶粒114黏著至載體基板(未圖示,但參見圖2中之載體基板100)。包封物130形成於各種組件上。包封物130可為模塑料、環氧樹脂或其類似者,且可藉由壓縮成型、轉注成型或其類似者予以施加。在固化之後,包封物130可經歷研磨製程(例如,CMP製程)以曝光晶粒連接器126及重佈層198。晶粒連接器126、重佈層198及包封物130之頂部表面在研磨製程之後共面。在一些實施例中,可(例如)在晶粒連接器126及重佈層198已經被曝光的情況下省略研磨。
在圖43中,將貫穿通路136形成於晶粒連接器126及重佈層198上。重佈層198允許對應貫穿通路136側向地移動且在鄰近貫穿通路136之間提供較多空間。鄰近貫穿通路136之間的此較大空間允許鄰近貫穿通路136之側壁之間的較大間距S1(參見圖44B),此亦實現對應鄰近金屬化圖案158之側壁之間的較大間距S2。另外,在此實施例中,重佈層198可用以重佈某一輸入/輸出(I/O),諸如電力線及接地線(參見(例如)圖46A至圖46C)。
如圖43所說明,兩個貫穿通路136及一個重佈層198形成於積體電路晶粒114上方且耦接至積體電路晶粒114,且在其他實施例中,較多或較少貫穿通路136及/或重佈層198可形成於積體電路晶粒114上方且耦接至積體電路晶粒114。
在圖44A及圖44B中,已如上文在圖8及圖9中所描述而附接及形成積體電路晶粒138及包封物152,且在本文中不重複描述。另外,如上文參考圖10、圖11及圖12A至圖12B所描述而形成介電層154、金屬
化圖案158、通路156及佈線160,惟如下情形除外:在此實施例中,歸因於重佈層198側向地移動貫穿通路136中之至少一者,間距S1及S2可大於圖12A至圖12B中之間距S1及S2。因此,在此實施例中,歸因於增加的間距S1及S2,在鄰近金屬化圖案158之間可存在較多佈線160。
在圖45中,處理繼續形成前側重佈結構172、墊174及連接器176。用以形成前側重佈結構172、墊174及連接器176之步驟及製程可相似於上文在圖13至圖22中所描述之步驟及製程,且在本文中不重複描述。
圖46A、圖46B及圖46C為根據一些實施例之輸入/輸出組態的俯視圖。舉例而言,在圖46A中,晶粒連接器126係以柵格圖案而佈置,其中對應貫穿通路136係在晶粒連接器126上方且與晶粒連接器126對準。在此實例中,一列中之每一晶粒連接器126係用於一特定功能(例如,接地連接器、訊號連接器、電力連接器等等),其中每一列特定功能晶粒連接器126係與另一列相同特定功能晶粒連接器126分離。舉例而言,如所說明,兩個訊號功能列係由一電力功能列分離。
圖46B及圖46C說明貫穿通路136中之至少一些耦接至重佈層190/198的實例。此等重佈層190/198允許與其耦接之貫穿通路136移動,且因此可允許未側向地移動之貫穿通路136之間的較多佈線間距。在一些實施例中,重佈層190/198允許將電力訊號及接地訊號合併至較少貫穿通路136,此可釋放(例如)耦接至訊號連接器之貫穿通路136之間的較多佈線空間。
晶粒連接器126、貫穿通路136及重佈層190/198之此等組態僅為例示性實施例,且晶粒連接器126、貫穿通路136及重佈層190/198之其他組態係在本揭露之預期範疇內。
儘管所揭露之實施例包括堆疊式晶粒結構,但可將該等實施例
之教示應用於在封裝中僅具有一個晶粒層之封裝結構。舉例而言,在圖22中,可省略積體電路晶粒114,且貫穿通路136可形成用於僅具有一個晶粒層(例如,包括積體電路晶粒138之層)之封裝結構的後側重佈結構。
本揭露之實施例增加鄰近貫穿通路136之側壁之間的間距(例如,間距S1),此增加對應鄰近金屬化圖案158之側壁之間的間距(例如,間距S2)。藉由具有較大間距S2,存在較多空間以供佈線160通過鄰近金屬化圖案158之間。此可允許較多及/或較寬佈線160通過鄰近金屬化圖案158之間。
一實施例為一種方法,其包括形成一第一封裝。該形成該第一封裝包括鄰近於一第一晶粒而形成一貫穿通路,藉由一包封物來至少側向地包封該第一晶粒及該貫穿通路,及在該第一晶粒、該貫穿通路及該包封物上方形成一第一重佈結構。該形成該第一重佈結構包括在該貫穿通路上形成一第一通路,及在該第一通路上形成一第一金屬化圖案,該第一金屬化圖案之至少一個側壁直接地覆蓋該貫穿通路。
另一實施例為一種方法,其包括形成一第一封裝。該形成該第一封裝包括:鄰近於一第一晶粒而形成一第一貫穿通路及一第二貫穿通路,該第一貫穿通路及該第二貫穿通路之鄰近側壁被分離達一第一距離;藉由一包封物來至少側向地包封該第一晶粒、該第一貫穿通路及該第二貫穿通路;及在該第一晶粒、該第一貫穿通路、該第二貫穿通路及該包封物上方形成一第一重佈結構。該形成該第一重佈結構包括在該第一貫穿通路上形成一第一通路,在該第二貫穿通路上形成一第二通路,在該第一通路上形成一第一金屬化圖案,及在該第二通路上形成一第二金屬化圖案,該第一金屬化圖案及該第二金屬化圖案之鄰近側壁被分離達一第二距離,該第二距離大於該第一距離。
一另外實施例為一種結構,其包括:鄰近於一第一晶粒之一第
一貫穿通路及一第二貫穿通路,該第一貫穿通路及該第二貫穿通路之鄰近側壁被分離達一第一距離;至少側向地環繞該第一晶粒、該第一貫穿通路及該第二貫穿通路之一包封物;在該第一貫穿通路上之一第一通路;在該第二貫穿通路上之一第二通路;在該第一通路上之一第一金屬化圖案;及在該第二通路上之一第二金屬化圖案,該第一金屬化圖案及該第二金屬化圖案之鄰近側壁被分離達一第二距離,該第二距離大於該第一距離。
前文概述若干實施例之特徵,使得熟習此項技術者可較佳地理解本揭露之態樣。熟習此項技術者應瞭解,其可易於使用本揭露作為設計或修改用於實行本文中所介紹之實施例之相同目的及/或達成該等實施例之相同優點的其他製程及結構的基礎。熟習此項技術者亦應認識到,此等等效構造並不脫離本揭露之精神及範疇,且其可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、替換及更改。
100‧‧‧載體基板
102‧‧‧離型層
114‧‧‧積體電路晶粒
136‧‧‧導電構件/貫穿通路/貫穿成型通路
138‧‧‧積體電路晶粒
168‧‧‧金屬化圖案
170‧‧‧介電層
172‧‧‧前側重佈結構
174‧‧‧墊
176‧‧‧外部電連接器
Claims (10)
- 一種方法,其包含:形成一第一封裝,該形成該第一封裝包含:鄰近於一第一晶粒而形成一貫穿通路;藉由一包封物來至少側向地包封該第一晶粒及該貫穿通路;在該第一晶粒、該貫穿通路及該包封物上方形成一第一重佈結構,該形成該第一重佈結構包含:在該貫穿通路上形成一第一通路;及在該第一通路上形成一第一金屬化圖案,該第一金屬化圖案之至少一個側壁直接地覆蓋該貫穿通路。
- 如請求項1之方法,其中該形成該貫穿通路進一步包含:形成具有一第一寬度的該貫穿通路之一第一部分,該第一寬度係在一第一平面中量測,該第一平面平行於該第一晶粒之一主表面;及在該貫穿通路之該第一部分上形成該貫穿通路之一第二部分,該第二部分具有一第二寬度,該第二寬度係在該第一平面中量測。
- 如請求項2之方法,其中該貫穿通路之該第一部分的一底部表面係與該第一晶粒之一後側表面共面,且其中該貫穿通路之該第二部分的一頂部表面係與該第一晶粒之一主動表面共面。
- 如請求項1之方法,其進一步包含:鄰近於該第一金屬化圖案而形成一第二金屬化圖案,該第二金屬化圖案係與該第一金屬化圖案處於同一水平,該第一重佈結構之一介電材料介於該第一金屬化圖案與該第二金屬化圖案 之間。
- 如請求項1之方法,其進一步包含:在該鄰近於該第一晶粒而形成該貫穿通路之前,將該第一晶粒之一第一側黏著至一第二晶粒之一第一側。
- 如請求項5之方法,其中該第一晶粒之該第一側為該第一晶粒之一後側表面,且其中該第二晶粒之該第一側為該第二晶粒之一主動表面。
- 如請求項5之方法,其進一步包含:在該鄰近於該第一晶粒而形成該貫穿通路之前,在該第二晶粒上方形成一重佈層且電耦接至該第二晶粒,其中該貫穿通路形成於該重佈層上。
- 如請求項5之方法,其中該鄰近於該第一晶粒而形成該貫穿通路進一步包含:在該第二晶粒上方形成該貫穿通路,該貫穿通路電耦接至該第二晶粒。
- 一種方法,其包含:形成一第一封裝,該形成該第一封裝包含:鄰近於一第一晶粒而形成一第一貫穿通路及一第二貫穿通路,該第一貫穿通路及該第二貫穿通路之鄰近側壁被分離達一第一距離;藉由一包封物來至少側向地包封該第一晶粒、該第一貫穿通路及該第二貫穿通路;在該第一晶粒、該第一貫穿通路、該第二貫穿通路及該包封物上方形成一第一重佈結構,該形成該第一重佈結構包含:在該第一貫穿通路上形成一第一通路;在該第二貫穿通路上形成一第二通路;在該第一通路上形成一第一金屬化圖案;及 在該第二通路上形成一第二金屬化圖案,該第一金屬化圖案及該第二金屬化圖案之鄰近側壁被分離達一第二距離,該第二距離大於該第一距離。
- 一種結構,其包含:鄰近於一第一晶粒之一第一貫穿通路及一第二貫穿通路,該第一貫穿通路及該第二貫穿通路之鄰近側壁被分離達一第一距離;至少側向地環繞該第一晶粒、該第一貫穿通路及該第二貫穿通路之一包封物;在該第一貫穿通路上之一第一通路;在該第二貫穿通路上之一第二通路;在該第一通路上之一第一金屬化圖案;及在該第二通路上之一第二金屬化圖案,該第一金屬化圖案及該第二金屬化圖案之鄰近側壁被分離達一第二距離,該第二距離大於該第一距離。
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