TW201828439A - 半導體裝置以及半導體裝置製造方法 - Google Patents

半導體裝置以及半導體裝置製造方法 Download PDF

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TW201828439A
TW201828439A TW106120018A TW106120018A TW201828439A TW 201828439 A TW201828439 A TW 201828439A TW 106120018 A TW106120018 A TW 106120018A TW 106120018 A TW106120018 A TW 106120018A TW 201828439 A TW201828439 A TW 201828439A
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molding compound
tiv
layer
package
die
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TW106120018A
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TWI720209B (zh
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林俊成
施應慶
王卜
余振華
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種半導體裝置。該半導體裝置包括：一底部封裝，其中在導體與貫穿通路之間的一接觸表面積實質上等於該貫穿通路之一橫截面積，且該底部封裝包括：一模塑料；一貫穿通路，其穿透該模塑料；一晶粒，其模製在該模塑料中；及一導體，其在該貫穿通路上。亦揭示一種製造半導體裝置之相關聯方法。

Description

半導體裝置以及半導體裝置製造方法
本發明實施例係有關半導體裝置以及半導體裝置製造方法。
隨著半導體技術之演進，半導體晶片/晶粒逐漸變小。同時，需將更多功能整合至半導體晶粒中。相應地，半導體晶粒需將更多數目個I/O墊封裝至更小區中，且I/O墊之密度隨時間而快速上升。因此，半導體晶粒之封裝變得更加困難，此負面影響封裝之良率。如何降低生產複雜性及封裝成本已成為該領域亟待解決的問題。
根據本發明的一實施例，一種半導體裝置包含一底部封裝，該底部封裝包括：一模塑料；一貫穿通路，其穿透該模塑料；一晶粒，其在該模塑料中模製；及一導體，其在該貫穿通路上；其中在該導體與該貫穿通路之間之一接觸表面積實質上等於該貫穿通路之一橫截面積。 根據本發明的一實施例，一種半導體裝置包含：一底部封裝，其包括一模塑料、穿透該模塑料之一貫穿通路及在該模塑料中模製之一晶粒；一導體，其在該貫穿通路上；一頂部封裝，其在該底部封裝上方且透過該導體接合至該底部封裝；及一底膠填充，其在該頂部封裝與該底部封裝之間；其中該貫穿通路在形成該導體之一側處自該模塑料突出小於約1微米。 根據本發明的一實施例，一種製造一半導體裝置之方法，該方法包含：提供一載體；在該載體上形成一犧牲層；在該犧牲層上方形成一貫穿通路；在該犧牲層上放置一晶粒；在該犧牲層上形成一模塑料以填充該晶粒與該貫穿通路之間之間隙；在該晶粒、該貫穿通路及該模塑料上方形成一重佈層；移除該載體及該犧牲層以暴露該貫穿通路及該模塑料之一個末端；在該貫穿通路之該末端上放置一導體；及放置一底膠填充以圍繞該導體，其中該底膠填充與該模塑料實體接觸。
下列揭露內容提供用於實施所提供標的物之不同構件之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不旨在限制。舉例而言，在下列描述中之一第一構件形成於一第二構件上方或上可包含其中該第一構件及該第二構件經形成直接接觸之實施例，且亦可包含其中額外構件可形成在該第一構件與該第二構件之間，使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭露可在各個實例中重複參考符號及/或字母。此重複係用於簡化及清楚之目的且本身並不指示所論述的各種實施例及/或組態之間的關係。 此外，為便於描述，可在本文中使用空間相對術語(諸如「在……下方」、「在……下」、「下」、「在……上」、「上」及類似者)以描述一個元件或構件與另一(若干)元件或構件之關係，如圖中所繪示。空間相對術語旨在涵蓋除在圖中描繪之定向以外的在使用或操作中之裝置之不同定向。設備可經另外定向(旋轉90度或以其他定向)，且因此可同樣解釋本文中所使用之空間相對描述符。 雖然闡述本揭露之廣泛範疇之數值範圍及參數為近似值，但已儘可能精確地報告特定實例中所闡述之數值。然而，任何數值本就包含由各自試驗測量中所得到的標準偏差引起之某些必然誤差。又，如本文中使用，術語「大約」一般意謂在一給定值或範圍之10%、5%、1%或0.5%內。替代地，當由一般技術者考慮時，術語「大約」意謂在一可接受平均值標準誤差內。除了在操作/工作實例中外，或除非另有明確指定，否則所有數值範圍、數量、值及百分比(諸如材料數量、持續時間、温度、操作條件、數量比及本文揭示之其等之類似物之數值範圍、數量、值及百分比)應理解為在所有例項中被術語「大約」修飾。因此，除非相反地指示，否則本揭露及隨附發明申請專利範圍中闡述之數值參數係可視需要變化之近似值。最起碼，應至少鑒於所報告之有效數字且藉由應用普通捨位技術解釋各數值參數。本文將範圍表達為從一個端點至另一端點或在兩端點之間。除非另有指定，否則本文揭示之所有範圍包含該等端點。 根據各種例示性實施例，提供無雷射鑽孔製程之一整合扇出(InFO)封裝及其形成方法。繪示形成InFO封裝之中間階段。論述實施例之變動。貫穿各個視圖及闡釋性實施例，相似的元件符號用來指定相似的元件。 圖1至圖13係根據一些例示性實施例之一封裝結構之製造中之中間階段之橫截面圖。參考圖1，提供一載體20。該載體20可經組態以提供結構剛度或用於沉積後續非剛性層之基底。在一項實施例中，載體20可為玻璃載體、陶瓷載體或類似物。例如，在一些實施例中，載體20可替代地為晶圓、半導體、金屬、具有合適形貌及結構剛度之合成或其他材料。參考圖2，在載體20上形成一犧牲層24而不形成一介電層(例如：聚合物層)，該介電層在現有製程中通常在一後續晶種層形成之前形成。舉例來說，此處省略之介電層可為聚醯亞胺、聚苯并㗁唑(PBO)、苯并環丁烯(BCB)、味之素增建膜(ABF)、防焊膜(SR)或類似物。實施例之概念係使用犧牲層24以取代現有介電層，且藉此達成省去現有製程中所需的雷射鉆孔製程之目的。在以段落中將描述相關聯細節。 又，如圖2中繪示，例如透過物理氣相沉積(PVD)或金屬箔積層在犧牲層24上形成一晶種層26。晶種層26可包括銅、銅合金、鋁、鈦、鈦合金或其組合物。在一些實施例中，晶種層26包括鈦層26A及在鈦層26A上方之銅層26B。然而，此並非本揭露之限制。在替代實施例中，晶種層26係銅層。 參考圖3，在晶種層26上方塗敷一光阻劑28且基於電路設計需求圖案化光阻劑28。因此，在光阻劑28中形成開口30以暴露晶種層26之一些部分。 如圖4中所示，透過鍍覆(其可為電鍍或無電式電鍍)在開口30中形成金屬構件32。金屬構件32被鍍覆在晶種層26之暴露部分上且可實質上填充開口30。金屬構件32可包括銅、鋁、鎢、鎳、焊料或其合金。金屬構件32之俯視形狀可為長方形、正方形、圓形或類似者。金屬構件32之高度可根據圖7中之隨後放置晶粒34之厚度而設計，其中在一些實施例中金屬構件32之高度可大於晶粒34之厚度。在鍍覆金屬構件32後，移除光阻劑28，且在圖5中展示所得結構。在移除光阻劑28後，暴露晶種層26由光阻劑28所覆蓋之部分。 參考圖6，執行一蝕刻步驟以移除晶種層26之暴露部分，其中蝕刻可為各向異性蝕刻。另一方面，晶種層26由金屬構件32重疊之部分保持未蝕刻。貫穿描述，金屬構件32及晶種層26之剩餘底層部分結合稱作貫穿InFO通路(TIV) 33，其等亦稱作貫穿通路33。雖然晶種層26被展示為與金屬構件32分離之一層，但當晶種層26係由類似或相同於各自上覆金屬構件32之一材料形成時，晶種層26可與金屬構件32合併而在其等之間不具有可區分界面。在替代實施例中，可區分界面存在於晶種層26與上覆金屬構件32之間。 圖7繪示將裝置晶粒34放置在犧牲層24上方。裝置晶粒34可透過(若干)黏著層36黏著至犧牲層24。在一項實施例中，黏著層36可為膠帶或晶粒附著膜(DAF)，或替代地可為經由旋塗製程或類似物塗敷至犧牲層24之膠液或環氧樹脂。裝置晶粒34之應用不限於一單晶粒之應用，此係因為本揭露可包括一個以上晶粒。在一些實施例中，裝置晶粒34可具有用於將電連接能力提供至裝置晶粒34內之電路(未展示)之一或多個基座，其等例如可為接點、接腳、安裝墊、焊盤或類似物。裝置晶粒34可包括各種被動及主動微電子裝置(未展示)，例如電阻器、電容器、電感器、二極體、金屬氧化物半導體場效電晶體(MOSFET)、互補MOS (CMOS)電晶體、雙極接面電晶體(BJT)、橫向擴散MOS (LDMOS)電晶體、高功率MOS電晶體、FinFET電晶體、其他類型的電晶體及/或其之任一組合。裝置晶粒34可為其中包括邏輯電晶體之邏輯裝置晶粒。在一些例示性實施例中，裝置晶粒34經設計用於行動應用，且可為中央計算裝置(CPU)晶粒、電力管理積體電路(PMIC)晶粒、收發器(TRX)晶粒或類似物。裝置晶粒34之各者包括接觸黏著層36之一半導體基板35 (例如矽基板)，其中半導體基板35之背表面與黏著層36接觸。 在一半導體積體電路製造中採用半導體基板35，且可在半導體基板35中及/或上形成積體電路。半導體基板係指包含半導體材料之任何構造，包括(但不限於)塊體矽、半導體晶圓、絕緣體上矽(SOI)基板或矽鍺基板。亦可使用其他半導體材料，包括III族、IV族及V族元素。半導體基板可進一步包含複數個隔離構件(未展示)，諸如淺溝渠隔離(STI)構件或局部矽氧化(LOCOS) 構件。隔離構件可界定及隔離各種微電子元件。可形成在半導體基板中之各種微電子元件之實例(未展示)包括電晶體(例如金屬氧化物半導體場效電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極接面(BJT)、高電壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體(PFET/NFET)等)；電阻器；二極體；電容器；電感器；熔絲；及其他合適元件。執行各種製程以形成各種微電子元件，包括沉積、蝕刻、佈植、光微影、退火及/或其他合適製程。微電子元件經互連以形成積體電路裝置，例如邏輯裝置、記憶體裝置(例如SRAM)、RF裝置、輸入/輸出(I/O)裝置、系統單晶片(SoC)裝置、其之組合及其他合適類型的裝置。 在一些例示性實施例中，金屬柱40 (諸如銅柱)經形成為裝置晶粒34之頂部且電耦合至諸如裝置晶粒34中之電晶體(未展示)之裝置。在一些實施例中，在各自裝置晶粒34之頂部表面處形成一介電層38，其中金屬柱40具有在介電層38中之至少下部分。在一些實施例中，金屬柱40之頂部表面亦可與介電層38之頂部表面齊平。或者，未形成介電層38，且金屬柱40突出於各自裝置晶粒34之一頂部介電層上方。 參考圖8，在裝置晶粒34及TIV 33上模製一模塑料42。模塑料42填充裝置晶粒34與TIV 33之間之間隙，且可與犧牲層24接觸。在一些實施例中，裝置晶粒34之金屬柱40之間的間隙亦可由模塑料42填充。在一些實施例中，可預先填充裝置晶粒34之金屬柱40之間的間隙。作為實例，模塑料42可包括絕緣材料，諸如環氧樹脂、樹脂、填充物材料、應力釋放劑(SRA)、黏著促進劑、其他材料或其組合。模塑料42可在實質上液體時塗敷，且接著可透過諸如環氧樹脂或樹脂中之一化學反應而固化。在另一實施例中，模塑料42可為一紫外線(UV)或熱固化聚合物，其作為能夠放置於裝置晶粒34及TIV 33周圍之凝膠或可延展固體而塗敷。在採用紫外線或熱固化模塑料42之一實施例中，模塑料42可使用與成型區之周邊接界之一模具(諸如一晶圓或封裝)形成在適當位置中。 接著，可部分移除模塑料42。在一些實施例中，模塑料42可經歷一研磨步驟以自裝置晶粒34及TIV 33移除過量材料。在此一實施例中，模塑料42可經受化學機械拋光、純機械拋光、化學蝕刻或另一合適還原製程。在一些實施例中，所得還原模塑料42可具有在TIV 33及裝置晶粒34之頂部表面處或下方之一頂部表面。在例示性實施例中，TIV 33及裝置晶粒34之頂部表面可實質上與模塑料42之頂部表面齊平。因此，可在模塑料42之拋光側處暴露TIV 33及裝置晶粒34之第一末端使得電接點形成在TIV 33及裝置晶粒34上。在一些實施例中，研磨亦可降低TIV 33及裝置晶粒34之高度。 在圖9中展示所得結構。歸因於研磨，金屬構件32之頂端32A實質上與金屬柱40之頂端40A齊平(共面)，且實質上與模塑料42之頂部表面42A齊平(共面)。由於研磨，金屬殘留物(諸如金屬顆粒)可經產生且留在頂部表面32A、40A及42A上。因此，在研磨之後，可例如透過一清潔操作執行清潔使得移除金屬殘留物。 接著，參考圖10，在模塑料42上方形成重佈線(RDL) 44以連接至金屬柱40及TIV 33。RDL 44亦可使金屬柱40及TIV 33互連。根據各種實施例，一或複數個介電層46形成在圖9中所示之結構上方，其中RDL 44形成在介電層46中。在一些實施例中，形成RDL 44及介電層46之一層包括：形成一毯覆式銅晶種層；在該毯覆式銅晶種層上方形成並圖案化一遮罩層；執行鍍覆以形成RDL 44；移除遮罩層；及執行蝕刻以移除毯覆式銅晶種層未由RDL 44所覆蓋之部分。在替代實施例中，RDL 44藉由沉積金屬層、圖案化金屬層而形成且填充RDL 44與介電層46之間的間隙。RDL 44可包含一金屬或一金屬合金，包括鋁、銅、鎢及/或其合金。圖10繪示RDL 44之兩層，但取決於各自封裝之繞線要求，可存在RDL之一個或兩個以上層。在此等實施例中，介電層46可包含聚合物，諸如聚醯亞胺、苯并環丁烯(BCB)、聚苯并㗁唑(PBO)或類似物。或者，介電層46可包括無機介電材料，諸如氧化矽、氮化矽、碳化矽、氮氧化矽或類似物。 圖11繪示根據一些例示性實施例形成電連接器48。形成電連接器48可包括在RDL 44之暴露部分上放置焊球(或凸塊下金屬(若形成，未展示))且接著使焊球回銲。在替代實施例中，形成電連接器48包括執行鍍覆步驟以在RDL 44上方形成銲料區域，且接著使焊料區域回銲。電連接器48亦可包括金屬柱或金屬柱及銲料帽，其等亦可透過鍍覆形成。貫穿描述，將包括裝置晶粒34、TIV 33、模塑料42、上方RDL 44及介電層46以及犧牲層24之組合結構稱為TIV封裝50，其可為一複合晶圓。 接著，TIV封裝50一起自載體20卸離。犧牲層24亦連同載體20一起移除。在圖12中展示所得結構。如以上段落中所提及，實施例之概念係使用犧牲層24取代現有介電層。由於犧牲層24能夠在卸離載體20時移除，故TIV 33、模塑料42及黏著層36經暴露且藉此達成省去對習知介電層操作之雷射鉆孔製程之目的以便敞開習知介電層且暴露TIV。此外，根據本揭露之一些實施例，亦省去習知介電層之回蝕刻，且因此TIV 33與模塑料42之間的步階高度可小於約1微米。換言之，TIV 33可與模塑料42之頂部表面齊平或自模塑料42突出約小於1微米。 在一些實施例中，可將TIV封裝50鋸切成複數個TIV封裝60，且在TIV 33之末端上放置導體以形成圖13中所示之銲料區域68。圖13繪示一頂部封裝62至TIV封裝60之接合，其中該接合可透過銲料區域(例如焊球) 68。在一些實施例中，銲料區域68可為透過TIV 33 連結至TIV封裝60之頂部封裝62之焊球。在例示性實施例中，銲料區域68完全接觸並覆蓋對應TIV 33之暴露頂部表面。由於對應TIV 33之頂部表面經暴露而未由習知介電層覆蓋，故各銲料區域68與對應TIV 33之間的接觸表面積實質上等於TIV 33之橫截面積。 貫穿描述，TIV封裝60亦稱為底部封裝60，此係由於其等可充當底部封裝。在一些實施例中，頂部封裝62包括接合至一封裝基板64之裝置晶粒66。裝置晶粒66可包括一(若干)記憶體晶粒，其可為例如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒或類似物。 在一些實施例中，將經接合頂部封裝62及TIV封裝60進一步接合至另一封裝組件72 (其可為一封裝基板)。然而，此並非本揭露之限制。在一些實施例中，底膠填充74經施配以與模塑料42接觸且至少圍繞銲料區域68。在一些實施例中，底膠填充74可包括如針對模塑料42描述之類似材料。在一些實施例中，作為實例，底膠填充74可包括苯甲醇、環氧樹脂、氧化矽及/或其他材料。 在一些實施例中，可使用一底膠材料施配工具或系統塗敷底膠材料42。作為實例，可使用螺旋技術及一施配閥塗敷底膠填充74。在一些實施例中，底膠填充74在塗敷時係液體使得其在底部封裝60與頂部封裝62之間的複數個銲料區域68之間及周圍流動。接著使底膠填充74固化或允許底膠填充74乾燥使得其形成固體。 在一替代實施例中，封裝組件72包含一印刷電路板(PCB)。封裝組件72可具有相對側上之電連接器76 (諸如金屬墊或金屬柱)及使電連接器76互連之金屬跡線78。 圖14係根據本揭露之一實施例之圖12之區A之放大圖。如上文所提及，例示性實施例藉由使用犧牲層24取代現有介電層而揭示一新穎半導體裝置及相關聯方法。由於犧牲層24能夠在使載體20脫膠時連同載體20一起移除，故可自然地暴露TIV 33之晶種層26之頂端26A。以此方式，可略過對現有介電層執行以便敞開現有介電層並暴露TIV之習知雷射鑽孔製程。此外，亦可省去現有介電層之習知回蝕刻製程。由於回蝕刻製程或多或少可傷害或損害模塑料42下方，故可放大一現有結構中之TIV與模塑料之間之一步階高度。 通常，使用回蝕刻製程以移除現有介電層之習知結構可在TIV與模塑料之間具有大於1微米之一步階高度。然而，在本揭露中，如圖14中所示，根據本揭露之一些實施例，在TIV 33與模塑料42之間之一步階高度h經控制而小於約1微米。換言之，如圖14中所示，根據本揭露之一些實施例，在TIV 33之晶種層26之頂端26A與鄰近模塑料42之間之步階高度h可小於約1微米。即，TIV 33之晶種層26之頂端26A可實質上與鄰近模塑料42齊平；或TIV 33之晶種層26之頂端26A可自鄰近模塑料42突出約小於1微米。 圖15係根據本揭露之一實施例之圖13之區B之放大圖。如上文所提及，例示性實施例藉由使用犧牲層24取代現有介電層而揭示一新穎半導體裝置及相關聯方法。由於犧牲層24能夠在使載體20脫膠時連同載體20一起移除，故可自然地暴露TIV 33之晶種層26之頂端26A。以此方式，對現有介電層執行以便敞開現有介電層並暴露TIV之習知雷射鑽孔製程變得不必要。對於習知結構，現有介電層可仍或多或少覆蓋TIV之頂端之一部分，尤其自俯視圖觀看時TIV之外環之邊界周圍之部分。因此，在未採用回蝕刻製程時之該等情況中，需形成在TIV上之後續銲料區域可藉由TIV之外環之邊界周圍之介電層而與TIV之頂端部分分離。TIV與銲料區域之間之不完全結合可降低電特性及剝落之可能性。 在例示性實施例中，完全暴露TIV 33之晶種層26之頂端。因此，銲料區域68可完全接觸且完全覆蓋TIV 33之晶種層26之頂端。由於TIV 33之頂端經暴露而未由習知介電層部分覆蓋，故在各銲料區域68與對應TIV 33之間之接觸表面積s1實質上等於TIV 33之晶種層26之頂端之面積。在一些實施例中，在各銲料區域68與對應TIV 33之間之接觸表面積s1實質上等於TIV 33之一橫截面積。 亦可包括其他構件及製程。例如，可包括測試結構以輔助3D封裝或3DIC裝置之驗證測試。例如，測試結構可包括形成在一重佈層中或允許測試3D封裝或3DIC、使用探針及/或探針卡及類似物之一基板上之測試墊。驗證測試可對中間結構以及最終結構執行。另外，本文中所揭示之結構及方法可結合併入已知良好晶粒之中間驗證之測試方法論使用以增加良率且降低成本。 本揭露之一些實施例提供一種半導體裝置。該半導體裝置包括：一底部封裝；其中在導體與貫穿通路之間之一接觸表面積實質上等於該貫穿通路之橫截面積，且該底部封裝包括：一模塑料；一貫穿通路，其穿透該模塑料；一晶粒，其模製於該模塑料中；及一導體，其在該貫穿通路上。 本揭露之一些實施例提供一種半導體裝置。該半導體裝置包括：一底部封裝、該底部封裝上方且透過導體接合至該底部封裝之一頂部封裝；及一底膠填充，其在該頂部封裝與該底部封裝之間；其中貫穿通路在該導體所處之一側處自模塑料突出小於約1微米，且該底部封裝包括：一模塑料；一貫穿通路，其穿透該模塑料；一晶粒，其模製於該模塑料中；及一導體，其在該貫穿通路上。 本揭露之一些實施例提供一種製造一半導體裝置之方法。該方法包括：提供一載體；在該載體上形成一犧牲層；在該犧牲層上方形成一貫穿通路；在該犧牲層上放置一晶粒；在該犧牲層上形成一模塑料以填充該晶粒與該貫穿通路之間的間隙；在該晶粒、該貫穿通路及該模塑料上方形成一重佈層；移除該載體及該犧牲層以暴露該貫穿通路及該模塑料之一個末端；在該貫穿通路之該末端上放置一導體；及放置一底膠填充以圍繞該導體，其中該底膠填充與該模塑料實體接觸。 前文概述數項實施例之特徵，使得熟習此項技術者可更佳理解本揭露之態樣。熟習此項技術者應明白，其等可容易將本揭露用作設計或修改其他操作及結構之一基礎以實行本文中介紹之實施例之相同目的及/或達成相同優點。熟習此項技術者亦應認識到，此等等效構造並未脫離本揭露之精神及範疇，且其等可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、置換及更改。 再者，本申請案之範疇並不旨在限於說明書中描述之程序、機器、製造、物質組合物、構件、方法及步驟之特定實施例。一般技術者將容易從本揭露之揭露內容瞭解，可根據本揭露利用執行與本文描述之對應實施例實質上相同之功能或達成與其等實質上相同之結果之當前現有或隨後開發之程序、機器、製造、物質組合物、構件、方法或步驟。因此，隨附發明申請專利範圍旨在將此等程序、機器、製造、物質組合物、構件、方法或步驟包括於其等範疇內。
20‧‧‧載體
24‧‧‧犧牲層
26‧‧‧晶種層
26A‧‧‧鈦層
26B‧‧‧銅層
28‧‧‧光阻劑
30‧‧‧開口
32‧‧‧金屬構件
32A‧‧‧金屬構件之頂端
33‧‧‧貫穿InFO通路(TIV)
34‧‧‧裝置晶粒
35‧‧‧半導體基板
36‧‧‧黏著層
38‧‧‧介電層
40‧‧‧金屬柱
40A‧‧‧金屬柱之頂端
42‧‧‧模塑料
42A‧‧‧模塑料之頂部表面
44‧‧‧重佈線(RDL)
46‧‧‧介電層
48‧‧‧電連接器
50‧‧‧TIV封裝
60‧‧‧TIV封裝
62‧‧‧頂部封裝
64‧‧‧封裝基板
66‧‧‧裝置晶粒
68‧‧‧銲料區域
72‧‧‧封裝組件
74‧‧‧底膠填充
76‧‧‧電連接器
78‧‧‧金屬跡線
A‧‧‧區
B‧‧‧區
s1‧‧‧接觸表面積
h‧‧‧步階高度
在結合附圖閱讀時，可自以下詳細描述最佳理解本揭露之態樣。應注意，根據產業中之標準實踐，各個構件不按比例繪製。實際上，為了清楚論述，可任意增大或減小各個構件之尺寸。 圖1至圖13係根據一些例示性實施例之一封裝結構之製造中之中間階段之橫截面圖； 圖14係根據本揭露之一實施例之圖12之區A之放大圖；及 圖15係根據本揭露之一實施例之圖13之區B之放大圖。

Claims (1)

  1. 一種半導體裝置，其包含： 一底部封裝，其包括： 一模塑料； 一貫穿通路，其穿透該模塑料； 一晶粒，其模製在該模塑料中；及 一導體，其在該貫穿通路上； 其中在該導體與該貫穿通路之間之一接觸表面積實質上等於該貫穿通路之一橫截面積。
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