TW202008478A - 封裝結構的形成方法 - Google Patents

封裝結構的形成方法 Download PDF

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TW202008478A
TW202008478A TW108118652A TW108118652A TW202008478A TW 202008478 A TW202008478 A TW 202008478A TW 108118652 A TW108118652 A TW 108118652A TW 108118652 A TW108118652 A TW 108118652A TW 202008478 A TW202008478 A TW 202008478A
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semiconductor die
conductive
protective layer
semiconductor
forming
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TW108118652A
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English (en)
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TWI816804B (zh
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茅一超
張進傳
盧思維
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台灣積體電路製造股份有限公司
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Abstract

提供封裝結構及其形成方法。方法包含在承載基底上設置第一半導體晶粒，以及形成第一保護層以環繞第一半導體晶粒。方法也包含在第一保護層和第一半導體晶粒上形成介電層。方法更包含將介電層圖案化以形成開口，此開口部分地暴露出第一半導體晶粒和第一保護層。此外，方法包含在形成前述的開口之後，將第二半導體晶粒接合至第一半導體晶粒。方法包含形成第二保護層以環繞第二半導體晶粒。

Description

封裝結構的形成方法
本發明實施例是關於封裝結構的形成方法，特別是有關於具有堆疊的半導體晶粒(die)的封裝結構。
半導體積體電路(integrated circuit，IC)產業經歷了快速的成長。半導體製程持續地進展產生了具有較精密之部件(feature)及高度整合的半導體裝置。功能密度(即每一個晶片區中互相連結的裝置數量)總體上增加，同時部件尺寸(即使用一製造程序可生產的最小組件)縮小。此尺寸縮減製程一般而言提供增加生產效率以及降低相關成本等優勢。
晶片封裝體不只對半導體裝置提供對於外在環境汙染的防護，也對其內部封裝的半導體裝置提供了連接界面。目前已發展高度較小或利用較少面積之小尺寸的封裝結構以對半導體裝置進行封裝。
目前已發展新的封裝技術以進一步提升半導體晶粒的密度和功能。這些相對較新型之半導體晶粒的封裝技術面臨製造流程的挑戰。
根據本發明的一些實施例，提供封裝結構的形成方法。方法包含在承載基底上設置第一半導體晶粒，以及形成第一保護層以環繞第一半導體晶粒。方法也包含在第一保護層和第一半導體晶粒上形成介電層。方法更包含將介電層圖案化以形成開口，此開口部分地暴露出第一半導體晶粒和第一保護層。此外，方法包含在形成前述的開口之後，將第二半導體晶粒接合至第一半導體晶粒。方法更包含形成第二保護層以環繞第二半導體晶粒。
根據本發明的一些實施例，提供封裝結構的形成方法。方法包含形成第一保護層以環繞第一半導體晶粒和第二半導體晶粒。方法也包含形成介電層以覆蓋第一半導體晶粒、第二半導體晶粒和第一保護層。方法更包含在介電層內形成開口，此開口部分地暴露出第一半導體晶粒、第二半導體晶粒和第一保護層。此外，方法包含在形成前述的開口之後，設置第三半導體晶粒以部分地覆蓋第一半導體晶粒和第二半導體晶粒。第三半導體晶粒在第一半導體晶粒與第二半導體晶粒之間形成電性連接。方法更包含形成第二保護層以環繞第三半導體晶粒。
根據本發明的一些實施例，提供封裝結構。封裝結構包含下半導體晶粒和環繞下半導體晶粒的第一保護層。封裝結構也包含部分地覆蓋第一保護層和下半導體晶粒的介電層。封裝結構更包含在下半導體晶粒和第一保護層上的上半導體晶粒。上半導體晶粒經由連接件與下半導體晶粒接合。此外，封裝結構包含環繞連接件的絕緣膜以及環繞上半導體晶粒的第二保護層。
以下揭露提供了很多不同的實施例或範例，用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本揭露的說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，以下敘述中提及第一部件形成於第二部件之上或上方，可能包含第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。此外，本揭露在各種範例中可能重複參考數字及/或字母，此重複是為了簡化和清楚，並非在討論的各種實施例及/或組態之間指定其關係。
再者，空間上相關的用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」和其他類似的用語可用於此，使得描述圖中所示之一元件或部件與其他元件或部件之間的關係更加地容易。此空間上相關的用語可涵蓋除圖式描繪之方向外，使用或操作中的裝置之不同方向。設備可以其他方向定位(旋轉90度或其他方向)，且在此使用的空間相關描述可同樣依此解讀。
以下描述了本發明的一些實施例。可在下述實施例之步驟的前、中、後提供額外的操作。以下描述的一些步驟可在不同的實施例中被取代或刪除。可在半導體裝置結構中加入額外的部件。以下描述的一些部件可在不同的實施例中被取代或刪除。雖然在此討論的一些實施例及操作是以特定的順序予以實施，然而，這些操作可以其他的邏輯順序予以實施。
本發明的一些實施例是與三維(three dimensional，3D)封裝或三維-積體電路(three dimensional integrated circuit，3D-IC)裝置有關。本發明的一些實施例也可包含其他部件和製程。舉例而言，可包含測試結構(testing structure)以幫助對於三維封裝或三維積體電路裝置進行的驗證測試。測試結構可例如包含形成於重佈線層內或形成於基底上的測試接墊(test pad)，以便能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構和最終結構進行驗證測試。另外，可將本文所揭露的結構和方法與包含對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
第1A-1J圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。根據一些實施例，如第1A圖所示，在承載基底100上黏附或放置半導體晶粒104A和104B。可使用黏著層102以固定半導體晶粒104A和104B。
半導體晶粒104A和104B各自包含半導體基底106和形成在半導體基底106上的互連結構107。互連結構107包含多個層間介電層和多個形成在層間介電層內的導電部件。這些導電部件包含導線(conductive line)、導孔(conductive via)及/或導電接觸件(conductive contact)。導電部件的一些部分可作為導電墊。
一些實施例中，在半導體基底106內及/或半導體基底106上形成各種裝置元件。各種裝置元件的範例包含電晶體(例如金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)、互補式金屬氧化物半導體(complementary metal oxide semiconductor，CMOS)電晶體、雙極性接面電晶體(bipolar junction transistor，BJT)、高電壓電晶體、高頻率電晶體、P形通道(p-channel)及/或N型通道(n-channel)場效電晶體(PFET/NFET)等)、二極體(diode)、光感測器、一或多個其他合適的元件、或前述之組合。
裝置元件經由互連結構107互相連接，以形成積體電路裝置。積體電路裝置包含邏輯裝置、記憶體裝置(例如靜態隨機存取記憶體(static random access memories，SRAM))、射頻(radio frequency，RF)裝置、輸入/輸出(input/output，I/O)裝置、系統單晶片(system-on-chip，SoC)裝置、邏輯裝置、一或多個其他合適之類型的裝置、或前述之組合。
一些實施例中，半導體晶粒104A更包含導電部件110A，且半導體晶粒104B更包含導電部件110B。導電部件110A和110B可包含金屬柱。一些實施例中，導電部件110A和110B各自具有垂直的側壁。導電部件110A和110B可由銅、鈦、鈷、金、鉑、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。導電部件110A和110B的形成可使用電鍍(electroplating)製程、物理氣相沉積(physical vapor deposition，PVD)製程、化學氣相沉積(chemical vapor deposition，CVD)製程、一或多個其他合適的製程、或前述之組合。
一些實施例中，半導體晶粒104A和104B各自更包含鈍化層108。鈍化層108係用以保護鈍化層108下方的互連結構107和裝置元件。鈍化層108可包含暴露出導電部件110A和110B的開口。鈍化層108可由聚亞醯胺(polyimide，PI)、聚對苯撐苯並二噁唑(poly-p-phenylenebenzobisthiazole，PBO)、氮化矽、氮氧化矽、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。鈍化層108的形成可使用旋轉塗佈(spin coating)製程、化學氣相沉積(CVD)製程、噴塗(spray coating)製程、一或多個其他合適的製程、或前述之組合。可使用圖案化製程以形成具有預期圖案的鈍化層108。
隨後，根據一些實施例，如第1A圖所示，在承載基底100上形成保護層112。保護層112環繞且覆蓋半導體晶粒104A和104B。保護層112可由模塑(molding)材料(或模塑化合物材料)製成，或者包含上述材料。模塑材料可包含以環氧樹脂為基底的樹脂(epoxy-based resin)，且具有填充物(filler)分散於其中。填充物可包含纖維(例如矽纖維)、粒子(例如矽粒子)、或前述之組合。保護層112的形成可使用射出成型(injecting)製程、旋轉塗佈製程、噴塗製程、一或多個其他合適的製程、或前述之組合。
本揭露的實施例可具有多種變化及/或調整。在其他實施例中，保護層112係由氧化矽、氮氧化矽、氮化矽、碳化矽、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。在這些例子中，保護層112的沉積可使用化學氣相沉積(CVD)製程、旋轉塗佈製程、噴塗製程、一或多個其他合適的製程、或前述之組合。
根據一些實施例，如第1B圖所示，使用平坦化製程以薄化保護層112。結果，暴露出半導體晶粒104A和104B的導電部件110A和110B。一些實施例中，導電部件110A和110B的頂面大抵上與薄化的保護層112的頂面共平面。一些實施例中，保護層112的頂面、鈍化層108的頂面以及導電部件110A和110B的頂面大抵上共平面。平坦化製程可包含研磨(grinding)製程、化學機械拋光(chemical mechanical polishing，CMP)製程、乾式拋光製程、蝕刻製程、切割製程、一或多個其他的製程、或前述之組合。
根據一些實施例，如第1C圖所示，在保護層112以及半導體晶粒104A和104B上形成介電層114。介電層114可用以保護半導體晶粒104A和104B。半導體晶粒104A和104B的導電部件110A和110B由介電層114所覆蓋。
介電層114可由高分子材料製成，或者包含高分子材料。高分子材料可例如包含聚亞醯胺(PI)、聚對苯撐苯並二噁唑(PBO)、一或多個其他合適的高分子材料、或前述之組合。介電層114的形成可使用旋轉塗佈製程、噴塗製程、一或多個其他合適的製程、或前述之組合。
一些其他的實施例中，介電層114係由氧化物材料(例如氧化矽)、氮化物材料(例如氮化矽)、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。在這些例子中，介電層114的沉積可使用化學氣相沉積(CVD)製程、旋轉塗佈製程、噴塗製程、一或多個其他合適的製程、或前述之組合。
根據一些實施例，如第1D圖所示，將介電層114圖案化以形成部分地暴露出半導體晶粒104A和104B的開口116。半導體晶粒104A的一些導電部件110A由開口116所暴露出來，且一些其他的導電部件110A仍然由介電層114所覆蓋。相似地，半導體晶粒104B的一些導電部件110B由開口116所暴露出來，且一些其他的導電部件110B仍然由介電層114所覆蓋。一些實施例中，如第1D圖所示，保護層112在半導體晶粒104A與半導體晶粒104B之間的一部分也由開口116所暴露出來。
一些實施例中，開口116係使用微影(photolithography)製程以形成。一些其他的實施例中，使用微影製程和蝕刻製程以形成開口116。一些其他的實施例中，使用能量束鑽孔(energy beam drilling)製程(例如雷射(laser)鑽孔製程或電子束(electron-beam)鑽孔製程)以形成開口116。
然而，本揭露的實施例不限於此。本揭露的實施例可具有多種變化及/或調整。一些其他的實施例中，未形成介電層114。
根據一些實施例，如第1E圖所示，在介電層114上形成導電元件118和導電柱120。導電元件118可作為凸塊下金屬化(under bump metallization，UBM)結構及/或重佈線(redistribution)層。一些實施例中，導電柱120包含垂直的側壁。導電元件118和導電柱120可由銅、鈷、鎳、鈦、金、鉑、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。導電元件118和導電柱120的形成可包含電鍍製程、物理氣相沉積(PVD)製程、無電電鍍(electroless plating)製程、一或多個其他合適的製程、或前述之組合。
隨後，根據一些實施例，如第1F圖所示，形成或接收半導體晶粒122。半導體晶粒122可用以形成半導體晶粒104A與104B之間的電性連接。半導體晶粒122可作為晶粒與晶粒之間的訊號傳輸媒介。一些實施例中，半導體晶粒122包含多個導電部件，這些導電部件包含導線和導孔。這些導電部件中的每一個皆可與半導體晶粒104A和104B中的裝置元件進行電性連接。半導體晶粒122內的導電部件的線寬或間距可小於約0.4 μm。半導體晶粒122內的導電部件的線寬或間距可在約10 nm至約0.4 μm的範圍內。一些其他的實施例中，半導體晶粒122更包含例如電晶體的裝置元件。一些其他的實施例中，半導體晶粒122並未包含任何裝置元件。
第2A-2F圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。一些實施例中，第2A-2F圖顯示半導體晶粒122之製程中的各個階段。
如第2A圖所示，提供或接收半導體基底124。一些實施例中，半導體基底124為半導體晶圓(wafer)，例如矽晶圓。一些實施例中，在半導體基底124內形成多個導電部件126。一些實施例中，導電部件126自半導體基底124的前表面向半導體基底124的背表面延伸。導電部件126可作為提供垂直方向上之電性連接的導孔。
導電部件126可由銅、鈷、鈦、鋁、鎢、金、鉑、鎳、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。一些實施例中，使用微影製程和蝕刻製程以形成多個穿孔開口(via opening)，這些穿孔開口自半導體基底126的前表面向背表面延伸。隨後，在前表面上設置導電材料層以填充這些穿孔開口。導電材料層的沉積可使用物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、電鍍製程、無電電鍍製程、一或多個其他合適的製程、或前述之組合。
隨後，可實施平坦化製程以移除導電材料層在這些穿孔開口外的部分。結果，導電材料層在穿孔開口內的剩餘部分形成導電部件126。平坦化製程可包含化學機械拋光(CMP)製程、研磨製程、乾式拋光製程、蝕刻製程、一或多個其他合適的製程、或前述之組合。
一些實施例中，在半導體基底124與導電部件126之間形成絕緣層(未繪示)。絕緣層係用以將半導體基底124與導電部件126電性隔離。因此，可防止導電部件126之間形成任何不必要的短路。絕緣層可由氧化矽、氮氧化矽、氮化矽、氧化鍺、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。
一些實施例中，在形成導電材料層之前，在穿孔開口的側壁和底部上沉積絕緣層。絕緣層的沉積可使用化學氣相沉積(CVD)製程、原子層沉積(atomic layer deposition，ALD)製程、物理氣相沉積(PVD)製程、熱氧化製程、一或多個其他合適的製程、或前述之組合。
一些實施例中，如第2A圖所示，在導電部件126上形成導電元件128。導電元件128可用於接收或支撐後續形成的導電凸塊。導電元件128也可用於形成一些導電部件126之間的電性連接。
一些實施例中，如第2A圖所示，在半導體基底124的前表面上形成鈍化層125。鈍化層125可部分地覆蓋導電元件128。一些其他的實施例中，鈍化層125的頂面可與導電元件128的頂面大抵上共平面。鈍化層125可具有暴露出導電元件128的多個開口。鈍化層125的材料和形成方法可相同或相似於半導體晶粒104A或104B的鈍化層108的材料和形成方法。
根據一些實施例，如第2B圖所示，在導電元件128上形成連接件130。連接件130可包含焊料凸塊。焊料凸塊可包含錫和其他金屬材料的合金。一些實施例中，焊料凸塊大抵上不含鉛。一些實施例中，連接件130包含金屬柱。金屬柱可由銅、鈷、鈦、鋁、金、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。金屬柱可包含垂直的側壁。
連接件130的形成方法可包含電鍍製程、無電電鍍製程、物理氣相沉積(PVD)製程、一或多個其他合適的製程、或前述之組合。連接件130的形成方法可更包含回流(reflow)製程、蝕刻製程、或其他合適的製程。一些實施例中，每一個連接件130皆包含焊料凸塊與金屬柱的組合。
根據一些實施例，如第2C圖所示，在半導體基底124上形成覆蓋連接件130的絕緣膜(或非導電膜)132。一些實施例中，絕緣膜132由以環氧樹脂為基底的樹脂製成，或者包含以環氧樹脂為基底的樹脂。根據一些實施例，相似於形成保護層112的模塑材料，絕緣膜132由以環氧樹脂為基底的樹脂製成，且具有填充物分散於其中，或者包含上述材料。填充物可包含纖維(例如矽纖維)、粒子(例如矽粒子)、或前述之組合。一些實施例中，相較於保護層112中的填充物，絕緣膜132具有較低的重量百分比的填充物。一些實施例中，絕緣膜132中填充物的重量百分比在約20 wt%至約30 wt%的範圍內。保護層112中填充物的重量百分比在約50 wt%至約60 wt%的範圍內。一些實施例中，使用貼合(lamination)製程將絕緣膜132形成於連接件130上。一些實施例中，絕緣膜132為有黏性的。
根據一些實施例，如第2D圖所示，部分地移除絕緣膜132以暴露出連接件130。在後續的接合製程之後，暴露的連接件130可用於將半導體晶粒104A和104B的導電部件110A和110B電性連接。
一些實施例中，使用薄化製程以部分地移除絕緣膜132。薄化製程可包含切割製程、研磨製程、乾式拋光製程、化學機械拋光(CMP)製程、蝕刻製程、一或多個其他合適的製程、或前述之組合。一些實施例中，在進行薄化製程的期間也部分地移除連接件130。一些實施例中，如第2D圖所示，在薄化製程之後，連接件130的頂面與絕緣膜132的頂面大抵上共平面。
根據一些實施例，如第2E圖所示，將第2D圖所示的結構貼附至載具202上。載具202可為後續實施切割製程時用以暫時黏著晶圓的切割膠帶(dicing tape)。
根據一些實施例，如第2F圖所示，切割第2E圖所示的結構以形成溝槽204。可使用晶粒切割器(die saw)以形成溝槽204。溝槽204將半導體基底124分隔成多個半導體晶粒122。
隨後，根據一些實施例，如第1F圖所示，將半導體晶粒122的其中一個抬起並放置於半導體晶粒104A和104B上。半導體晶粒122部分地覆蓋半導體晶粒104A和104B。根據一些實施例，半導體晶粒122經由連接件130與半導體晶粒104A和104B接合。由於介電層114被圖案化以暴露出半導體晶粒104A和104B的導電部件110A和110B，可較容易地形成連接件130與半導體晶粒104A和104B的導電部件110A和110B之間的電性連接。一些實施例中，同時將半導體晶粒122與半導體晶粒104A和104B接合在一起。
一些實施例中，將一些連接件130接合至半導體晶粒104A中暴露出的導電部件110A上，且與導電部件110A電性連接。將一些連接件130接合至半導體晶粒104B中暴露出的導電部件110B上，且與導電部件110B電性連接。半導體晶粒122可作為半導體晶粒104A和104B之間傳送電子訊號的傳輸晶粒。
一些實施例中，由於開口116的尺寸較大，可確保在介電層114內形成開口116之圖案化製程的品質。在介電層114的圖案化製程期間，沒有殘餘物留在導電部件110A和110B上，因此使得連接件130與暴露出的導電部件110A和110B之間形成良好的連接。
一些其他的例子中，在介電層114內設計形成較小的開口(例如寬度小於約7 μm的開口)以暴露出導電部件110A和110B。由於相較於形成較大開口的微影製程，形成較小開口的微影製程較為困難，可能發生顯影不足(under-development)的問題。一部分的介電層114可能顯影不足而仍留在導電部件110A和110B的表面上。結果，殘餘物將對連接件130與導電部件110A和110B之間的連接產生負面的影響，如此可能對封裝結構的效能和可靠度產生負面的影響。
一些實施例中，使用熱壓接合(thermal compression bonding)製程將半導體晶粒122與半導體晶粒104A和104B接合。一些實施例中，絕緣膜132具有黏著性。因此，在熱壓接合製程期間，半導體晶粒122係固定於半導體晶粒104A和104B上。絕緣膜132的黏著性促進了熱壓接合製程。
在熱壓接合製程中，可使用晶粒夾具(holder)以夾取並保持半導體晶粒122對於半導體晶粒104A和104B的相對位置。絕緣膜132也可幫助提高半導體晶粒122與半導體晶粒122下方元件之間的黏著性。在熱壓接合製程中，在高溫下對半導體晶粒122施加壓縮壓力，此壓縮壓力可確保連接件130直接接觸半導體晶粒104A和104B的導電部件110A和110B。因此，可避免或降低連接件130與導電部件110A和110B之間的冷結合(cold-joint)問題。
一些實施例中，熱壓接合製程的操作溫度在約150 ℃至約350 ℃的範圍內。一些實施例中，熱壓接合製程施加的壓縮壓力在約1百萬帕(MPa)至約100百萬帕(MPa)的範圍內。然而，一些其他的實施例中，將施加的壓縮壓力及/或操作溫度調整為其他不同的範圍。
熱壓接合製程和有黏性的絕緣膜132可允許半導體晶粒122具有較小的厚度。半導體晶粒122的厚度可在約50 μm至約150 μm的範圍內。由於半導體晶粒122具有較小的厚度，隨後將形成的保護層(例如模塑層)的厚度也可較薄。由於減少了用以形成保護層之模塑材料的量，在後續的熱處理後明顯地降低封裝結構的翹曲度，進而改善了封裝結構的品質和可靠度。
一些其他的例子中，並未使用熱壓接合製程及/或絕緣膜132。舉例而言，使用回流製程以接合半導體晶粒122，且並未施加額外的壓縮壓力。在這些例子中，由於相較於較薄的半導體晶粒，較厚的半導體晶粒較容易夾取，因此半導體晶粒122可能需要具有較大的厚度(例如大於約150 μm)以確保接合製程的平順，並避免冷結合問題的產生。然而，若半導體晶粒122的厚度大於約150μm，由於需要較厚的模塑層以密封較厚的半導體晶粒122，在後續的熱處理後將產生大量的翹曲，可能對封裝結構的品質和可靠度產生負面的影響。舉例而言，將可能因高度翹曲而導致冷結合問題的發生。
一些實施例中，絕緣膜132並未直接接觸介電層114。如第1F圖所示，絕緣膜132具有邊緣E1 ，且介電層114具有邊緣E2 。一些實施例中，邊緣E1 是絕緣膜132最靠近介電層114的部分。絕緣膜132的邊緣E1 與介電層114的邊緣E2 相隔一段距離D。距離D在約2 μm至約10 μm的範圍內。一些實施例中，距離D是絕緣膜132與介電層114之間的最短距離。
根據一些實施例，如第1G圖所示，形成覆蓋第1F圖所示之結構的保護層134。保護層134的材料和形成方法可相同或相似於保護層112的材料和形成方法。根據一些實施例，如第1G圖所示，絕緣膜132藉由一部分的保護層134與介電層114隔開。
根據一些實施例，如第1H圖所示，將保護層134薄化。結果，暴露出導電柱120。可使用平坦化製程以將保護層134薄化。平坦化製程可包含研磨製程、乾式拋光製程、化學機械拋光(CMP)製程、切割製程、蝕刻製程、一或多個其他合適的製程、或前述之組合。
一些實施例中，平坦化製程進一步移除一部分的導電柱120和一部分的半導體晶粒122。部分地移除半導體晶粒122的半導體基底124。結果，也暴露出半導體晶粒122中的導電部件126。導電部件126可作為基底穿孔(through substrate via，TSV)。
根據一些實施例，如第1I圖所示，在第1H圖所示的結構上形成重佈線結構136。重佈線結構136可包含多個介電層和多個形成在前述之介電層之間的導電部件。這些導電部件包含導孔和導線。一些前述之導電部件與導電柱120電性連接。一些前述之導電部件與半導體晶粒122的導電部件126電性連接。
重佈線結構136的介電層可由聚對苯撐苯並二噁唑(PBO)、聚亞醯胺(PI)、氧化矽、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。重佈線結構136的導電部件可由銅、鋁、鈷、鈦、金、鉑、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。重佈線結構136的形成方式可包含多個塗佈(或沉積)製程、多個微影製程及/或多個蝕刻製程。
隨後，根據一些實施例，如第1I圖所示，在重佈線結構136上形成導電凸塊138。導電凸塊138可包含焊料凸塊、金屬柱、一或多個其他合適的導電元件、或前述之組合。焊料凸塊可包含錫和其他金屬材料的合金。一些實施例中，焊料凸塊大抵上不含鉛。金屬柱可由銅、鈷、鈦、鋁、金、一或多個其他合適的材料、或前述之組合製成，或者包含上述材料。金屬柱可包含垂直的側壁。導電凸塊138的形成方式可包含電鍍製程、無電電鍍製程、物理氣相沉積(PVD)製程、一或多個其他合適的製程、或前述之組合。導電凸塊138的形成方式可更包含回流製程、蝕刻製程、或其他合適的製程。
根據一些實施例，如第1J圖所示，移除承載基底100。結果形成封裝結構。封裝結構可與其他結構整合。舉例而言，封裝結構可接合至印刷電路板(printed circuit board)、重佈線結構、中介層(interposer)基板、或其他封裝結構。一些其他的實施例中，在保護層112的背表面以及半導體晶粒104A和104B的背表面上形成另一個重佈線結構。
本揭露的實施例可具有多種變化及/或調整。第3圖是根據一些實施例，顯示封裝結構的剖面示意圖。一些實施例中，每一個連接件130皆包含金屬柱302和焊料元件304。金屬柱302的材料和形成方法可相同或相似於導電柱120的材料和形成方法。焊料元件304可包含錫和其他金屬材料的合金。一些實施例中，焊料元件304大抵上不含鉛。
如第2C-2F和1F圖所示的實施例，在半導體晶粒122接合至半導體晶粒104A和104B之前，部分地移除絕緣膜132。然而，本揭露的實施例不限於此。本揭露的實施例可具有多種變化及/或調整。第4A和4B圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。
根據一些實施例，如第4A圖所示，將與第2C圖所示的結構相同或相似的結構貼附至載具202上。絕緣膜132並未被部分地移除。因此，連接件130由絕緣膜132所覆蓋。
根據一些實施例，如第4B圖所示，切割第4A圖所示的結構以形成溝槽204。溝槽204將半導體基底124分隔成多個半導體晶粒122。
第5A和5B圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。根據一些實施例，如第5A圖所示，將半導體晶粒122中的其中一個抬起並放置於半導體晶粒104A和104B上。根據一些實施例，半導體晶粒122經由連接件130與半導體晶粒104A和104B接合。
一些實施例中，使用熱壓接合製程將半導體晶粒122與半導體晶粒104A和104B接合。如前所述，在熱壓接合製程期間，對半導體晶粒122施加壓縮壓力。一些實施例中，由於壓縮壓力的緣故，連接件130穿過絕緣膜132以直接接觸半導體晶粒104A和104B的導電部件110A和110B。一些實施例中，由於在熱壓接合製程期間施加的壓縮壓力，一部分的絕緣膜132受擠壓超出半導體晶粒122的邊緣。
根據一些實施例，如第5A圖所示，在將半導體晶粒122與半導體晶粒104A和104B接合後，形成絕緣膜132中一(或多個)擠壓部分502。擠壓部分502延伸超出半導體晶粒122之半導體基底124的邊緣。一些實施例中，如第5A圖所示，擠壓部分502具有相對於擠壓部分502的內部向外彎曲的側壁表面。
一些實施例中，如第5A圖所示，絕緣膜132具有多個擠壓部分502。一些實施例中，每一個擠壓部分502皆具有相對於擠壓部分502的內部向外彎曲的側壁表面。一些實施例中，擠壓部分502的頂面高於半導體晶粒122的鈍化層125與絕緣膜132之間的界面。一些實施例中，擠壓部分502與介電層114分隔一段距離。擠壓部分502並未直接接觸介電層114。
隨後，根據一些實施例，如第5B圖所示，進行相同或相似於第1G-1J圖所說明的製程以形成封裝結構。一些實施例中，絕緣膜132的擠壓部分502藉由一部分的保護層134與介電層114隔開。
本揭露的實施例可具有多種變化及/或調整。第6圖是根據一些實施例，顯示封裝結構的剖面示意圖。第6圖顯示的結構與第5B圖顯示的結構相似。一些實施例中，每一個連接件130皆包含金屬柱302和焊料元件304。金屬柱302的材料和形成方法可相同或相似於導電柱120的材料和形成方法。焊料元件304可包含錫和其他金屬材料的合金。一些實施例中，焊料元件304大抵上不含鉛。
本揭露的實施例可具有多種變化及/或調整。第7圖是根據一些實施例，顯示封裝結構的剖面示意圖。一些實施例中，絕緣膜132的擠壓部分502不只延伸超出半導體晶粒122的邊緣，還接觸介電層114。換言之，根據一些實施例，絕緣膜132的擠壓部分502與介電層114直接接觸。
一些實施例中，絕緣膜132的擠壓部分502直接接觸介電層114的邊緣。一些實施例中，如第7圖所示，即使擠壓部分502直接接觸介電層114的邊緣，保護層134仍具有一部分在擠壓部分502與介電層114之間。
如第7圖所示，絕緣膜132也包含擠壓部分502’。一些實施例中，擠壓部分502’延伸超出介電層114的邊緣。一些實施例中，擠壓部分502’部分地覆蓋介電層114的頂面。一些實施例中，擠壓部分502’直接接觸介電層114的頂面和邊緣。
本揭露的實施例形成具有堆疊的半導體晶粒的封裝結構。使用熱壓接合製程以將上半導體晶粒接合至下半導體晶粒之上。由於熱壓接合製程的特性，可在不產生冷結合問題的情況下，允許上半導體晶粒具有較小的厚度。因此，用於環繞上半導體晶粒之後續形成的保護層(例如模塑層)也可具有較小的厚度，進而顯著地降低封裝結構的翹曲度。在熱壓接合製程之前，在下半導體晶粒上的介電層內形成部分地暴露出下半導體晶粒的大開口。形成此大開口的微影製程係容易實施的。沒有殘餘物留在下半導體晶粒的導電部件上，故可避免顯影不足的問題。因此可改善上半導體晶粒和下半導體晶粒之間的電性連接，進而大幅提升封裝結構的品質和可靠度。
根據本發明的一些實施例，提供封裝結構的形成方法。方法包含在承載基底上設置第一半導體晶粒，以及形成第一保護層以環繞第一半導體晶粒。方法也包含在第一保護層和第一半導體晶粒上形成介電層。方法更包含將介電層圖案化以形成開口，此開口部分地暴露出第一半導體晶粒和第一保護層。此外，方法包含在形成前述的開口之後，將第二半導體晶粒接合至第一半導體晶粒。方法更包含形成第二保護層以環繞第二半導體晶粒。
在一實施例中，封裝結構的形成方法更包含在第一保護層形成之前，在承載基底上設置第三半導體晶粒，其中在將介電層圖案化之後，前述之開口部分地暴露出第三半導體晶粒，且第二半導體晶粒係同時與第一半導體晶粒和第三半導體晶粒接合。
在一實施例中，封裝結構的形成方法更包含在第二半導體晶粒上形成連接件，以及在第二半導體晶粒與第一半導體晶粒和第三半導體晶粒接合之前，在第二半導體晶粒上形成覆蓋連接件的絕緣膜。
在一實施例中，使用貼合製程在第二半導體晶粒上形成絕緣膜。
在一實施例中，封裝結構的形成方法更包含在第二半導體晶粒與第一半導體晶粒和第三半導體晶粒接合之前，部分地移除絕緣膜以暴露出連接件。
在一實施例中，在第二半導體晶粒與第一半導體晶粒接合之後，一部分的絕緣膜受擠壓超出第二半導體晶粒的邊緣。
在一實施例中，受擠壓超出第二半導體晶粒的邊緣的絕緣膜的上述部分藉由第二保護層與介電層隔開。
在一實施例中，受擠壓超出第二半導體晶粒的邊緣的絕緣膜的上述部分直接接觸介電層。
在一實施例中，封裝結構的形成方法更包含在第二半導體晶粒與第一半導體晶粒接合之前，在介電層上形成導電柱，以及將第二保護層、第二半導體晶粒和導電柱薄化以暴露出第二半導體晶粒中的導孔。
在一實施例中，使用熱壓接合製程將第二半導體晶粒與第一導體晶粒接合。
根據本發明的一些實施例，提供封裝結構的形成方法。方法包含形成第一保護層以環繞第一半導體晶粒和第二半導體晶粒。方法也包含形成介電層以覆蓋第一半導體晶粒、第二半導體晶粒和第一保護層。方法更包含在介電層內形成開口，此開口部分地暴露出第一半導體晶粒、第二半導體晶粒和第一保護層。此外，方法包含在形成前述的開口之後，設置第三半導體晶粒以部分地覆蓋第一半導體晶粒和第二半導體晶粒。第三半導體晶粒在第一半導體晶粒與第二半導體晶粒之間形成電性連接。方法更包含形成第二保護層以環繞第三半導體晶粒。
在一實施例中，封裝結構的形成方法更包含在第三半導體晶粒上形成連接件，以及在設置第三半導體晶粒以部分地覆蓋第一半導體晶粒和第二半導體晶粒之前，在第三半導體晶粒上貼合絕緣膜以覆蓋連接件。
在一實施例中，封裝結構的形成方法更包含在設置第三半導體晶粒以部分地覆蓋第一半導體晶粒和第二半導體晶粒之前，部分地移除絕緣膜以暴露出連接件。
在一實施例中，在設置第三半導體晶粒以部分地覆蓋第一半導體晶粒和第二半導體晶粒之後，一部分的絕緣膜受擠壓超出第三半導體晶粒的邊緣。
在一實施例中，封裝結構的形成方法更包含在第二保護層上形成重佈線結構，以及在重佈線結構上形成複數個導電凸塊。
根據本發明的一些實施例，提供封裝結構。封裝結構包含下半導體晶粒和環繞下半導體晶粒的第一保護層。封裝結構也包含部分地覆蓋第一保護層和下半導體晶粒的介電層。封裝結構更包含在下半導體晶粒和第一保護層上的上半導體晶粒。上半導體晶粒經由連接件與下半導體晶粒接合。此外，封裝結構包含環繞連接件的絕緣膜以及環繞上半導體晶粒的第二保護層。
在一實施例中，絕緣膜藉由一部分的第二保護層與介電層隔開。
在一實施例中，絕緣膜包含擠壓部分延伸超出上半導體晶粒的邊緣，前述的擠壓部分具有相對於擠壓部分的內部向外彎曲的側壁表面。
在一實施例中，前述的擠壓部分藉由一部分的第二保護層與介電層隔開。
在一實施例中，前述的擠壓部分直接接觸介電層。
以上概述數個實施例或範例之特徵，以便在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例或範例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並無悖離本發明實施例的精神與範圍，且他們能在不違背本發明實施例之精神和範圍之下，做各式各樣的改變、取代和替換。
100‧‧‧承載基底； 102‧‧‧黏著層； 104A、104B‧‧‧半導體晶粒； 106、124‧‧‧半導體基底； 107‧‧‧互連結構； 108、125‧‧‧鈍化層； 110A、110B、126‧‧‧導電部件； 112、134‧‧‧保護層； 114‧‧‧介電層； 116‧‧‧開口； 118、128‧‧‧導電元件； 120‧‧‧導電柱； 122‧‧‧半導體晶粒； 130‧‧‧連接件； 132‧‧‧絕緣膜； 202‧‧‧載具； 204‧‧‧溝槽； 136‧‧‧重佈線結構； 138‧‧‧導電凸塊； 302‧‧‧金屬柱； 304‧‧‧焊料元件； 502、502’‧‧‧擠壓部分； D‧‧‧距離； E1、E2‧‧‧邊緣。
藉由以下的詳述配合所附圖式，我們能更加理解本發明實施例的內容。需注意的是，根據產業上的標準做法，許多部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，這些部件的尺寸可能被任意地增加或減少。 第1A-1J圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。 第2A-2F圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。 第3圖是根據一些實施例，顯示封裝結構的剖面示意圖。 第4A和4B圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。 第5A和5B圖是根據一些實施例，顯示形成封裝結構之製程中各個階段的剖面示意圖。 第6圖是根據一些實施例，顯示封裝結構的剖面示意圖。 第7圖是根據一些實施例，顯示封裝結構的剖面示意圖。
106、124‧‧‧半導體基底
107‧‧‧互連結構
108、125‧‧‧鈍化層
110A、110B、126‧‧‧導電部件
112、134‧‧‧保護層
114‧‧‧介電層
118、128‧‧‧導電元件
120‧‧‧導電柱
122‧‧‧半導體晶粒
130‧‧‧連接件
132‧‧‧絕緣膜
136‧‧‧重佈線結構
138‧‧‧導電凸塊
E1、E2‧‧‧邊緣

Claims (1)

  1. 一種封裝結構的形成方法，包括： 在一承載基底上設置一第一半導體晶粒； 形成一第一保護層以環繞該第一半導體晶粒； 在該第一保護層和該第一半導體晶粒上形成一介電層； 將該介電層圖案化以形成一開口，該開口部分地暴露出該第一半導體晶粒和該第一保護層； 在形成該開口之後，將一第二半導體晶粒接合至該第一半導體晶粒；以及 形成一第二保護層以環繞該第二半導體晶粒。
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