CN110323143B - 包括多芯片模块的电子卡 - Google Patents

包括多芯片模块的电子卡 Download PDF

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CN110323143B
CN110323143B CN201910245042.4A CN201910245042A CN110323143B CN 110323143 B CN110323143 B CN 110323143B CN 201910245042 A CN201910245042 A CN 201910245042A CN 110323143 B CN110323143 B CN 110323143B
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package
wafer
circuit board
printed circuit
forming
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CN110323143A (zh
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余振华
李建勋
吴俊毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括将第一封装件接合到第二封装件以形成第三封装件，其中第一封装件是InFO封装件，InFO封装件包括：第一多个封装组件；第一密封材料，将第一多个封装组件密封在其中。第一多个封装组件包括器件管芯。该方法还包括将第三封装件的至少一部分放入PCB中的凹槽中，其中凹槽从PCB的顶面延伸到PCB的顶面和底面之间的中间层级。实施引线接合以将第三封装件电连接到PCB。本发明的实施例还涉及包括多芯片模块的电子卡。

Description

包括多芯片模块的电子卡
技术领域
本发明的实施例涉及包括多芯片模块的电子卡。
背景技术
当今的高性能计算(HPC)系统可以包括连接到主系统的多个独立的卡或板。独立的卡或板通过电缆线连接。通过锯切晶圆以形成器件管芯并且将器件管芯封装以形成封装件来形成卡或板。封装件安装在印刷电路板的表面上，然后将其组装以形成卡或板。将多个卡或板组装到系统的机架中，使得多个卡或板电互连。该系统具有有限的带宽和性能，因此其在高频应用中的使用受到限制。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：将第一封装件接合到第二封装件以形成第三封装件，其中，所述第一封装件是集成扇出(InFO)封装件，所述集成扇出封装件包括：第一多个封装组件，其中，所述第一多个封装组件包括器件管芯；和第一密封材料，将所述第一多个封装组件密封在其中；将所述第三封装件的至少一部分放入印刷电路板(PCB)中的第一凹槽中，其中，所述第一凹槽从所述印刷电路板的顶面延伸到所述印刷电路板的顶面和底面之间的中间层级；以及实施引线接合以将所述第三封装件电连接到所述印刷电路板。
本发明的又一实施例提供了一种形成封装件的方法，包括：重建第一晶圆，包括：将第一多个封装组件密封在第一密封材料中，其中，所述第一多个封装组件包括不同类型的器件管芯；形成与所述第一密封材料和所述第一多个封装组件重叠的第一多个再分布线(RDL)；和在所述第一多个再分布线上形成第一电连接件，并且所述第一电连接件电连接至所述第一多个再分布线；重建第二晶圆；将所述第一晶圆接合到所述第二晶圆以形成封装件；将所述封装件粘附到印刷电路板；以及将所述封装件上的第一导电部件电连接到所述印刷电路板上的第二导电部件。
本发明的又一实施例提供了一种封装件，包括：第一晶圆，所述第一晶圆包括：第一多个封装组件，所述第一多个封装组件包括第一器件管芯；第一密封剂，将所述第一多个封装组件密封在其中；和第一再分布线，互连所述第一多个封装组件；第二晶圆，接合到所述第一晶圆，其中，所述第二晶圆包括：第二多个封装组件，包括第二器件管芯；第二密封剂，将所述第二多个封装组件密封在其中；和第二再分布线，互连所述第二多个封装组件；印刷电路板，其中，所述第二晶圆粘附到所述印刷电路板；以及电连接件，将所述第二晶圆上的第一接合焊盘连接到所述印刷电路板上的接合焊盘。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图4、图5A、图5B、图6、图7A、图7B、图8和图9示出了根据一些实施例的在电子卡的形成中的中间阶段的顶视图和截面图。
图10至图13示出了根据一些实施例的在电子卡的形成中的中间阶段的顶视图和截面图。
图14至图18、图19A、图19B和图20示出了根据一些实施例的在电子卡的形成中的中间阶段的顶视图和截面图。
图21至图23示出了根据一些实施例的在电子卡的形成中的中间阶段的顶视图和截面图。
图24和图25示出了根据一些实施例的重建晶圆的截面图。
图26示出了根据一些实施例的用于形成电子卡的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各种实施例提供了封装件或电子卡及其形成方法。多个封装组件集成到重建晶圆中，这些晶圆以晶圆级接合在一起以形成例如封装件或电子卡。因此改善了所得封装件的集成度，并且可以将系统集成到接合的晶圆中。根据一些实施例，示出了形成封装件或电子卡的中间阶段。讨论了一些实施例的一些变型。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。
图1至图9示出了根据本发明的一些实施例的电子卡(或封装件)的形成中的中间阶段的截面图和顶视图。图1至图9中所示的步骤也在图26中所示的工艺流程中示意性地反映。
图1示出了封装组件100和封装组件200，其中实施对准以将封装组件100与封装组件200对准。根据本发明的一些实施例，封装组件100和200处于晶圆级，这意味着封装组件100和200形成为晶圆，并且不被锯成包含器件的单个(相同的)封装件。封装组件100和200的尺寸与半导体晶圆的尺寸相同或接近。例如，封装组件100和200可以是4英寸晶圆、6英寸晶圆、12英寸晶圆或更大。根据一些实施例的封装组件100和200被称为多芯片模块或重建晶圆。封装组件100和200也称为晶圆上系统封装件，因为它们包括用于形成系统的不同类型的器件管芯和封装件。例如，单独或组合的封装组件100和200可以形成人工智能系统，人工智能系统可以包括用于并行计算的多个核心芯片以及用于存储的多个不同类型的存储器。
封装组件100包括位于其中的封装组件102，封装组件102由密封材料(密封剂)104密封。互连结构106形成在封装组件102和密封材料104上，并且用于电连接至封装组件102中的集成电路器件。互连结构106还互连封装组件102。在图1中，示意性地示出互连结构106，并且可以参考图24找到互连结构106中的细节。封装组件100还包括用于接合的电连接件108。根据本发明的一些实施例，电连接件108包括焊料区、金属柱、金属焊盘等。
封装组件200包括其中的封装组件202，封装组件202由密封材料(密封剂)204密封。互连结构206形成在封装组件202和密封材料204上，并且用于电连接到封装组件202中的集成电路器件。互连结构206还互连封装组件202。在图1中，示意性地示出互连结构206，并且互连结构206中的细节类似于图24中所示的细节。因此，后续段落中讨论的互连结构206的细节也适用于互连结构206。封装组件200还包括用于接合的电连接件208。根据本发明的一些实施例，电连接件208包括焊料区、金属柱、金属焊盘等。
根据本发明的一些实施例，封装组件102和202可以是任何器件管芯(诸如逻辑管芯和存储器管芯)、片上系统管芯、封装件、高带宽存储器(HBM)封装件、数字管芯、模拟管芯、表面贴装无源器件等。一些封装组件102可以具有彼此不同的结构，而一些其他封装组件102可以彼此相同。一些封装组件202也可以具有彼此不同的结构和功能，而一些其他封装组件202可以彼此相同。封装组件102和202可以包括如前所述的多种类型的管芯，它们通过互连结构106和206互连(在它们接合在一起之后)以形成集成系统。封装组件102的尺寸、厚度和集成度可以彼此不同。封装组件202的尺寸、厚度和集成度可以彼此不同，并且可以与封装组件102的尺寸、厚度和集成度不同。
图24说明封装组件100的一部分的截面图。应了解，根据本发明的一些实施例，封装组件200也可以具有与封装组件100类似的结构。因此，封装组件100的描述也可以应用于封装组件200。封装组件200的细节因此未单独示出和讨论，并且可以参考封装组件100的细节。根据本发明的一些实施例，在所示的示例中，封装组件102包括从晶圆锯切的分立器件管芯。封装组件102还可以包括高带宽存储器(HBM)堆叠件。密封材料104可以包括模塑料、模塑底部填充物、底部填充物等，其可以包括混合在基底材料中的颗粒。填料颗粒可以是诸如SiO2、Al2O3、硅石等的介电材料的颗粒，并且可以具有球形形状。而且，球形填料颗粒可以具有相同或不同的直径。基底材料可以包括聚合物、树脂、环氧树脂等。
互连结构106包括多个介电层109，其包括介电层109A和109B。介电层109B可以由聚合物形成，例如聚酰亚胺、聚苯并且恶唑(PBO)、味之素增层膜(ABF)、预浸料(其中具有填料和/或纤维)、阻焊剂等。介电层109A可以由诸如PBO、聚酰亚胺等的有机材料和/或无机介电材料形成。互连结构106还包括在介电层109中形成的再分布线(RDL)110(包括110A和110B)，以电连接到封装组件102中的器件。RDL 110可以由铜、铝、镍、钛、钽、氮化钛、氮化钽或它们的多层形成。RDL 110可以包括或不包括胶合层(也称为阻挡层)，其可以由钛、钽、氮化钛、氮化钽等形成。胶合层可以比RDL的上覆部分更薄。例如，胶合层的厚度可以是相应RDL的厚度的约5％至约10％。
根据本发明的一些实施例，形成在介电层109B中的RDL 110B比形成在介电层109A中的RDL 110A更厚且更宽。根据本发明的一些实施例，RDL 110A用于局部连接，并且可以用于相邻封装组件102之间的信号路由。RDL 110B可以用作全局线，例如电源线、地线等，或者用作连接彼此不相近的封装组件102的信号线。电连接件108形成在封装组件100的表面上。根据本发明的一些实施例，电连接件108包括焊料区。根据本发明的其他实施例，电连接件108包括金属凸块、金属焊盘、或金属凸块以及位于金属凸块的顶部上的焊料区。
如下简要讨论封装组件100的形成。相应的工艺示出为图26中所示的工艺流程中的工艺402。可以使用与形成封装组件100类似的工艺来形成封装组件200，并且相应的工艺示出为图26所示的工艺流程中的工艺403。根据本发明的一些实施例，封装组件100的形成包括在载体上涂覆释放膜(例如光-热转换(LTHC)涂层)，通过管芯附接膜(粘合膜)将封装组件102放置在载体上，将封装组件102密封在密封材料104中，并且进行平坦化工艺，例如化学机械抛光(CMP)工艺或机械研磨工艺，以去除密封材料的多余部分，使得暴露封装组件102的电连接件(例如金属柱)。
然后，在封装组件102和密封材料104上形成互连结构106。根据本发明的一些实施例，互连结构106的形成包括逐层形成介电层和相应的RDL。例如，形成介电层和相应的RDL层包括沉积介电层，图案化介电层以形成开口，通过开口暴露下面的导电部件，沉积金属晶种层，形成图案化的掩模，在图案化的掩模中镀RDL，去除图案化的掩模，并且蚀刻先前由图案化的掩模覆盖的金属晶种层的部分。电连接件108通过镀和/或通过焊球放置形成。在形成互连结构106之后，可以例如通过将激光束投射在释放膜上以分解释放膜来拆卸载体。由此形成封装组件100。
图2示出了封装组件100中的封装组件102和密封材料104的顶视图。根据本发明的一些实施例，一些封装组件102的尺寸可以彼此不同，而一些封装组件102可以具有相同的尺寸。而且，一些封装组件102的形状可以彼此不同，而一些封装组件102可以具有相同的形状。
图3示出了根据一些实施例的封装组件100的修整。在图26所示的工艺流程中，相应的工艺示出为工艺404。在修整步骤中，封装组件100的边缘部分(其中边缘部分中不包括有源器件和RDL)被去除以减小封装组件100的尺寸。根据封装组件100的形状和厚度，可以通过切割刀片、激光束、刨机等实施修整。在修整步骤之后，所有封装组件102和RDL仍然保留在同一晶圆中，而不会分成不同的封装件。根据封装组件100小于封装组件200的一些实施例，可以实施或不实施修整。
图4示出了封装组件200中的封装组件202和密封材料204的顶视图。根据本发明的一些实施例，封装组件202的尺寸可以彼此不同，而一些封装组件202可以具有相同的尺寸。而且，一些封装组件202的形状可以彼此不同，而一些其他封装组件202可以具有相同的形状。接合焊盘214形成在封装组件200的外围区和表面上。一些接合焊盘214电连接到封装组件202。一些其他接合焊盘214没有电连接到封装组件202，并且一旦封装组件100接合到封装组件200，该其他接合焊盘214将电连接到封装组件102(图9)。一些接合焊盘214(例如电源和接地焊盘)也可以连接到封装组件202，并且一旦封装组件100接合到封装组件200，该接合焊盘214还将电连接到封装组件102。
图5A和图5B分别示出了封装组件100与封装组件200的接合中的截面图和顶视图。相应的工艺示出为图26中所示的工艺流程中的工艺406。可以通过焊料接合、金属-金属接合、混合接合等来实现接合。根据本发明的一些实施例，使用激光烧蚀来实施接合。例如，产生的激光束的尺寸远大于典型激光束的尺寸。激光束发生器(未示出)可以配置成将小激光束放大到期望的更大尺寸。封装组件100被分成多个子区，并且激光烧蚀包括多个激光照射，每个激光照射投射在多个子区中的一个上。当激光投射在封装组件100的其中一个子区上时，直接位于相应子区下面的焊料区被回流。因此，通过逐个子区地接合封装组件100和200，整个封装组件100接合到封装组件200，从而形成封装件20。连接电连接件108和208以形成电连接件22，电连接件22可以是回流的焊料区、接合在一起的焊料区和金属柱、或接合在一起的金属凸块。在接合之后，可以将底部填充物24分配到封装组件100和200之间的间隙中，然后固化。
图5B示出了如图5A中所示的封装件20的顶视图。如图5A和图5B所示，可以形成在封装组件200的边缘区上的接合焊盘214未被封装组件100覆盖。当最初形成的重建晶圆100和200具有相同的尺寸时，封装组件100的修整去除了覆盖接合焊盘214的封装组件100的部分。应当理解，尽管封装组件102示出为与封装组件200中的相应封装组件202重叠，但是封装组件102的布局和尺寸可以与封装组件202的布局和尺寸完全不同，并且与封装组件202的布局和尺寸无关。一些封装组件102可以与多个封装组件202重叠并且接合至多个封装组件202，反之亦然。
图6示出了封装组件300的截面图。根据本发明的一些实施例，封装组件300是印刷电路板(PCB)，因此在下文中称为PCB 300，但是封装组件300可以是其他类型。根据本发明的一些实施例，PCB 300包括从PCB300的顶面延伸到PCB 300的中间层级的晶圆尺寸凹槽302。根据本发明的其他实施例，没有形成凹槽302。接合焊盘314形成在PCB 300的顶面上，并且可以布置成与环绕凹槽302的环对准。电连接件316形成为与PCB 300的侧面(例如图7B中的右侧)对准。电连接件316电连接到接合焊盘314，并且可以延伸到PCB 300的边缘。
根据本发明的一些实施例，金属板306粘附在PCB 300的顶面上。金属板306可以放置在凹槽302(当形成时)中。相应的工艺在图26所示的工艺流程中示出为工艺408。金属板306可以由铜、铝、不锈钢等形成，并且用于重新分配和传导热量。金属板306可以通过热界面材料(TIM)304粘附到PCB 300。TIM 308可以形成在金属板306上。TIM 304和308可以具有高于约1W/k*m的热导率值，高于约1W/k*m，高于约5W/k*m，高于约20W/k*m，高于约50W/k*m或更高。粘合剂310分配在凹槽302中，并且可以沿着凹槽302的侧壁分配为环。
根据本发明的一些实施例，PCB 300包括示意性地示出的导电迹线320(包括320A和320B)，并且可以包括导线和通孔。导电迹线320可以由铜、铝、钛、钨等形成。导电迹线320可以包括多个层，这些层组合地穿透PCB 300。导电迹线320可以包括用于路由信号、电源、电接地等的有源迹线320A，有源迹线320A可以电连接到接合焊盘314。导电迹线320还可以包括迹线320B，迹线320B不具有电功能，并且与最终封装件中的封装组件100和200中的所有器件和电路电断开。根据本发明的一些实施例，迹线320B可以是电浮置的，并且称为伪迹线。导电迹线320B用于将封装组件100和200中产生的热传导到PCB 300的底侧。PCB 300可以是单侧的，导电迹线形成在顶侧，但不形成在底侧。PCB 300也可以形成为双侧的，如图6所示，在顶侧和底侧都形成导电迹线。
图7A和图7B分别示出了封装件20与PCB 300的粘附中的截面图和顶视图。例如，通过TIM 308和粘合剂310实现粘附。相应的工艺示出为图26所示的工艺流程中的工艺410。根据本发明的一些实施例，封装件20放置在凹槽302中(图6)。封装组件200的顶面可以与PCB300的顶面齐平，高于或低于PCB 300的顶面。如图7B所示，封装件20的尺寸和形状适合于凹槽302的相应的尺寸和形状，使得封装件20固定在PCB 300上。
图8示出了封装件20与PCB 300的电连接。相应的工艺示出为图26中所示的工艺流程中的工艺412。根据本发明的一些实施例，实施引线接合以在接合焊盘214和314上形成线接合26，使得接合焊盘214电连接到接合焊盘314。因此，封装件20电连接到电连接件316。
参考图9，将TIM 28涂覆或放置在封装件20的顶部上，并且将机械支撑件30和冷却系统32安装在PCB 300上。相应的工艺分别示出为图26中所示的工艺流程中的工艺414和416。例如，机械支撑件30可以是金属框架。冷却系统32可以包括具有鳍的金属板、其中具有用于传导冷却剂(例如水、油或冷空气)的导管的金属板等。由此形成封装件34。封装件34也可以是电子卡。可以通过将具有电连接件316的端部插入机架的槽中来使用封装件34，其中电连接件316接触机架的电连接件。或者，可以将销(未示出)安装为封装件34的连接件。相应的工艺示出为图26所示的工艺流程中的工艺418。
图10至图13示出了根据本发明的一些实施例的在封装件的形成中的中间阶段的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法基本上与由图1至图9所示的实施例中的相同的附图标记表示的相同的组件相同。因此，可以在图1至图9所示的实施例的讨论中找到关于图10至图13(以及图14至图23)中所示的组件的形成工艺和材料的细节。
图10示出了根据本发明的一些实施例的PCB 300。如图10所示的PCB300类似于图6中所示的PCB 300，除了凹槽330形成为从PCB 300的底面延伸到凹槽302延伸到的中间层级。凹槽330连接凹槽302以形成穿透PCB 300的连续凹槽。当从顶部或底部观察时，凹槽330小于凹槽302。凹槽330的底视图形状可以是圆形、矩形或具有其他形状。粘合剂310分配在凹槽302中。根据本发明的一些实施例，图10中的PCB 300包括有源导电迹线320，并且可以包括或不包括伪导电迹线。
参考图11，封装件20例如通过粘合剂310粘附到PCB 300。已经参考图1至图5A/图5B和图24讨论了封装件20的形成，并且在此不再重复细节。当形成凹槽302(图10)时，封装件20的至少底部延伸到凹槽302中。例如，封装组件200可以完全或部分地位于凹槽302中。接下来，对接合焊盘214和314实施引线接合，使得接合焊盘214和314通过接合线26电连接。封装件20的底部暴露于凹槽330。TIM 28分配在封装件20的顶部。
图12示出了机械支撑件30和冷却系统32的安装。冷却系统32与TIM28接触，TIM 28被分配或放置在封装件20的顶部。接下来，如图13所示，冷却系统36例如通过TIM 38附接到封装件20。可以分配额外的粘合剂以将冷却系统36的侧壁连接到面向凹槽330的PCB 300的侧壁。冷却系统36还可以包括鳍，或者可以包括其中的用于传导冷却剂的导管。根据本发明的一些实施例，支撑系统40附接到冷却系统36的底部。当所得到的封装件34在其使用期间水平放置时使用支撑系统40，因为封装件34具有大尺寸，因此需要支撑以避免由于其重量引起的问题。如果在垂直方向上使用封装件34，则不安装支撑系统40。
图14至图20示出了根据本发明的一些实施例的封装件34的形成。这些实施例类似于图1至图9中所示的实施例，除了封装组件200不包括器件管芯(以及包括器件管芯的封装组件)之外。图14示出了封装组件100与封装组件200的对准。图15示出了封装组件100的顶视图，其例如使用与图3中所示的基本相同的方法和材料形成。图24示出了根据本发明的一些实施例的封装组件100的一些细节，其中示出了RDL 110和相应的介电层109。
图16示出了根据本发明的一些实施例的封装组件200的顶视图，其示出了形成在封装组件200的外围区中的接合焊盘214。由外围区围绕的内部区包括其中的RDL。图25示出了封装组件200的一些部分的一些细节。根据本发明的一些实施例，封装组件200包括RDL110(包括110A和110B)以及在空白衬底220上形成的相应的介电层109(包括109A和109B)。可以在空白衬底220上形成介电层222，其中RDL 110形成在介电层222上。RDL 110和介电层109的细节可以与参考图24所讨论的相同，因此这里不再重复。
根据一些实施例，在空白衬底220上没有形成诸如晶体管和二极管的有源器件。此外，根据一些实施例，封装组件200可以在介电层109中没有或可以包括诸如电阻器、电容器、电感器等的无源器件。空白衬底220可以由均质材料形成，其可以是例如硅。或者，空白衬底220可以是介电衬底，其可以由例如氧化硅形成。封装组件200用于电气布线。
接下来，将封装组件100接合到封装组件200，得到如图17所示的封装件20。将底部填充物24分配到封装组件100和200之间的间隙中。封装件20的顶视图也在图18中示出。
参考图18，封装件20粘附到PCB 300，PCB 300可以与图6中所示的基本相同。图19A示出了图18中所示结构的截面图。TIM 304和308以及金属板306可以放置在PCB 300中的凹槽302(图6)中，类似于图6中所示。封装件20通过粘合剂310(图6)和TIM 308粘附到PCB300。
接下来，形成引线接合26以将封装件20电连接到PCB 300，也如图19A中的顶视图所示。图20示出了机械支撑件30和冷却系统32的安装。结构、材料和安装方法可以与参考图9所讨论的基本相同。因此形成封装件(电子卡)34。在随后的步骤中，如果需要，可以安装销(未示出)以连接到电连接件316，或者可以将封装件34插入机架的槽中，其中电连接件316用作电连接。
图21至图23示出了根据本发明的一些实施例的封装件34的形成。这些实施例类似于图1至9中所示的实施例，除了封装组件200具有图25中所示的结构并且其中没有器件管芯和有源晶体管，并且在PCB 300中形成开口330(图22)。参考图21，封装组件100例如使用与图3中所示的基本相同的方法和材料形成。封装组件100与封装组件200对准，参考图16和图25描述和说明封装组件200。如图22所示，将封装组件100接合到封装组件200上，形成封装件20。
进一步参考图22，提供了封装组件300。如已经讨论的，封装组件300的结构类似于图10中所示的结构。因此，这里不再重复细节。封装件20例如通过粘合剂310粘附到PCB300。接下来，对接合焊盘214和314实施引线接合工艺，使得接合焊盘214和314通过接合线26电连接。封装件20的底部通过PCB 300中的凹槽330暴露。然后，机械支撑件30和冷却系统32通过TIM 28安装在PCB 300上。冷却系统32与TIM 28接触，TIM28分配在封装件20的顶部。接下来，冷却系统36例如通过TIM 38附接到封装件20。可以分配附加的粘合剂(未示出)以将冷却系统36的侧壁连接到PCB 300的侧壁，PCB 300的该侧壁面向凹槽330。冷却系统36可以包括鳍，或者可以包括用于传导冷却剂的导管。根据本发明的一些实施例，支撑系统40附接到冷却系统36的底部。根据本发明的其他实施例，如果垂直地安装所得到的封装件34，则不安装支撑系统40。图23示出了在集成了如图22所示的组件之后的封装件34。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件。还可以包括其他部件和工艺。例如，可以包括测试结构以帮助3D封装或3DIC器件的验证测试。例如，测试结构可以包括在再分布层中或在衬底上形成的测试焊盘，测试焊盘允许使用探针和/或探针卡等测试3D封装或3DIC。可以对中间结构以及最终结构实施验证测试。另外，本文所公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用，以增加产量并且降低成本。
本发明的实施例具有一些有利特征。通过将多个封装组件集成到重建晶圆中，可以提高集成度，并且可以通过将重建晶圆接合在一起来集成系统。多个封装组件的连接线很短，因此相应的系统具有改进的性能。这允许该系统用于一些性能要求苛刻的应用，例如人工智能应用，这些应用需要多种不同类型的芯片用于并行计算。凹陷PCB的使用提高了封装件的稳定性并且减小了所得封装件的厚度。此外，PCB中的背侧开口允许从两侧散热。
根据本发明的一些实施例，一种方法包括将第一封装件接合到第二封装件以形成第三封装件，其中第一封装件是InFO封装件，InFO封装件包括：第一多个封装组件，其中第一多个封装组件包括器件管芯；第一密封材料，将第一多个封装组件密封在其中；将第三封装件的至少一部分放入PCB中的第一凹槽中，其中第一凹槽从PCB的顶面延伸到PCB的顶面和底面之间的中间层级；以及实施引线接合以将第三封装件电连接到PCB。在一个实施例中，该方法还包括形成第二封装件，包括：在空白衬底上形成多条再分布线，其中多条再分布线位于空白硅衬底和第一封装件之间。在一个实施例中，该方法还包括形成第二封装件，包括：将第二多个封装组件密封在第二密封材料中；以及在第二多个封装组件上形成多条再分布线，多条再分布线电连接到第二多个封装组件，其中第二多个封装组件包括额外的器件管芯。在一个实施例中，第二封装件是未锯切的晶圆。在一个实施例中，形成第一封装件包括：将第一多个封装组件密封在第一密封材料中；和修整第一密封材料的边缘部分。在一个实施例中，PCB还包括从PCB的底面延伸到中间层级的第二凹槽，并且该方法还包括：将冷却系统附接到第三封装件，其中冷却系统延伸到第二凹槽中。在一个实施例中，该方法还包括通过TIM将金属板粘附到PCB，其中PCB包括穿透PCB的伪金属部件，TIM与伪金属部件重叠。
根据本发明的一些实施例，一种方法包括重建第一晶圆，包括：将第一多个封装组件密封在第一密封材料中，其中，第一多个封装组件包括不同类型的器件管芯；形成与第一密封材料和第一多个封装组件重叠的第一多个RDL；在第一多个RDL上形成第一电连接件，并且第一电连接件电连接至第一多个RDL；重建第二晶圆；将第一晶圆接合到第二晶圆以形成封装件；将封装件粘附到印刷电路板；以及将封装件上的第一导电部件电连接到印刷电路板上的第二导电部件。在一个实施例中，重建第二晶圆包括：将第二多个封装组件密封在第二密封材料中；并且形成连接到第二多个封装组件的第二多个RDL。在一个实施例中，该方法还包括在将第一晶圆接合到第二晶圆之前修整第一晶圆的边缘部分。在一个实施例中，在修整之后，由第一密封材料密封的所有器件管芯保留在第一晶圆中，并且当附接到印刷电路板时，所有器件管芯都在封装件中。在一个实施例中，重建第二晶圆包括：在空白硅衬底上形成第二多个RDL，其中第二多个RDL位于空白硅衬底和第一晶圆之间。在一个实施例中，重建第二晶圆包括：将第二多个封装组件密封在第二密封材料中；在第二多个封装组件上形成第二多个RDL，并且第二多个RDL电连接到第二多个封装组件。在一个实施例中，该方法还包括在第一晶圆和第二晶圆之间增加分配底部填充物。在一个实施例中，该方法还包括从封装件的底部附接冷却系统，其中冷却系统的一部分延伸到印刷电路板中。
根据本发明的一些实施例，封装件包括第一晶圆，该第一晶圆包括第一多个封装组件，第一多个封装组件包括第一器件管芯；第一密封剂，将第一多个封装组件密封在其中；和第一再分布线，互连第一多个封装组件；第二晶圆，接合到第一晶圆，其中第二晶圆包括：第二多个封装组件，包括第二器件管芯；第二密封剂，将第二多个封装组件密封在其中；和第二再分布线，互连第二多个封装组件；印刷电路板，其中第二晶圆粘附到印刷电路板；电连接件，将第二晶圆上的第一接合焊盘连接到印刷电路板上的接合焊盘。在一个实施例中，第二晶圆延伸到印刷电路板中。在一个实施例中，基本上整个第二晶圆位于印刷电路板内。在一个实施例中，封装件还包括位于印刷电路板的一侧上的电连接件，其中电连接件配置为插入插槽中。在一个实施例中，封装件还包括延伸到印刷电路板中的冷却系统，其中冷却系统附接到第二晶圆的背面。封装件包括第一晶圆，该第一晶圆包括第一多个封装组件，第一多个封装组件包括第一器件管芯；第一密封剂，将第一多个封装组件密封在其中；和第一再分布线，互连第一多个封装组件；第二晶圆，接合到第一晶圆，其中第二晶圆包括：第二多个封装组件，第二多个封装组件包括第二器件管芯；第二密封剂，将第二多个封装组件密封在其中；和第二再分布线，互连第二多个封装组件；印刷电路板，其中第二晶圆粘附到印刷电路板；电连接件，将第二晶圆上的第一接合焊盘连接到印刷电路板上的接合焊盘。在一个实施例中，第二晶圆延伸到印刷电路板中。在一个实施例中，基本上整个第二晶圆位于印刷电路板内。在一个实施例中，封装件还包括位于印刷电路板的一侧上的电连接件，其中电连接件配置为插入插槽中。在一个实施例中，封装件还包括延伸到印刷电路板中的冷却系统，其中冷却系统附接到第二晶圆的背面。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法，包括：
形成第一封装件，包括：
将第一多个封装组件密封在第一密封材料中，其中，所述第一多个封装组件包括器件管芯；
在所述第一多个封装组件和所述第一密封材料上形成第一互连结构并且所述第一互连结构与所述第一多个封装组件电连接；和
修整所述第一密封材料的边缘部分，其中，所述第一封装件是包括集成扇出(InFO)封装件的重建晶圆；
形成第二封装件，包括形成第二互连结构，其中，所述第二封装件是重建晶圆；
将所述第一封装件接合到所述第二封装件以形成第三封装件，其中，所述第一封装件接合到所述第二封装件包括将所述第一互连结构和所述第二互连结构相对设置并且将所述第一互连结构和所述第二互连结构电连接；
将所述第三封装件的至少一部分放入印刷电路板(PCB)中的第一凹槽中，其中，在放入时，所述第一封装件是未锯切的重建晶圆，所述第二封装件粘附在所述印刷电路板上，所述第一凹槽从所述印刷电路板的顶面延伸到所述印刷电路板的顶面和底面之间的中间层级；以及
实施引线接合以将所述第三封装件电连接到所述印刷电路板，其中，所述第二互连结构中的接合焊盘电连接至所述印刷电路板中的接合焊盘。
2.根据权利要求1所述的方法，其中，形成所述第二封装件，包括：在衬底上形成所述第二互连结构，所述第二互连结构包括多条再分布线，其中，所述多条再分布线位于所述衬底和所述第一封装件之间。
3.根据权利要求1所述的方法，其中，形成所述第二封装件，包括：将第二多个封装组件密封在第二密封材料中；以及
在所述第二多个封装组件上形成所述第二互连结构，所述第二互连结构包括多条再分布线，所述多条再分布线电连接到所述第二多个封装组件，其中，所述第二多个封装组件包括额外的器件管芯。
4.根据权利要求1所述的方法，其中，所述第二封装件是未锯切的晶圆。
5.根据权利要求1所述的方法，还包括在接合所述第一封装件和所述第二封装件之后在所述第一封装件和所述第二封装件之间分配底部填充物。
6.根据权利要求1所述的方法，其中，所述印刷电路板还包括从所述印刷电路板的底面延伸到所述中间层级的第二凹槽，并且所述方法还包括：
将冷却系统附接到所述第三封装件，其中，所述冷却系统延伸到所述第二凹槽中。
7.根据权利要求1所述的方法，还包括通过热界面材料(TIM)将金属板粘附到所述印刷电路板，其中，所述印刷电路板包括穿透所述印刷电路板的伪金属部件，所述热界面材料与所述伪金属部件重叠。
8.一种形成封装件的方法，包括：
重建第一晶圆，包括：
将第一多个封装组件密封在第一密封材料中，其中，所述第一多个封装组件包括不同类型的器件管芯；
形成与所述第一密封材料和所述第一多个封装组件重叠的第一多个再分布线(RDL)，其中，所述第一多个再分布线和所述器件管芯电连接；和
在所述第一多个再分布线上形成第一电连接件，并且所述第一电连接件电连接至所述第一多个再分布线；
重建第二晶圆，包括形成第二多个再分布线和接合焊盘；
修整所述第一晶圆的边缘部分，其中，在所述修整之后，所有的所述器件管芯和所有的所述第一多个再分布线都保留在所述第一晶圆；
在所述修整之后，将所述第一晶圆接合到所述第二晶圆以形成封装件，其中，将所述第一电连接件与所述第二多个再分布线相对设置并且将所述第一电连接件与所述第二多个再分布线电连接；
将所述第二晶圆粘附到印刷电路板；以及
将所述第二晶圆上的所述接合焊盘电连接到所述印刷电路板上的接合焊盘。
9.根据权利要求8所述的方法，其中，重建所述第二晶圆包括：
将第二多个封装组件密封在第二密封材料中；和
形成连接到所述第二多个封装组件的第二多个再分布线。
10.根据权利要求8所述的方法，其中，所述印刷电路板包括凹槽，所述第二晶圆粘附到所述凹槽的表面上。
11.根据权利要求10所述的方法，其中，所述封装件的顶面高于、等于或低 于所述印刷电路板的顶面。
12.根据权利要求8所述的方法，其中，重建所述第二晶圆包括：
在衬底上形成第二多个再分布线，其中，所述第二多个再分布线位于所述衬底和所述第一晶圆之间。
13.根据权利要求8所述的方法，其中，重建所述第二晶圆包括：
将第二多个封装组件密封在第二密封材料中；和
在所述第二多个封装组件上形成第二多个再分布线，并且所述第二多个再分布线电连接到所述第二多个封装组件。
14.根据权利要求8所述的方法，还包括在所述第一晶圆和所述第二晶圆之间分配底部填充物。
15.根据权利要求8所述的方法，还包括从所述封装件的底部附接冷却系统，其中，所述冷却系统的一部分延伸到所述印刷电路板中。
16.一种封装件，包括：
第一晶圆，其中，所述第一晶圆是重组晶圆，并且包括：
第一多个封装组件，所述第一多个封装组件包括第一器件管芯；
第一密封剂，将所述第一多个封装组件密封在其中；和
第一再分布线，互连所述第一多个封装组件；
第二晶圆，接合到所述第一晶圆，其中，所述第二晶圆是重组晶圆，并且包括：
第二多个封装组件，包括第二器件管芯；
第二密封剂，将所述第二多个封装组件密封在其中；和
第二再分布线，互连所述第二多个封装组件，其中，所述第一再分布线和所述第二再分布线相对设置并且所述第一再分布线和所述第二再分布线电连接；
印刷电路板，其中，所述第二晶圆粘附到所述印刷电路板；以及
电连接件，将所述第二晶圆上的第一接合焊盘连接到所述印刷电路板上的接合焊盘。
17.根据权利要求16所述的封装件，其中，所述第二晶圆延伸到所述印刷电路板中。
18.根据权利要求16所述的封装件，其中，整个第二晶圆位于所述印刷电路板内。
19.根据权利要求16所述的封装件，还包括位于所述印刷电路板的一侧上的电连接件，其中，所述电连接件配置为插入插槽中。
20.根据权利要求16所述的封装件，还包括延伸到所述印刷电路板中的冷却系统，其中，所述冷却系统附接到所述第二晶圆的背面。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11217563B2 (en) 2019-10-24 2022-01-04 Apple Inc. Fully interconnected heterogeneous multi-layer reconstructed silicon device
US11201127B2 (en) * 2020-03-09 2021-12-14 Qualcomm Incorporated Device comprising contact to contact coupling of packages
US11594498B2 (en) * 2020-04-27 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method
US20240145432A1 (en) * 2021-03-08 2024-05-02 Tesla, Inc. Cooled system-on-wafer with means for reducing the effects of electrostatic discharge and/or electromagnetic interference
US11935761B2 (en) 2021-08-27 2024-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming thereof
CN114759012B (zh) * 2022-06-14 2022-08-26 之江实验室 基于tsv工艺晶上系统与pcb板互连结构及制造方法
US11705437B1 (en) * 2023-01-19 2023-07-18 Zhejiang Lab Interconnection structure of system on wafer and PCB base on TSV process and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101409241A (zh) * 2007-10-09 2009-04-15 英飞凌科技股份有限公司 半导体芯片封装、半导体芯片组件和制造器件的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3292798B2 (ja) 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
JP2004296613A (ja) 2003-03-26 2004-10-21 Renesas Technology Corp 半導体装置
US7763963B2 (en) * 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
CN102169875B (zh) 2010-02-26 2013-04-17 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8535989B2 (en) * 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
EP2535926A3 (en) * 2011-06-17 2015-08-05 BIOTRONIK SE & Co. KG Semiconductor package
KR101849223B1 (ko) 2012-01-17 2018-04-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9721920B2 (en) 2012-10-19 2017-08-01 Infineon Technologies Ag Embedded chip packages and methods for manufacturing an embedded chip package
KR102134133B1 (ko) * 2013-09-23 2020-07-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9527723B2 (en) * 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
US9881908B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
US9773757B2 (en) * 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US10062648B2 (en) * 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101409241A (zh) * 2007-10-09 2009-04-15 英飞凌科技股份有限公司 半导体芯片封装、半导体芯片组件和制造器件的方法

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