TWI736866B - 封裝體及其形成方法 - Google Patents

封裝體及其形成方法 Download PDF

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TWI736866B
TWI736866B TW108110867A TW108110867A TWI736866B TW I736866 B TWI736866 B TW I736866B TW 108110867 A TW108110867 A TW 108110867A TW 108110867 A TW108110867 A TW 108110867A TW I736866 B TWI736866 B TW I736866B
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package
printed circuit
circuit board
wafer
components
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TW108110867A
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TW201942986A (zh
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余振華
李建勳
吳俊毅
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台灣積體電路製造股份有限公司
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Abstract

一種形成封裝體的方法包括：將第一封裝體接合至第二 封裝體以形成第三封裝體。第一封裝體是積體扇出型(InFO)封裝體，積體扇出型封裝體包括多個封裝組件及包封材料，包封材料將所述多個封裝組件包封於其中。所述多個封裝組件包括多個裝置晶粒。所述方法更包括將第三封裝體的至少一部分放置於印刷電路板(PCB)中的凹槽中。凹槽自印刷電路板的頂表面延伸至位於印刷電路板的頂表面與底表面之間的中間水平高度。執行打線接合以將第三封裝體電性連接至印刷電路板。

Description

封裝體及其形成方法
本發明實施例是有關於封裝體及其形成方法。
當今的高效能計算(High Performance Computing，HPC)系統可包括連接至主系統的多個獨立的卡或板。所述獨立的卡或板是經由纜線打線(cable wire)連接。所述卡或板是藉由鋸切晶圓以形成多個裝置晶粒並對所述多個裝置晶粒進行封裝以形成封裝體而形成。將封裝體安裝於印刷電路板的表面上，然後對所述印刷電路板進行裝配以形成卡或板。將多個卡或板裝配成系統構架，以使所述多個卡或板電性內連。此系統所具有的頻寬及效能是有限的，且因此其在高頻率應用中的使用受到限制。
本發明實施例的一種形成封裝體的方法，所述形成封裝體的方法包括：將第一封裝體接合至第二封裝體以形成第三封裝體，其中所述第一封裝體是積體扇出型封裝體，所述積體扇出型 封裝體包括多個第一封裝組件以及第一包封材料，多個第一封裝組件包括多個裝置晶粒，第一包封材料將所述多個第一封裝組件包封於其中；將所述第三封裝體的至少一部分放置於印刷電路板中的第一凹槽中，其中所述第一凹槽自所述印刷電路板的頂表面延伸至位於所述印刷電路板的所述頂表面與底表面之間的中間水平高度；以及執行打線接合以將所述第三封裝體電性連接至所述印刷電路板。
本發明實施例的一種形成封裝體的方法，所述形成封裝體的方法包括重構第一晶圓，其中所述重構第一晶圓包括將多個第一封裝組件包封於第一包封材料中，其中所述多個第一封裝組件包括不同類型的多個裝置晶粒，形成與所述第一包封材料及所述多個第一封裝組件交疊的多個第一重佈線，以及在所述多個第一重佈線之上形成電性連接至所述多個第一重佈線的多個第一電性連接件；重構第二晶圓；將所述第一晶圓接合至所述第二晶圓以形成封裝體；將所述封裝體黏合至印刷電路板；以及將所述封裝體上的多個第一傳導特徵電性連接至所述印刷電路板上的多個第二傳導特徵。
本發明實施例的一種封裝體，所述封裝體包括第一晶圓、第二晶圓、印刷電路板以及多個電性連接部。所述第一晶圓包括多個第一封裝組件、第一包封體以及多個第一重佈線。所述多個第一封裝組件包括多個第一裝置晶粒。所述第一包封體將所述多個第一封裝組件包封於其中。所述多個第一重佈線對所述多 個第一封裝組件進行內連。所述第二晶圓接合至所述第一晶圓，其中所述第二晶圓包括多個第二封裝組件、第二包封體以及多個第二重佈線。所述多個第二封裝組件包括多個第二裝置晶粒。所述第二包封體將所述多個第二封裝組件包封於其中。所述多個第二重佈線對所述多個第二封裝組件進行內連。所述第二晶圓黏合至所述印刷電路板。所述多個電性連接部將所述第二晶圓上的多個第一接合墊連接至所述印刷電路板上的多個接合墊。
20、34:封裝體
22、108、208、316:電性連接件
24:底部填充膠
26:鍵合線
28、38、304、308:熱界面材料
30:機械支撐體
32、36:冷卻系統
40:支撐系統
100、102、200、202:封裝組件
104、204:包封材料
106、206:內連線結構
109A、109B:介電層
110A、110B:重佈線
214、314:接合墊
220:空白基底
300:印刷電路板
302、330:凹槽
306:金屬板
310:黏著劑
320A:主動跡線
320A、320B:傳導跡線
402、403、404、406、408、410、412、414、416、418:製程
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖4、圖5A、圖5B、圖6、圖7A、圖7B、圖8及圖9說明形成根據一些實施例的電子卡的中間階段的俯視圖及剖視圖。
圖10至圖13說明形成根據一些實施例的電子卡的中間階段的俯視圖及剖視圖。
圖14至圖18、圖19A、圖19B及圖20說明形成根據一些實施例的電子卡的中間階段的俯視圖及剖視圖。
圖21至圖23說明形成根據一些實施例的電子卡的中間階段的俯視圖及剖視圖。
圖24及圖25說明根據一些實施例的經重構晶圓的剖視圖。
圖26說明用於形成根據一些實施例的電子卡的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同的實施例或實例。下文闡述組件及排列的具體實例以簡化本發明。當然，該些僅為實例且不旨在進行限制。舉例而言，在以下說明中，第一特徵形成於第二特徵「之方」或第二特徵「上」可包括其中第一特徵與第二特徵形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有額外特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但本質上並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明起見，本文中可使用例如「在...之下」、「在...下方」、「下部」、「上覆於」、「上部」等空間相對術語來闡述圖中所說明的一個元件或特徵與另一元件或特徵的關係。除了圖中所繪示的定向之外，所述空間相對術語旨在涵蓋裝置在使用或操作中的不同定向。設備可被另外定向(旋轉90度或處於其他定向)，且同樣地對本文中所使用的空間相對描述符相應地加以解 釋。
根據各種實施例提供封裝體或電子卡以及形成封裝體及電子卡的方法。將多個封裝組件整合成經重構晶圓，將所述經重構晶圓在晶圓級下接合在一起以形成例如封裝體或電子卡。所得封裝體的整合程度(integration level)會因此得以提高，且系統可被整合成接合型晶圓。根據一些實施例說明形成封裝體或電子卡的中間階段。對一些實施例的一些變化形式加以論述。在通篇的各種視圖中及說明性實施例中，相似參考編號用於表示相似的元件。
圖1至圖9說明形成根據本發明的一些實施例的電子卡(或封裝體)的中間階段的剖視圖及俯視圖。圖1至圖9中所示的步驟亦示意性地反映於圖26中所示的製程流程中。
圖1說明封裝組件100及封裝組件200，其中執行對準以將封裝組件100對準至封裝組件200。根據本發明的一些實施例，封裝組件100及封裝組件200處於晶圓級下，此意味著封裝組件100及封裝組件200形成為晶圓，而非被鋸切成包括裝置的多個個別封裝體(該些個別封裝體是相同的)。封裝組件100及封裝組件200的尺寸相同於或接近於半導體晶圓的尺寸。舉例而言，封裝組件100及封裝組件200可以是4英寸晶圓、6英寸晶圓、12英寸晶圓或大於12英寸的晶圓。根據一些實施例的封裝組件100及封裝組件200被稱為多晶片模組(multi-chip module)或經重構晶圓(re-constructed wafer)。封裝組件100及封裝組件200亦可被稱 為系統晶圓封裝體(system-on-wafer package)，此乃因該些系統晶圓封裝體包括用於形成系統的不同類型的多個裝置晶粒及多個封裝體。舉例而言，封裝組件100及封裝組件200可個別地或以組合形式形成人工智慧系統，所述人工智慧系統可包括用於進行並行計算的多個核心晶片以及用於儲存的多個不同類型的記憶體。
封裝組件100中包括多個封裝組件102，封裝組件102由包封材料(包封體)104包封。內連線結構106形成於封裝組件102及包封材料104上，且用於電性連接至封裝組件102中的積體電路裝置。內連線結構106亦對封裝組件102進行內連。圖1中示意性地繪示內連線結構106，且可參考圖24瞭解內連線結構106的細節。封裝組件100更包括用於進行接合的多個電性連接件108。根據本發明的一些實施例，電性連接件108包括焊料區、金屬柱、金屬接墊等。
封裝組件200中包括多個封裝組件202，封裝組件202由包封材料(包封體)204包封。內連線結構206形成於封裝組件202及包封材料204上，且用於電性連接至封裝組件202中的積體電路裝置。內連線結構206亦對封裝組件202進行內連。圖1中示意性地繪示內連線結構206，且內連線結構206的細節類似於圖24中所示。因此，在後續段落中對內連線結構106的細節的論述亦適用於內連線結構206。封裝組件200更包括用於進行接合的多個電性連接件208。根據本發明的一些實施例，電性連接件208 包括焊料區、金屬柱、金屬接墊等。
根據本發明的一些實施例，封裝組件102及封裝組件202可以是裝置晶粒(諸如，邏輯晶粒及記憶體晶粒)、系統晶片晶粒、封裝體、高頻寬記憶體(High Bandwidth Memory，HBM)封裝體、數位晶粒、類比晶粒、表面安裝型被動裝置等中的任一者。多個封裝組件102中的一些封裝組件可具有彼此不同的結構，而一些其他封裝組件102可彼此相同。多個封裝組件202中的一些封裝組件亦可具有彼此不同的結構及功能，而一些其他封裝組件202可彼此相同。封裝組件102及封裝組件202可包括如上所述的多種類型的晶粒，該些多種類型的晶粒是經由內連線結構106及內連線結構206達成內連(在該些晶粒被接合在一起之後)以形成積體系統。封裝組件102的尺寸、厚度及整合程度可彼此不同。封裝組件202的尺寸、厚度及整合程度可彼此不同，且可不同於封裝組件102的尺寸、厚度及整合程度。
圖24說明封裝組件100的一部分的剖視圖。應瞭解，根據本發明的一些實施例，封裝組件200亦可具有與封裝組件100類似的結構。因此，對封裝組件100的說明亦可適用於封裝組件200。因此不針對封裝組件200的細節進行單獨繪示及論述，且可參考封裝組件100的細節來瞭解封裝組件200的細節。根據本發明的一些實施例，在所說明的實例中，封裝組件102包括離散裝置晶粒，離散裝置晶粒是由晶圓鋸切而來。封裝組件102可更包括高頻寬記憶體(HBM)堆疊。包封材料104可包括模塑化合物、 模塑底部填充膠、底部填充膠等，上述包封材料可包括混合於基部材料中的粒子。填充膠粒子可以是諸如SiO2、Al2O3、二氧化矽等介電材料的粒子，且可具有球形形狀。此外，球形填充膠粒子可具有相同或不同的直徑。基部材料可包括聚合物、樹脂、環氧樹脂等。
內連線結構106包括多個介電層109，介電層109包括介電層109A及介電層109B。介電層109B可由聚合物形成，諸如聚醯亞胺(polyimide)、聚苯並噁唑(polybenzoxazole，PBO)、味之素堆積膜(Ajinomoto Build-up Film，ABF)、預浸體(prepreg，其中具有填充膠及/或纖維)、阻焊劑(solder resist)等。介電層109A可由諸如聚苯並噁唑、聚醯亞胺等有機材料及/或無機介電材料形成。內連線結構106更包括形成於介電層109中以電性連接至封裝組件102中的裝置的多個重佈線(Redistribution Line，RDL)110(包括多個重佈線110A及多個重佈線110B)。重佈線110可由銅、鋁、鎳、鈦、鉭、氮化鈦、氮化鉭或上述材料的多個層形成。重佈線110可包括或可不包括膠層(其亦可被稱為障壁層)，所述膠層可由鈦、鉭、氮化鈦、氮化鉭等形成。膠層可較重佈線的上覆部分薄。舉例而言，膠層的厚度可為對應重佈線的厚度的約5%至約10%。
根據本發明的一些實施例，形成於介電層109B中的重佈線110B較形成於介電層109A中的重佈線110A厚且寬。根據本發明的一些實施例，重佈線110A用於局部連接，且可用於鄰近封 裝組件102之間的訊號路由(routing)。重佈線110B可用作諸如電源線、接地線等全局線(global line)，或者用作連接彼此不接近的封裝組件102的訊號線。電性連接件108形成於封裝組件100的表面上。根據本發明的一些實施例，電性連接件108包括焊料區。根據本發明的其他實施例，電性連接件108包括金屬凸塊、金屬接墊或金屬凸塊，以及位於金屬凸塊的頂部上的焊料區。
如下簡要論述封裝組件100的形成。將相應製程說明為圖26中所示的製程流程中的製程402。可使用與封裝組件100的形成類似的製程來形成封裝組件200，且將相應製程說明為圖26中所示的製程流程中的製程403。根據本發明的一些實施例，形成封裝組件100包括：將釋放膜(諸如光熱轉換(Light-To-Heat-Conversion，LTHC)塗層)塗佈於載體上；藉由晶粒貼合膜(黏著膜)將封裝組件102放置於載體上；將封裝組件102包封於包封材料104中；及執行平坦化製程(諸如，化學機械拋光(Chemical Mechanical Polish，CMP)製程或機械研磨製程)以移除包封材料的多餘部分，以暴露出封裝組件102的電性連接件(諸如，金屬柱)。
然後，將內連線結構106形成於封裝組件102及包封材料104上。根據本發明的一些實施例，形成內連線結構106包括逐層地形成介電層及對應重佈線。舉例而言，形成介電層及對應重佈線層包括：沉積介電層；將介電層圖案化以形成多個開口，下方多個傳導特徵經由所述多個開口暴露出；沉積金屬晶種層； 形成圖案化罩幕；在圖案化罩幕中鍍覆多個重佈線；移除圖案化罩幕；及蝕刻金屬晶種層的先前被圖案化罩幕覆蓋的部分。經由鍍覆及/或經由焊料植球來形成多個電性連接件108。在形成內連線結構106之後，可例如藉由將雷射束投射於釋放膜上以分解所述釋放膜來拆卸載體。因此形成封裝組件100。
圖2說明封裝組件100中的多個封裝組件102及包封材料104的俯視圖。根據本發明的一些實施例，多個封裝組件102中的一些封裝組件的尺寸可彼此不同，而多個封裝組件102中的一些封裝組件可具有相同的尺寸。此外，多個封裝組件102中的一些封裝組件的形狀可彼此不同，而多個封裝組件102中的一些封裝組件可具有相同的形狀。
圖3說明對根據一些實施例的封裝組件100的修整。將相應製程說明為圖26中所示的製程流程中的製程404。在修整步驟中，將封裝組件100的邊緣部分移除以減小封裝組件100的尺寸，所述邊緣部分中不包括主動裝置及重佈線。修整可根據封裝組件100的形狀及厚度而藉由切刀、雷射束、刳刨器(router)等來執行。在修整步驟之後，所有的封裝組件102及重佈線保留於同一晶圓中，而未被分離成不同封裝體。根據封裝組件100小於封裝組件200的一些實施例，可執行或可不執行修整。
圖4說明封裝組件200中的多個封裝組件202及包封材料204的俯視圖。根據本發明的一些實施例，多個封裝組件202的尺寸可彼此不同，而多個封裝組件202中的一些封裝組件可具 有相同的尺寸。此外，多個封裝組件202中的一些封裝組件的形狀可彼此不同，而一些其他封裝組件202可具有相同的形狀。多個接合墊214形成於封裝組件200的周邊區中且形成於封裝組件200的表面上。多個接合墊214中的一些接合墊電性連接至封裝組件202。一些其他接合墊214並不電性連接至封裝組件202且在封裝組件100接合至封裝組件200時將會電性連接至封裝組件102(圖9)。一些接合墊214(諸如，電源接墊及接地接墊)亦可連接至封裝組件202，且在封裝組件100接合至封裝組件200時亦將電性連接至封裝組件102。
圖5A及圖5B分別說明將封裝組件100接合至封裝組件200時的剖視圖及俯視圖。將相應製程說明為圖26中所示的製程流程中的製程406。所述接合可經由焊料接合、金屬對金屬直接接合、混合接合等來實現。根據本發明的一些實施例，所述接合是使用雷射燒蝕(laser ablation)來執行。舉例而言，將雷射束產生成具有較典型雷射束的大小更大的尺寸。雷射束產生器(未繪示)可被配置成將小雷射束放大成所需要的更大尺寸。封裝組件100被劃分成多個子區，且雷射燒蝕包括多次雷射射擊，每次雷射射擊投射於所述多個子區中的一者上。當將雷射投射於封裝組件100的子區中的一者上時，直接在相應子區下方的焊料區發生回流。因此，藉由逐個子區地接合封裝組件100與封裝組件200，將整個封裝組件100接合至封裝組件200，從而形成封裝體20。將電性連接件108與電性連接件208結合以形成電性連接件22，電性連 接件22可以是回流的焊料區、接合在一起的焊料區與金屬柱或接合在一起的金屬凸塊。在接合之後，可將底部填充膠24填入至封裝組件100與封裝組件200之間的間隙中，且然後進行固化。
圖5B說明圖5A中所示封裝體20的俯視圖。如圖5A及圖5B中所示，可被形成於封裝組件200的邊緣區上的接合墊214未被封裝組件100覆蓋。當最初形成的經重構晶圓100及經重構晶圓200具有相同的尺寸時，修整封裝組件100會移除封裝組件100的覆蓋接合墊214的部分。應瞭解，儘管封裝組件102被繪示為與封裝組件200中的對應封裝組件202交疊，但封裝組件102的佈局及尺寸可與封裝組件202的佈局及尺寸完全不同且不相關。封裝組件102中的一些封裝組件可與多個封裝組件202交疊並接合，且反之亦然。
圖6說明封裝組件300的剖視圖。根據本發明的一些實施例，封裝組件300是印刷電路板(Printed Circuit Board，PCB)，且因此在下文被稱為印刷電路板300，而封裝組件300可以是其他類型。根據本發明的一些實施例，印刷電路板300包括具有晶圓尺寸的凹槽302，凹槽302自印刷電路板300的頂表面延伸至印刷電路板300的中間水平高度。根據本發明的其他實施例，不形成凹槽302。接合墊314形成於印刷電路板300的頂表面上，且可被排列以對準成環，所述環圍繞凹槽302。多個電性連接件316形成為對準至印刷電路板300的一側(諸如，在圖7B中為右側)。電性連接件316電性連接至接合墊314，且可延伸至印刷電路板300 的邊緣。
根據本發明的一些實施例，將金屬板306黏合於印刷電路板300的頂表面上。金屬板306可放置於凹槽302(在形成時)中。將相應製程說明為圖26中所示的製程流程中的製程408。金屬板306可由銅、鋁、不銹鋼等形成且用於進行重佈及傳導熱量。可藉由熱界面材料(Thermal Interface Material，TIM)304將金屬板306黏合至印刷電路板300。熱界面材料308可形成於金屬板306之上。熱界面材料304及熱界面材料308可具有高於約1瓦/開爾文*米(W/k*m)、高於約5瓦/開爾文*米、高於約20瓦/開爾文*米、高於約50瓦/開爾文*米或更高的熱傳導率值。黏著劑310被填入於凹槽302中，且可被點膠成沿著凹槽302的側壁的環。
根據本發明的一些實施例，印刷電路板300包括多個傳導跡線320(包括多個主動跡線320A及多個傳導跡線320B)，傳導跡線320是示意性地繪示的且可包括多個傳導線及多個導通孔。傳導跡線320可由銅、鋁、鈦、鎢等形成。傳導跡線320可包括多個層，所述多個層以組合形式穿透過印刷電路板300。傳導跡線320可包括用於路由訊號、電源、接地電位等的主動跡線320A，主動跡線320A可電性連接至接合墊314。傳導跡線320亦可包括傳導跡線320B，傳導跡線320B不具有電性功能，且在最終封裝體中自封裝組件100及封裝組件200中的所有裝置及電路電性斷開連接。根據本發明的一些實施例，傳導跡線320B可電性浮動，且被稱為虛設跡線。傳導跡線320B用於將封裝組件100及 封裝組件200中所產生的熱量傳導至印刷電路板300的底側。印刷電路板300可以是單側式的，其中傳導跡線形成於頂側上，而不形成於底側上。印刷電路板300亦可形成為雙側式，如圖6中所示，傳導跡線形成於頂側及底側二者上。
圖7A及圖7B分別說明在將封裝體20黏合至印刷電路板300時的剖視圖及俯視圖。所述黏合是例如藉由熱界面材料308及黏著劑310來實現。將相應製程說明為圖26中所示的製程流程中的製程410。根據本發明的一些實施例，將封裝體20放置於凹槽302中(圖6)。封裝組件200的頂表面可與印刷電路板300的頂表面齊平、可高於或可低於印刷電路板300的頂表面。如圖7B中所示，封裝體20的尺寸及形狀適合於凹槽302的相應尺寸及形狀，以將封裝體20固定於印刷電路板300上。
圖8說明封裝體20至印刷電路板300的電性連接。將相應製程說明為圖26中所示的製程流程中的製程412。根據本發明的一些實施例，執行打線接合(wiring bonding)以在接合墊214及接合墊314上形成鍵合線(wiring bonds)26，以使接合墊214電性連接至接合墊314。因此，封裝體20電性連接至電性連接件316。
參考圖9，將熱界面材料28塗佈或放置於封裝體20的頂部上，且將機械支撐體30及冷卻系統32安裝於印刷電路板300上。將相應製程分別說明為圖26中所示的製程流程中的製程414及製程416。舉例而言，機械支撐體30可以是金屬框架。冷卻系 統32可包括具有散熱片(fin)的金屬板、於內部具有用於傳導冷卻劑(諸如水、油或冷空氣)的導管的金屬板等。因而形成封裝體34。封裝體34亦可以是電子卡。可藉由將具有電性連接件316的一端插入至構架(rack)的槽中來使用封裝體34，其中連接件316與構架的電性連接件接觸。或者，可將多個引腳(未繪示)安裝為封裝體34的連接件。將相應製程說明為圖26中所示的製程流程中的製程418。
圖10至圖13說明形成根據本發明的一些實施例的封裝體的中間階段的剖視圖。除非另有規定，否則該些實施例中的組件的材料及形成方法與相似組件本質上相同，所述相似組件在圖1至圖9中所示的實施例中是由相似參考編號標示。因此，可在對圖1至圖9中所示實施例的論述中瞭解到與圖10至圖13(以及圖14至圖23)中所示組件的形成製程及材料有關的細節。
圖10說明根據本發明的一些實施例的印刷電路板300。圖10中所示印刷電路板300類似於圖6中所示印刷電路板300，但在圖10中所示印刷電路板300中，凹槽330形成為自印刷電路板300的底表面延伸至凹槽302所延伸到的中間水平高度。凹槽330與凹槽302結合以形成穿透過印刷電路板300的連續凹槽。當自頂部或底部觀察時，凹槽330小於凹槽302。凹槽330的仰視形狀可為圓形的、矩形的或具有其他形狀。將黏著劑310填入於凹槽302中。根據本發明的一些實施例，圖10中所示印刷電路板300包括主動的傳導跡線320，且可包括或可不包括虛設的傳導跡線。
參考圖11，例如藉由黏著劑310將封裝體20黏合至印刷電路板300。封裝體20的形成已參考圖1至圖5A/圖5B及圖24被論述，且細節在本文中不予贅述。當形成凹槽302(圖10)時，封裝體20的至少一底部部分延伸至凹槽302中。舉例而言，封裝組件200可完全地或部分地位於凹槽302中。接下來，對接合墊214與接合墊314執行打線接合以使接合墊214與接合墊314經由鍵合線26電性連接。封裝體20的底部露出至凹槽330。將熱界面材料28點膠於封裝體20的頂部上。
圖12說明機械支撐體30及冷卻系統32的安裝。冷卻系統32與被點膠或放置於封裝體20的頂部上的熱界面材料28接觸。接下來，如圖13中所示，例如藉由熱界面材料38將冷卻系統36貼合至封裝體20。可點膠額外黏著劑以將冷卻系統36的側壁結合至印刷電路板300的面向凹槽330的側壁。冷卻系統36亦可包括散熱片，或者冷卻系統36中可包括用於傳導冷卻劑的導管。根據本發明的一些實施例，將支撐系統40貼合至冷卻系統36的底部。當在所得封裝體34的使用期間水平地放置所得封裝體34時，使用支撐系統40，此乃因封裝體34具有大的尺寸且因此需要支撐以避免因其重量而導致的問題。若在封裝體34處於垂直方向上時使用封裝體34，則不安裝支撐系統40。
圖14至圖20說明根據本發明的一些實施例的封裝體34的形成。該些實施例類似於圖1至圖9中所示的實施例，但封裝組件200不包括裝置晶粒(及包括裝置晶粒的封裝組件)。圖14 說明封裝組件100至封裝組件200的對準。圖15說明封裝組件100的俯視圖，封裝組件100例如是使用與圖3中所示本質上相同的方法及材料形成。圖24說明根據本發明的一些實施例的封裝組件100的一些細節，其中對重佈線110及對應的介電層109加以說明。
圖16說明根據本發明的一些實施例的封裝組件200的俯視圖，圖16繪示形成於封裝組件200的周邊區中的接合墊214。被周邊區圍繞的內區中包括多個重佈線。圖25說明封裝組件200的一些部分的一些細節。根據本發明的一些實施例，封裝組件200包括形成於空白基底220之上的多個重佈線110(包括多個重佈線110A及多個重佈線110B)及對應的多個介電層109(包括多個介電層109A及多個介電層109B)。介電層109可形成於空白基底220之上，重佈線110形成於介電層109之上。重佈線110及介電層109的細節可與參考圖24所論述相同，且因此本文中不予贅述。
根據一些實施例，諸如電晶體及二極體等主動裝置不形成於空白基底220上。此外，根據一些實施例的封裝組件200在介電層109中可不包括或可包括被動裝置，諸如電阻器、電容器、電感器等。空白基底220可由均質材料形成，舉例而言所述均質材料可以是矽。或者，空白基底220可以是介電基底，所述介電基底可例如由氧化矽形成。封裝組件200用於電性佈線。
接下來，將封裝組件100接合至封裝組件200，從而形成圖17中所示的封裝體20。將底部填充膠24填入至封裝組件100與封裝組件200之間的間隙中。圖18中亦繪示封裝體20的俯視 圖。
參考圖18，將封裝體20黏合至印刷電路板300，印刷電路板300可與圖6中所示本質上相同。圖19A說明圖18中所示結構的剖視圖。可將熱界面材料304及熱界面材料308以及金屬板306放置於印刷電路板300中的凹槽302(圖6)中，此與圖6中所示類似。藉由黏著劑310(圖6)及熱界面材料308將封裝體20黏合至印刷電路板300。
接下來，形成鍵合線26以將封裝體20電性連接至印刷電路板300，亦如圖19B中的俯視圖中所示。圖20說明機械支撐體30及冷卻系統32的安裝。結構、材料及安裝方法可與參考圖9所論述本質上相同。因此形成封裝體(電子卡)34。在後續步驟中，可視需要安裝引腳(未繪示)以連接至電性連接件316，或者可將封裝體34插入至構架的槽中，其中電性連接件316用作電性連接。
圖21至圖23說明根據本發明的一些實施例的封裝體34的形成。該些實施例類似於圖1至圖9中所示的實施例，但封裝組件200具有圖25中所示的結構且其中不包括裝置晶粒及主動電晶體，且開口330(圖23)形成於印刷電路板300中。參考圖21，舉例而言，使用與圖3中所示本質上相同的方法及材料來形成封裝組件100。將封裝組件100對準至封裝組件200，參考圖16及圖25對此加以闡述及說明。將封裝組件100接合至封裝組件200，從而形成圖22中所示的封裝體20。
更參考圖22，提供封裝組件300。封裝組件300的結構類似於圖10中所示結構，如已論述。因此，在細節在本文中不予贅述。例如藉由黏著劑310將封裝體20黏合至印刷電路板300。接下來，對接合墊214及接合墊314執行打線接合製程，以使接合墊214與接合墊314經由鍵合線26電性連接。經由印刷電路板300中的凹槽330露出封裝體20的底部。然後，例如藉由熱界面材料28將機械支撐體30及冷卻系統32安裝於印刷電路板300上。冷卻系統32與被點膠於封裝體20的頂部上的熱界面材料28接觸。接下來，例如藉由熱界面材料28將冷卻系統36貼合至封裝體20。可點膠額外黏著劑(未繪示)來將冷卻系統36的側壁結合至印刷電路板300的面向凹槽330的側壁。冷卻系統36可包括散熱片，或者冷卻系統36中可包括用於傳導冷卻劑的導管。根據本發明的一些實施例，將支撐系統40貼合至冷卻系統36的底部。根據本發明的其他實施例，若不垂直地安裝所得封裝體34，則不安裝支撐系統40。圖23說明在圖22中所示組件已被整合之後的封裝體34。
在上文所說明的實施例中，根據本發明的一些實施例論述了一些製程及特徵。亦可包括其他特徵及製程。舉例而言，可包括測試結構以輔助對三維(three-dimension，3D)封裝體或三維積體電路(three-dimension integrated circuit，3DIC)裝置進行驗證測試。舉例而言，測試結構可包括形成於允許三維封裝體或三維積體電路被測試的重佈線層中或基底上的測試接墊、探針及/或 探針卡的使用等。可對中間結構及最終結構執行驗證測試。另外，本文中所揭示的結構及方法可與併入對已知良好晶粒進行中間驗證的測試方法結合使用來提高良率且降低成本。
本發明實施例具有一些有利的特徵。藉由將多個封裝組件整合成經重構晶圓，可提高整合程度，且可藉由將多個經重構晶圓接合在一起來整合為系統。所述多個封裝組件之間為短的連接線，且因此相應系統具有改善的效能。此允許系統可被用於需要多種不同類型的晶片以進行並行計算的一些高效能要求的應用中，諸如人工智慧應用。使用帶凹槽的印刷電路板會提高封裝體的穩定性且減小所得封裝體的厚度。此外，印刷電路板中的背面開口允許散熱自兩側進行。
根據本發明的一些實施例，一種形成封裝體的方法包括：將第一封裝體接合至第二封裝體以形成第三封裝體，其中所述第一封裝體是積體扇出型封裝體，所述積體扇出型封裝體包括多個第一封裝組件以及第一包封材料，其中所述多個第一封裝組件包括多個裝置晶粒，且所述第一包封材料將所述多個第一封裝組件包封於其中；將所述第三封裝體的至少一部分放置於印刷電路板中的第一凹槽中，其中所述第一凹槽自所述印刷電路板的頂表面延伸至位於所述印刷電路板的所述頂表面與底表面之間的中間水平高度；以及執行打線接合以將所述第三封裝體電性連接至所述印刷電路板。在一個實施例中，所述方法更包括形成所述第二封裝體，所述形成所述第二封裝體包括：在空白基底之上形成 多個重佈線，其中所述多個重佈線位於空白基底與所述第一封裝體之間。在一個實施例中，所述方法更包括形成所述第二封裝體，所述形成所述第二封裝體包括：將多個第二封裝組件包封於第二包封材料中；以及在所述多個第二封裝組件之上形成電性連接至所述多個第二封裝組件的多個重佈線，其中所述多個第二封裝組件包括額外的多個裝置晶粒。在一個實施例中，所述第二封裝體是未經鋸切的晶圓。在一個實施例中，所述形成所述第一封裝體包括：將所述多個第一封裝組件包封於所述第一包封材料中；以及修整所述第一包封材料的邊緣部分。在一個實施例中，所述印刷電路板更包括第二凹槽，所述第二凹槽自所述印刷電路板的所述底表面延伸至所述中間水平高度，且所述方法更包括：將冷卻系統貼合至所述第三封裝體，其中所述冷卻系統延伸至所述第二凹槽中。在一個實施例中，所述方法更包括：藉由熱界面材料將金屬板黏合至所述印刷電路板，其中所述印刷電路板包括穿透過所述印刷電路板的虛設金屬特徵，所述熱界面材料與所述虛設金屬特徵交疊。
根據本發明的一些實施例，一種形成封裝體的方法包括：重構第一晶圓，所述重構第一晶圓包括將多個第一封裝組件包封於第一包封材料中，其中所述多個第一封裝組件包括不同類型的多個裝置晶粒，形成與所述第一包封材料及所述多個第一封裝組件交疊的多個第一重佈線，以及在所述多個第一重佈線之上形成電性連接至所述多個第一重佈線的多個第一電性連接件；重 構第二晶圓；將所述第一晶圓接合至所述第二晶圓以形成封裝體；將所述封裝體貼合至印刷電路板；以及將所述封裝體上的多個第一傳導特徵電性連接至所述印刷電路板上的多個第二傳導特徵。在一個實施例中，所述重構所述第二晶圓包括：將多個第二封裝組件包封於第二包封材料中；以及形成連接至所述多個第二封裝組件的多個第二重佈線。在一個實施例中，所述方法更包括：在將所述第一晶圓接合至所述第二晶圓之前，修整所述第一晶圓的邊緣部分。在一個實施例中，在所述修整之後，被所述第一包封材料包封的所有裝置晶粒保留於所述第一晶圓中，且當所述封裝體貼合至所述印刷電路板時，所述所有裝置晶粒位於所述封裝體中。在一個實施例中，所述重構所述第二晶圓包括：在空白矽基底之上形成多個第二重佈線，其中所述多個第二重佈線位於所述空白矽基底與所述第一晶圓之間。在一個實施例中，所述重構所述第二晶圓包括：將多個第二封裝組件包封於第二包封材料中；以及在所述多個第二封裝組件之上形成電性連接至所述多個第二封裝組件的多個第二重佈線。在一個實施例中，所述方法更包括：在所述第一晶圓與所述第二晶圓之間填入底部填充膠。在一個實施例中，所述方法更包括：自所述封裝體的底部貼合冷卻系統，其中所述冷卻系統的一部分延伸至所述印刷電路板中。
根據本發明的一些實施例，一種封裝體包括第一晶圓、第二晶圓、印刷電路板以及多個電性連接部。所述第一晶圓包括：多個第一封裝組件，包括多個第一裝置晶粒；第一包封體，將所 述多個第一封裝組件包封於其中；以及多個第一重佈線，對所述多個第一封裝組件進行內連。所述第二晶圓接合至所述第一晶圓，其中所述第二晶圓包括：多個第二封裝組件，包括多個第二裝置晶粒；第二包封體，將所述多個第二封裝組件包封於所述第二包封體中；以及多個第二重佈線，對所述多個第二封裝組件進行內連。所述第二晶圓黏合至所述印刷電路板。所述多個電性連接部將所述第二晶圓上的多個第一接合墊連接至所述印刷電路板上的多個接合墊。在一個實施例中，所述第二晶圓延伸至所述印刷電路板中。在一個實施例中，整個所述第二晶圓實質上位於所述印刷電路板內。在一個實施例中，所述封裝體更包括位於所述印刷電路板的一側上的多個電性連接件，其中所述多個電性連接件被配置成插入至插孔(socket)中。在一個實施例中，所述封裝體更包括延伸至所述印刷電路板中的冷卻系統，其中所述冷卻系統貼合至所述第二晶圓的背面。
上述內容概述數個實施例的特徵，以使熟習此項技術者可更好地理解本發明的態樣。熟習此項技術者應瞭解，其可容易地使用本發明作為設計或修改其他製程及結構的基礎以達到與本文中所引入的實施例相同的目的及/或達成相同的優勢。熟習此項技術者亦應意識到，該些等效構造並不背離本發明的精神及範疇，且其可在不背離本發明的精神及範疇的情況下在本文中做出各種改變、替代及變更。
20、34:封裝體
22、316:電性連接件
24:底部填充膠
26:鍵合線
28、38:熱界面材料
30:機械支撐體
32、36:冷卻系統
40:支撐系統
100、102、200、202:封裝組件
104、204:包封材料
106、206:內連線結構
214、314:接合墊
300:印刷電路板
310:黏著劑
320:傳導跡線
330:凹槽

Claims (9)

  1. 一種形成封裝體的方法，包括：將第一封裝體接合至第二封裝體以形成第三封裝體，其中所述第一封裝體是積體扇出型封裝體，所述積體扇出型封裝體包括：多個第一封裝組件，其中所述多個第一封裝組件包括多個裝置晶粒；以及第一包封材料，將所述多個第一封裝組件包封於其中；將所述第三封裝體的至少一部分放置於印刷電路板中的第一凹槽中，在所述放置時，所述第一封裝體是未經鋸切的經重構晶圓，其中所述第一凹槽自所述印刷電路板的頂表面延伸至位於所述印刷電路板的所述頂表面與底表面之間的中間水平高度；以及執行打線接合以將所述第三封裝體電性連接至所述印刷電路板。
  2. 如申請專利範圍第1項所述的方法，更包括形成所述第二封裝體，所述形成所述第二封裝體包括：在基底之上形成多個重佈線，其中所述多個重佈線位於所述基底與所述第一封裝體之間。
  3. 如申請專利範圍第1項所述的方法，更包括形成所述第二封裝體，所述形成所述第二封裝體包括：將多個第二封裝組件包封於第二包封材料中；以及在所述多個第二封裝組件之上形成電性連接至所述多個第二封裝組件的多個重佈線，其中所述多個第二封裝組件包括額外的 多個裝置晶粒。
  4. 如申請專利範圍第1項所述的方法，其中所述印刷電路板更包括第二凹槽，所述第二凹槽自所述印刷電路板的所述底表面延伸至所述中間水平高度，且所述方法更包括：將冷卻系統貼合至所述第三封裝體，其中所述冷卻系統延伸至所述第二凹槽中。
  5. 如申請專利範圍第1項所述的方法，更包括藉由熱界面材料將金屬板黏合至所述印刷電路板，其中所述印刷電路板包括穿透過所述印刷電路板的虛設金屬特徵，所述熱界面材料與所述虛設金屬特徵交疊。
  6. 一種形成封裝體的方法，包括：重構第一晶圓，包括：將多個第一封裝組件包封於第一包封材料中，其中所述多個第一封裝組件包括不同類型的多個裝置晶粒；形成與所述第一包封材料及所述多個第一封裝組件交疊的多個第一重佈線；以及在所述多個第一重佈線之上形成電性連接至所述多個第一重佈線的多個第一電性連接件；重構第二晶圓；修整所述第一晶圓的多個邊緣部分，其中在所述修整之後，所有的所述多個第一封裝組件及所述多個第一重佈線保留於所述第一晶圓中； 在所述修整後，將所述第一晶圓接合至所述第二晶圓以形成封裝體，其中所述多個第一重佈線位於所述第一包封材料與所述第二晶圓之間且位於所述第一包封材料與所述多個第一電性連接件之間；將所述封裝體貼合至印刷電路板；以及將所述封裝體上的多個第一傳導特徵電性連接至所述印刷電路板上的多個第二傳導特徵。
  7. 如申請專利範圍第6項所述的方法，其中所述重構所述第二晶圓包括：將多個第二封裝組件包封於第二包封材料中；以及形成連接至所述多個第二封裝組件的多個第二重佈線。
  8. 一種封裝體，包括：第一晶圓，包括：多個第一封裝組件，包括多個第一裝置晶粒；第一包封體，將所述多個第一封裝組件包封於其中；以及多個第一重佈線，對所述多個第一封裝組件進行內連；第二晶圓，接合至所述第一晶圓，其中所述第二晶圓包括：多個第二封裝組件，包括多個第二裝置晶粒；第二包封體，將所述多個第二封裝組件包封於其中；以及多個第二重佈線，對所述多個第二封裝組件進行內連；印刷電路板，其中所述第二晶圓黏合至所述印刷電路板，其中所述第二晶圓延伸至所述印刷電路板中；以及 多個電性連接部，將所述第二晶圓上的多個第一接合墊連接至所述印刷電路板上的多個接合墊，其中所述多個第一重佈線與所述多個第二重佈線位於所述第一包封體與所述第二包封體之間。
  9. 如申請專利範圍第8項所述的封裝體，更包括延伸至所述印刷電路板中的冷卻系統，其中所述冷卻系統貼合至所述第二晶圓的背面。
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