CN102315182A - 半导体芯片及其制造方法 - Google Patents

半导体芯片及其制造方法 Download PDF

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Publication number
CN102315182A
CN102315182A CN2010106219546A CN201010621954A CN102315182A CN 102315182 A CN102315182 A CN 102315182A CN 2010106219546 A CN2010106219546 A CN 2010106219546A CN 201010621954 A CN201010621954 A CN 201010621954A CN 102315182 A CN102315182 A CN 102315182A
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China
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width
copper post
metal layer
lower metal
semiconductor chip
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CN102315182B (zh
Inventor
黄见翎
黄英叡
林正怡
雷弋易
林正忠
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例公开了一种半导体芯片及其制造方法，其中半导体芯片包含一导电凸块位于一半导体芯片上。提供一基材，其上具有一连接焊盘，该连接焊盘上具有一凸块下金属层。铜柱具有一顶面及凹型侧壁，该顶面具有一第一宽度。一镍层，具有一顶面及一底面，位于该铜柱的顶面上。该镍层的底面具有一第二宽度。第二宽度对第一宽度的比例为约0.93至1.07。一焊料位于该盖层的该顶面上。本发明可减少导电柱与焊料之间的界面因应力而产生的破裂。

Description

半导体芯片及其制造方法
技术领域
本发明涉及半导体封装工艺，尤其涉及一种倒装芯片封装的导电凸块的结构及其制造方法。
背景技术
倒装芯片技术在半导体装置封装中扮演着不可或缺的角色。倒装芯片微机电组成(assembly)包含使用焊料凸块作为内连线，直接电性连接面朝下(face down)的电子元件至基材(例如电路板)上。由于倒装芯片封装相较于其他封装方法具有尺寸、效能、及设计弹性上的优势，使倒装芯片封装的使用率大幅成长。
近来，已发展出铜柱(copper pillar)技术。电子元件借由铜柱来取代焊料凸块，连接电子元件及基材。铜柱技术可使凸块桥接的机率达到最低，减少电路的电容负载，及可使电子元件在更高的频率下操作。
然而，传统的焊料凸块及铜柱工艺仍具有缺点。例如，在传统的焊料凸块工艺中，使用焊料作为掩模以蚀刻底下的凸块下金属层(under bumpmetallurgy，UBM)。然而，凸块下金属层可能会在蚀刻工艺中受到横向的侵蚀，造成凸块下金属层的底切(undercut)。凸块下金属层的底切可能会在焊料凸块工艺中导致应力产生。此种应力可能会造成底下的基材中的低介电常数介电层破裂。在铜柱工艺中，应力可能沿着铜柱及用以连接电子元件的焊料之间的界面破裂，也会沿着底切及铜柱之间的界面破裂，因而可能会导致高漏电流并严重影响可靠度。
因此，业界所需的是一种改良的结构及方法，来形成适于半导体晶片的导电柱体，且具有良好的电性效能。
发明内容
为克服现有技术的缺陷，本发明提供一种半导体芯片，包括：一基材；一连接焊盘，位于该基材上；一凸块下金属层，位于该连接焊盘上；一铜柱，位于该凸块下金属层上，该铜柱具有一顶面及一凹型侧壁，其中该顶面具有一第一宽度；一镍盖层，具有一顶面及一底面，位于该铜柱的该顶面上，该镍盖层的底面具有一第二宽度，其中该第二宽度对该第一宽度的比例为约0.93至1.07；以及一焊料，位于该镍盖层的该顶面上。
本发明还提供一种半导体芯片的制造方法，包括：提供一基材；形成一连接焊盘于该基材上；沉积一凸块下金属层于该连接焊盘上；形成一铜柱于该凸块下金属层上；沉积一镍层于该铜柱上，其中该镍层及该铜柱之间具有一界面；沉积一焊料于该镍层上；在一水溶液中蚀刻该镍层及该铜柱，该水溶液包含55至85体积百分比的磷酸、小于1体积百分比的以叠氮为主的化合物及小于1体积百分比的锡；以及在蚀刻该镍层及该铜柱后，蚀刻该凸块下金属层。
本发明还提供一种半导体芯片的制造方法，包含：提供一基材；形成一连接焊盘于该基材上；沉积一含铜的凸块下金属层于该连接焊盘上；沉积一镍层于该凸块下金属层上；
沉积一焊料于该镍层上：以及在一水溶液中蚀刻该镍层及该凸块下金属层，该水溶液包含36至42体积百分比的磷酸、2至3体积百分比的硝酸、44至49体积百分比的醋酸及2至3体积百分比的锡。
在本发明实施例提供的半导体芯片及其制造方法中，第一宽度对第二宽度的适当比例能够减少应力，而此种应力会沿着导电柱及焊料(在随后工艺中用于连接元件)之间的界面产生破裂。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。
附图说明
图1～图7、图8A、图8B、图9～图14示出依照本发明实施例的结构在各种制造阶段的剖面图。
【主要附图标记说明】
101～基材          103～内连线层
105～第一保护层    107～连接焊盘
109～第二保护层    111～开口
113～缓冲层          114～侧壁
115～结合开口        117～凸块下金属层
117a～铜层           117b～钛层
119～光致抗蚀剂层    121～孔洞
123～铜柱            125～铜柱顶面
127～镍盖层          129～镍盖层底面
131～镍盖层顶面      133～焊料
135～元件            137～焊球
139～底部填充材料    141～镍层
143～焊材            W1～第一宽度
W2～第二宽度
具体实施方式
本发明接下来将详加讨论各种的实施例的制造及讨论。然而，值得注意的是，本发明所提供的这些实施例仅提供本发明的发明概念，且其可以宽广的形式应用于各种特定情况下。在此所讨论的实施例仅用于举例说明，并非以各种形式限制本发明。
图1至图14示出依照本发明一或多个实施例的结构在各种制造阶段的剖面图。在此所述的词汇“基材”是指半导体基材，且在其上形成有各种膜层及集成电路元件。基材可包含硅或化合物半导体，例如砷化镓、磷化铟、硅/锗或碳化硅。在某些实施例中，膜层可包含介电层、掺杂层、金属层、多晶硅层和/或可连接一膜层至其他一或多个膜层的通孔插塞(viaplug)。在某些实施例中，集成电路元件可包含晶体管、电阻和/或电容。基材可为含多个半导体芯片制造于基材表面上的晶片的一部分，其中每个芯片包含一或多个集成电路。这些半导体芯片是由芯片间的切割道(未显示)所分隔。以下的工艺步骤将在基材表面的多个半导体芯片上进行。
参见图1，提供一部分的基材101，其表面上具有多个半导体芯片。在图1所显示的一部分的基材101仅包含多个芯片中的一芯片的一部分。多个内连线层103形成在基材101的表面上。内连线层103包含位于一层或多层介电层中的一层或多层导电层。导电层与集成电路电性连接，并提供集成电路至较上方的膜层的电性连接。内连线层103中的介电层可包含，例如介电常数介于约2.9至3.8的低介电常数材料、介电常数介于约2.5至2.9的超低介电常数材料、前述的组合或其类似物。一般而言，介电常数越低的介电层越易碎，且易于脱层而导致膜层破裂。
第一保护层105形成在内连线层103上，以保护集成电路元件及内连线层103免于受到损坏及污染。第一保护层105可为一层或多层膜层，且通常包含例如未掺杂的硅玻璃(USG)、氮化硅(SiN)、二氧化硅、氮氧化硅。第一保护层105可避免或减少对于集成电路的水气、机械(mechanical)及热的损坏。
继续参见图1，连接焊盘107形成在第一保护层105上。连接焊盘107与内连线层103中的导电层电性接触，并提供与底下的集成电路元件电性连接。在一实施例中，连接焊盘107可包含导电材料，例如铝、铝合金、铜、铜合金或前述的组合。连接焊盘107可由物理气相沉积作沉积，例如使用含导电材料的溅镀靶材进行溅镀沉积，接着以光学光刻及蚀刻来图案化沉积层以形成连接焊盘107。
参见图2，第二保护层109形成在第一保护层105及连接焊盘107上。第二保护层109可包含一个或多个膜层，其可包含如前述的第一保护层所列的可用材料。第一保护层105及第二保护层109可具有相同或不同的材料。第二保护层109可由合适的沉积技术(例如化学气相沉积)沉积在第一保护层105及连接焊盘107上。在沉积后，接着进行光学光刻及蚀刻在连接焊盘107上的第二保护层109中，选择性地定义开口111。第二保护层109部分地覆盖连接焊盘107，剩余在开口111中的连接焊盘107的表面则暴露在外。第二保护层109可吸收或释放由基材封装所导致的热或机械应力。
参见图3，缓冲层113形成在第二保护层109及连接焊盘107上。缓冲层113包含聚酰亚胺、聚苯恶唑(polybenzoxazole，PBO)或环氧树脂，且厚度为约2μm至10μm。缓冲层113作为应力缓冲，以在组装工艺中减少传递至第一保护层105及第二保护层109的应力。在某些实施例中，首先沉积缓冲层113覆在第二保护层109上，并填满开口111以覆盖连接焊盘107的暴露表面。沉积缓冲层113后，接着以光学光刻及图案化来选择性定义一包含一部分的保护层109中的开口111及一部分的缓冲层113中的开口的结合开口(combined opening)。该结合开口115暴露出一部分的连接焊盘。结合开口115具有侧壁114。
参见图4，凸块下金属层117形成在缓冲层113上、内衬在结合开口115的侧壁114，及接触连接焊盘107的暴露部分。在某些实施例中，凸块下金属层117可包含多层导电材料，例如铜层117a加上钛层117b。凸块下金属层117中的每一层皆可使用电镀工艺形成，例如电化学电镀，或可依照所使用的材料选用使用其他工艺，例如溅镀、蒸镀、无电电镀或等离子体辅助式化学气相沉积(PECVD)。
参见图5，光致抗蚀剂层119形成在凸块下金属层117上，并经图案化以形成孔洞121，其暴露出至少位于结合开口115及连接焊盘107的暴露部分上的一部分的凸块下金属层117。光致抗蚀剂层扮演用于形成导电凸块的金属沉积工艺的模具。光致抗蚀剂材料可填满开口，适于使用在此工艺中。
参见图6，可以蒸镀、电镀或网印方式形成铜层，填充一部分的孔洞121，以形成凸块下金属层117上的铜柱123。铜柱123可为纯铜或铜合金。铜柱123具有顶面125。
镍盖层127形成在铜柱123的顶面125上，并填充一部分的孔洞121。在一实施例中，在含镍的无电电镀溶液中浸镀基材101，形成镍盖层127。镍是以化学反应工艺沉积在铜柱123的表面125上。镍盖层127具有底面129及顶面131。在铜柱123及镍盖层127之间定义有一界面。
继续参见图6，焊料133沉积在孔洞121中，焊料133填充镍盖层127的顶面131上的一部分的孔洞121。依照本发明一实施例，焊料133包含无铅焊料或共晶焊料。焊料133的熔点低于铜柱123及镍盖层127的熔点。
参见图7，移除光致抗蚀剂层119，并接着暴露出焊料133、镍盖层127、铜柱123及凸块下金属层117。
参见图8A，进行第一蚀刻工艺以蚀刻镍盖层127。在一实施例中，将基材101浸入至包含55至85体积百分比的磷酸、小于1体积百分比的以叠氮为主的化合物及小于1体积百分比的锡的水溶液中。在某些实施例中，水溶液包含体积百分比约70的磷酸。不受到理论的限制，可相信的是，以叠氮为主的化合物限制了对铜的蚀刻，锡限制了对焊料的蚀刻。该溶液可维持在约30至70℃的预定范围内。既然在铜柱123及焊料133的表面的蚀刻反应受到抑制，选择性蚀刻了镍盖层127。尽管存在有蚀刻抑制剂，水溶液仍蚀刻一小部分的焊料133及镍盖层127。水溶液对于蚀刻焊料133及镍盖层127相对速率比例为小于约1/15，且对蚀刻于铜柱123及镍盖层127的相对速率比例为小于约1/20。
参见图8B，进行第二蚀刻工艺以蚀刻凸块下金属层117。在一实施例中，首先，以包含氨水(NH4OH)、磷酸、硝酸、氢氟酸或硫酸的水溶液湿蚀刻凸块下金属层117的铜层117a。在湿蚀刻之后，铜柱123具有凹形侧壁。接着，以包含体积百分比小于1％的氢氟酸的水溶液湿蚀刻凸块下金属层117的钛层117b。在其他实施例中，在包含Cl2、CFx或CHFx的气态环境下干蚀刻凸块下金属层117的钛层117b。凸块下金属层117的第二蚀刻工艺可包含湿蚀刻、干蚀刻或前述的组合。
在蚀刻凸块下金属层117后，形成经蚀刻的镍盖层127及经蚀刻的铜柱123。经蚀刻的镍盖层127具有第一宽度W1。第一宽度W1邻近于经蚀刻的镍盖层127与经蚀刻的铜柱123之间的界面。换句话说，第一宽度W1靠近镍层127的底面129。经蚀刻的铜柱123具有第二宽度W2。第二宽度W2邻近于经蚀刻的镍盖层127及经蚀刻的铜柱123之间的界面。换句话说，第二宽度W2邻近于铜柱123的顶面。第一宽度W1对第二宽度W2的比例为约0.93至0.99，不管其机制是什么，该比例可减少镍盖层127及铜柱123之间的界面的应力，而这些应力可能会在随后的工艺中产生沿着铜柱与底部填充材料(用于密封元件与芯片间的空隙)之间的界面的破裂。
图9示出图8A及图8B中的各种工艺步骤，其中镍盖层127、铜柱123及凸块下金属层117的铜层117a是同时被蚀刻。在一实施例中，将基材101浸入至包含36至42体积百分比的磷酸、2至3体积百分比的硝酸、44至49体积百分比的醋酸及2至3体积百分比的锡的水溶液中。在某些实施例中，水溶液包含约40体积百分比的磷酸。可相信的是，锡抑制了对于焊料133的蚀刻。该溶液可维持在约30℃至45℃的预定温度下。水溶液中对于焊料133及镍盖层127的相对蚀刻速率为小于1/13，对于铜柱123及镍盖层127的相对蚀刻速率为介于1/3及5之间。在经湿蚀刻工艺之后，铜柱123具有凹形侧壁。
在移除凸块下金属层117中的一部分的铜层117a后，凸块下金属层117的钛层117b未由铜层117a所覆盖的部分，可能会如同前述被湿蚀刻或干蚀刻。
在经过蚀刻凸块下金属层117的一部分的铜层117a后，形成经蚀刻的镍盖层127及经蚀刻的铜柱123。经蚀刻的镍盖层127具有第一宽度W1。第一宽度W1邻近于经蚀刻的镍盖层127及经蚀刻的铜柱123之间的界面。换句话说，第一宽度W1邻近于经蚀刻的镍盖层127的底面129。经蚀刻的铜柱具有第二宽度W2。第二宽度W1邻近于经蚀刻的镍盖层127及经蚀刻的铜柱123之间的界面。换句话说，第二宽度W2邻近于铜柱123的顶面125。第一宽度W1对第二宽度W2的比例为约0.93至1.07。当比例为1时，在铜柱123及镍盖层127之间具有平滑的界面。不管其机制是什么，上述的第一宽度W1对第二宽度W2的比例可减少在镍盖层127及铜柱123之间的界面的应力，而此种应力可沿着铜柱123及底部填充材料(用于在随后工艺中密封元件及芯片间的空隙)之间的界面产生破裂。
参见图10，焊料133经回焊以覆盖镍盖层127的顶面131。回焊工艺可软化和/或融化焊料133，但无法软化和/或融化镍盖层127及铜柱123，以使焊料133可沿着顶面131流动。
图11示出前述的铜柱结构在与元件135接合后的剖面图。为了简化以便于说明，元件135仅显示为简单的芯片，而无更详细的构造。在一实施例中，元件135可包含半导体芯片、封装基材、电路板或其他类似的合适元件。基材101及元件135可能经由铜柱123作电性连接。在一实施例中，接合方法放置一焊球137于焊料133上，以接合铜柱123及元件133。
在接合工艺后，在基材101及电性元件133之间定义出一间隙。底部填充材料138可填充至该间隙中，以保护铜柱123及增加封装的可靠度。底部填充材料139减少铜柱123、基材101及元件133之间的应力，且在堆叠的电子元件中均匀地传递热。底部填充材料139可包含，但不限于，环氧树脂、聚酰亚胺、其他热塑性或热固性材料、或其他合适的相似材料。
图12至图14示出图6至图9所述的导电凸块制造的工艺步骤的变化例。在图12中重复的标号代表与图6所示的元件相同或相似。
参见图12，镍层141形成在凸块下金属层117上，并填充一部分的孔洞121。在一实施例中，在含镍的无电电镀溶液中浸镀基材101，形成镍层141。接着，镍以化学反应工艺沉积至凸块下金属层117的表面上。接着，沉积焊料143至孔洞121中，填充焊料143在镍层141顶面上的一部分的孔洞121中。依照本发明一实施例，焊料143包含无铅焊料或共晶焊料。
参见图13，移除光致抗蚀剂层119，暴露出焊料143、镍层141及凸块下金属层171。
参见图14，同时蚀刻镍层141及凸块下金属层117的铜层117。在一实施例中，在含36至42体积百分比的磷酸、2至3体积百分比的硝酸、44至49体积百分比的醋酸、及2至2体积百分比的锡的水溶液中浸镀基材101。在某些实施例中，水溶液包含体积百分比约40的磷酸。可相信的是，锡抑制了对于焊料的蚀刻。溶液可保持在约30℃至约45℃之间的预定温度中。在水溶液中，焊料143对镍层141的相对蚀刻比例为小于1/13，铜层117a对镍层141的相对蚀刻比例为1/3至5。该蚀刻工艺可在镍层141及凸块下金属层117的铜层117a之间产生平滑的界面。平滑的界面可减少应力，而底下低介电常数材料降低破裂的机率。因此，可改善某些在传统焊料凸块的工艺中可能会有的缺点。
在移除未被镍层141所覆盖的铜层117a后，未被铜层117a所覆盖的凸块下金属层117的钛层117b经含体积百分比小于1的氢氟酸的水溶液蚀刻。在其他实施例中，含Cl2、CFx或CHFx的气态环境下干蚀刻含凸块下金属层117的钛层117b。凸块下金属层117的蚀刻工艺可包含湿蚀刻、干蚀刻或前述的组合。
本发明的各种实施例可用于解决传统导电凸块工艺的缺点。例如，第一宽度W1对第二宽度W2的适当比例将减少应力，而此种应力会沿着导电柱123及焊料133/137(在随后工艺中用于连接元件)之间的界面产生破裂。在各种实施例中，将可提供在镍盖层127及铜柱123之间具有合适的界面形状，也可提供在镍层141及凸块下金属层117之间具有合适的界面形状，并将可提高组装的产率。
虽然本发明已以数个较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中具有普通知识的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当以所附的权利要求所界定的范围为准。此外，本领域普通技术人员将可依照本发明所公开的现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤达成相同的功能或相同的结果。因此本发明的保护范围包含这些程序、机器、制造、物质的组合、功能、方法或步骤。再者，每一权利要求都可视为建构一单独的实施例，且各权利要求及实施例的结合皆在本发明的范围中。

Claims (10)

1.一种半导体芯片，包括：
一基材；
一连接焊盘，位于该基材上；
一凸块下金属层，位于该连接焊盘上；
一铜柱，位于该凸块下金属层上，该铜柱具有一顶面及一凹型侧壁，其中该顶面具有一第一宽度；
一镍盖层，具有一顶面及一底面，位于该铜柱的该顶面上，该镍盖层的底面具有一第二宽度，其中该第二宽度对该第一宽度的比例为约0.93至1.07；以及
一焊料，位于该镍盖层的该顶面上。
2.如权利要求1所述的半导体芯片，还包含在该铜柱及该镍盖层之间有一平滑界面。
3.如权利要求1所述的半导体芯片，其中该第二宽度对该第一宽度的比例为约0.93至0.99。
4.一种半导体芯片的制造方法，包括：
提供一基材；
形成一连接焊盘于该基材上；
沉积一凸块下金属层于该连接焊盘上；
形成一铜柱于该凸块下金属层上；
沉积一镍层于该铜柱上，其中该镍层及该铜柱之间具有一界面；
沉积一焊料于该镍层上；
在一水溶液中蚀刻该镍层及该铜柱，该水溶液包含55至85体积百分比的磷酸、小于1体积百分比的以叠氮为主的化合物及小于1体积百分比的锡；以及
在蚀刻该镍层及该铜柱后，蚀刻该凸块下金属层。
5.如权利要求4所述的半导体芯片的制造方法，其中以水溶液蚀刻该镍层的步骤是在30℃至70℃下进行。
6.如权利要求4所述的半导体芯片的制造方法，其中在蚀刻镍层、该铜柱及蚀刻该凸块下金属层之后，邻近于该界面的经蚀刻的铜柱具有一第一宽度，邻近于该界面的经蚀刻的镍层具有一第二宽度，且该第二宽度对该第一宽度的比例为约0.93至0.99。
7.如权利要求4所述的半导体芯片的制造方法，其中该铜柱为凹形。
8.一种半导体芯片的制造方法，包含：
提供一基材；
形成一连接焊盘于该基材上；
沉积一含铜的凸块下金属层于该连接焊盘上；
沉积一镍层于该凸块下金属层上；
沉积一焊料于该镍层上：以及
在一水溶液中蚀刻该镍层及该凸块下金属层，该水溶液包含36至42体积百分比的磷酸、2至3体积百分比的硝酸、44至49体积百分比的醋酸及2至3体积百分比的锡。
9.如权利要求8所述的半导体芯片的制造方法，其中在该水溶液中的蚀刻步骤是在30℃至45℃下进行。
10.如权利要求8所述的半导体芯片的制造方法，还包含在该凸块下金属层上及该镍层底下形成一铜柱，因而在该铜柱及该镍层之间形成一界面，其中邻近于该界面的该铜柱具有一第一宽度，邻近于该界面的该镍层具有一第二宽度，且该第二宽度对该第一宽度的比例为约0.93至1.07。
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