CN109979903B - 具有凸块结构的半导体器件和制造半导体器件的方法 - Google Patents
具有凸块结构的半导体器件和制造半导体器件的方法 Download PDFInfo
- Publication number
- CN109979903B CN109979903B CN201811426233.2A CN201811426233A CN109979903B CN 109979903 B CN109979903 B CN 109979903B CN 201811426233 A CN201811426233 A CN 201811426233A CN 109979903 B CN109979903 B CN 109979903B
- Authority
- CN
- China
- Prior art keywords
- copper
- layer
- semiconductor device
- height
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/11622—Photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1183—Reworking, e.g. shaping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13247—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10252—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10271—Silicon-germanium [SiGe]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10272—Silicon Carbide [SiC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
半导体器件包括衬底和设置在衬底上方的至少一个凸块结构。至少一个凸块结构包括设置在衬底上方的由金属形成的柱,该金属相对于铜或铜合金与焊料相比具有更低的可焊性。焊料合金形成在比铜或铜合金具有更低的可焊性的金属的上表面正上方并且与金属的上表面接触。该柱具有大于10μm的高度。本发明实施例涉及具有凸块结构的半导体器件和制造半导体器件的方法。
Description
技术领域
本发明实施例涉及具有凸块结构的半导体器件和制造半导体器件的方法。
背景技术
随着具有更好性能的消费器件响应于消费者需求而变得越来越小,这些器件的各个组件也必须减小尺寸。构成诸如手机、计算机平板电脑等消费器件的主要组件的半导体器件已变得越来越小。随着诸如在半导体器件之间形成连接的半导体制造技术的进步,半导体器件尺寸的减小得到满足。
随着电子工业基于Si通孔(TSV)技术开发三维集成电路(3D IC),正在积极研究用于互连堆叠芯片的凸块的处理和可靠性。在减小凸块尺寸的过程中,凸块的直径减小至比倒装芯片焊点的直径小约一个数量级,并且体积小约1000倍。小得多的焊点尺寸增加了凸块焊点失效的可能性。
发明内容
根据本发明的一些实施例,提供了一种半导体器件,包括:衬底;以及至少一个凸块结构,设置在所述衬底上方,其中,所述至少一个凸块结构包括:柱,设置在所述衬底上方,由金属形成,与铜或铜合金至焊料合金的可焊性相比,所述金属具有至焊料合金的更低的可焊性;以及焊料合金,形成在比铜或铜合金具有更低的可焊性的所述金属的上表面正上方并且与所述金属的上表面接触;其中,所述柱具有大于10μm的高度。
根据本发明的另一些实施例,还提供了一种半导体器件,包括:第一衬底,包括第一电路;以及第二衬底;其中,所述第一衬底通过包括设置在第一柱和第二柱之间的焊料层的连接件连接至所述第二衬底,以及所述第一柱由镍基材料形成并且具有大于10μm的高度。
根据本发明的又一些实施例,还提供了一种制造半导体器件的方法,包括:在衬底上方形成光刻胶层;图案化所述光刻胶层以形成暴露所述衬底的多个开口;在所述多个开口中沉积比铜或铜合金材料具有更低的可焊性的金属;在所述多个开口中的所述金属上方形成焊料层,所述金属比所述铜或铜合金材料具有更低的可焊性;以及去除所述光刻胶层,其中,所述焊料层与比所述铜或铜合金材料具有更低的可焊性的金属直接接触。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制并且仅用于说明的目的。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的实施例的凸块结构的示意图。
图2A和图2B示出了根据本发明的实施例的制造半导体器件的方法的各个操作的一个。图2A是平面图,并且图2B是沿着图2A的线A-A的截面图。
图3是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图4是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图5是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图6是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图7是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图8是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图9是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图10A和图10B示出了根据本发明的实施例的制造半导体器件的方法的各个操作的一个。图10A是沿着图10B的平面图的线B-B的截面图。
图11是根据本发明的实施例的示出制造半导体器件的方法的流程图。
图12是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图13是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图14是根据本发明的实施例的示出制造半导体器件的方法的各个操作的一个的截面图。
图15是根据本发明的实施例的示出制造半导体器件的方法的流程图。
图16是根据本发明的实施例的凸块结构的示意图。
图17是根据本发明的实施例的示出制造半导体器件的方法的流程图。
图18是根据本发明的实施例的凸块结构的示意图。
图19是根据本发明的实施例的示出制造半导体器件的方法的流程图。
图20是根据本发明的实施例的凸块的示意图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,元件的尺寸不限于公开的范围或值,但是可能依赖于工艺条件和/或期望的器件性能。此外,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的,各个部件可任意地以不同比例绘制。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。此外,术语“由…制成”可能意味着“包括”或“由…组成”。
图1是根据本发明的实施例的凸块结构的示意图。半导体器件10具有衬底15和设置在衬底15上的至少一个凸块结构55。接合焊盘20设置在衬底15上。接合焊盘20电连接至衬底15的电路。凸块结构55经由接合焊盘20连接至衬底15的电路。至少一个凸块结构55包括主要由金属形成的柱25,与铜或铜合金至焊料合金的可焊性相比,该金属具有至焊料合金的更小的可焊性(润湿性)。换句话说,与铜或铜合金相比,具有更小的可焊性(或润湿性)的金属不太可能在金属和焊料合金的界面处与焊料合金的组分形成金属间化合物(或合金)。因为柱比铜或铜合金具有更低的可焊性,所以抑制了焊料沿着柱的侧向下流动。在一些实施例中,柱25由镍基材料形成。在一些实施例中,镍基材料包括镍和含有50mol%或更多镍的镍合金。在一些实施例中,凸块结构55仅包括一个镍基层25。在一些实施例中,半导体器件10包括设置在柱25和衬底15之间的接合焊盘20上的凸块下金属40。
在一些实施例中,凸块结构55包括设置在柱25和凸块下金属40之间的Cu或Cu合金层30。在一些实施例中,选择具有更低的可焊性(或润湿性)的金属,以非常慢的形成金属间化合物,从而防止焊料移动越过柱25的高度并且接触下面的Cu或Cu合金层30。在一些实施例中,绝缘层60形成在衬底15上方并且围绕凸块下金属40。
在一些实施例中,接合焊盘20由包括铝、铜、银、金、镍、钨、钛、它们的合金和/或它们的多层的合适的导电金属形成。
在一些实施例中,凸块结构55包括设置在柱25上的焊料层35。在一些实施例中,焊料层35由诸如AgSn、SnAgCu、PbSn和CuSn的含锡合金形成。在一些实施例中。焊料层35与柱25的上表面直接物理接触。在一些实施例中,焊料层35不与Cu或Cu合金层30直接物理接触。
在一些实施例中,柱25具有大于10μm并且介于10μm至约30μm的范围内的高度D1。在柱高度D1大于10μm时,柱25具有足够的高度,从而抑制焊料沿着凸块向下流动并且抑制了在焊料接合件中形成空隙或与其它半导体器件部件的接触并且引起短路。柱高度D1大于典型的覆盖层高度。在常规凸块结构中,覆盖层用作阻挡层,以防止Cu或Cu合金层中的Cu扩散至焊料层中。在柱高度大于约30μm时,由于集成电路组件之间的间隔增加,集成电路中器件密度减小。在一些实施例中,柱25的直径在从约5μm至约40μm的范围内。在一些实施例中,柱25的直径在从约20μm至约25μm的范围内。在实施例中,半导体器件10包括Cu或Cu合金层30,其在柱25和凸块下金属40的上表面之间具有约5μm至约10μm的高度D2。在一些实施例中,柱25的高度D1大于Cu或Cu合金层30的高度D2。在一些实施例中,柱25的高度D1与Cu或Cu合金层30的高度D2的比率(D1/D2)在从约1.5/1至约6/1的范围内。在一些实施例中,柱25的高度D1与Cu或Cu合金层30的高度D2的比率(D1/D2)在从约3/1至5/1约的范围内。在一些实施例中,柱25的高度D1与Cu或Cu合金层30的高度D2的比率(D1/D2)在从约2/1至4/1约的范围内。
在一些实施例中,在给定高度处,凸块结构55的侧壁的材料组分与凸块结构55的内部的材料组分基本相同。换句话说,在一些实施例中,在凸块结构55的侧壁上没有有意形成的层。例如,在一些实施例中,在柱25的侧壁上没有有意形成的钝化层,诸如氮化物层。
在一些实施例中,半导体器件10是其中包括诸如晶体管的有源器件的器件管芯。在其它实施例中,半导体器件10包括其上形成有器件管芯的封装衬底或中介层。在一些实施例中,凸块结构55用于将半导体芯片或管芯接合至中介层、封装衬底或另一半导体芯片或管芯。
图2A和图2B示出了根据本发明的实施例的制造半导体器件的方法的各个操作的一个。图2A是平面图,并且图2B是沿着图2A的线A-A的截面图。如图2A所示,多个接合焊盘20(其上形成凸块)布置在衬底15的表面上。接合焊盘20由包括铝、铜、银、金、镍、钨、钛、它们的合金和/或它们的多层的合适的导电金属形成。接合焊盘通过合适的金属沉积操作形成,合适的金属沉积操作包括电镀或化学镀、包括溅射的物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、热蒸发或电子束蒸发。在一些实施例中,接合焊盘20布置为行-列布置。
图3至图10B是根据本发明的实施例的示出制造半导体器件的方法的各个阶段的截面图。在一些实施例中,如图3所示,在接合焊盘和绝缘层60上方形成凸块下金属40。
在一些实施例中,包括器件160的电路155设置在衬底12上。在一些实施例中,器件160包括晶体管、电容器、电感器、电阻器等。在一些实施例中,接合焊盘20和凸块结构55通过下面的互连件165(包括布线层和通孔)电连接至电路155。互连件165的布线层和通孔可以由铜或铜合金、铝、钨、镍或任何其它合适的金属形成。可以使用镶嵌工艺形成布线层和通孔。在一些实施例中,电路155嵌入在诸如层间介电(ILD)层或金属间介电(IMD)层的绝缘层170内。
在一些实施例中,衬底15包括半导体基底12。半导体基底12由选自硅、金刚石、锗、SiGe、SiGeSn、SiGeC、GeSn、SiSn、GaAs、InGaAs、InAs、InP、InSb、GaAsP、GaInP和SiC组成的组中的至少一种形成。在一些实施例中,半导体基底12是硅晶圆。
在一些实施例中,在衬底15上方形成绝缘层60。在一些实施例中,绝缘层60是氧化物层。在一些实施例中,使用合适的光刻和蚀刻操作图案化绝缘层60以形成开口,在开口中沉积凸块下金属40。在一些实施例中,凸块下金属通过合适的金属沉积操作形成,合适的金属沉积操作包括电镀或化学镀、包括溅射的物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、热蒸发和电子束蒸发。在一些实施例中,在形成凸块下金属之前,在接合焊盘上沉积晶种层(未示出)。在一些实施例中,凸块下金属40在绝缘层60上方延伸,并且通过合适的操作(诸如化学机械抛光(CMP))去除过量的凸块下金属。
在实施例中,凸块下金属40包括设置在焊盘20上的钛基层,以及设置在钛基层上的溅射沉积的铜基层。钛基材料包括钛以及含有50mol%或更多钛的钛合金和钛化合物。铜基材料包括铜以及含有50mol%或更多铜的铜合金和铜化合物。在实施例中,钛基层是厚度在从20nm至70nm的范围的溅射沉积的Ti或TiW层。
接下来,在本发明的一些实施例中,如图4所示,在凸块下金属40和绝缘层60上方形成光刻胶层65。光刻胶层65可以是正性光刻胶或负性光刻胶。当光刻胶是正性光刻胶时,光刻胶的暴露于光化辐射的部分变得可溶于显影剂并且在显影操作期间去除。当光刻胶是负性光刻胶时,光刻胶的暴露于光化辐射的部分变得不溶于显影剂并且保留在器件上,而在显影操作期间去除未暴露于光化辐射的部分。在一些实施例中,光化辐射是包括i线和g线辐射的紫外辐射,以及深紫外辐射;极紫外(EUV)辐射;和电子束辐射。在一些实施例中,光化辐射由汞弧灯或激光(包括ArF和KrF准分子激光);和锡等离子体激发的激光产生。
如图5所示,随后将光刻胶层65选择性地暴露于光化辐射,并且显影以形成暴露凸块下金属40的多个开口75。在一些实施例中,开口75基本是直径在从约10μm至约40μm的范围的圆形。在一些实施例中,开口75的直径在从约20μm至约25μm的范围。
在一些实施例中,如图6所示,随后在凸块下金属40上方的开口75中形成第一金属层30。在一些实施例中,第一金属层30是铜或铜合金。第一金属层30可以通过合适的金属沉积操作形成,合适的金属沉积操作包括电镀或化学镀、包括溅射的物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、热蒸发和电子束蒸发。在一些实施例中,在形成第一金属层之前,在凸块下金属层上沉积晶种层(未示出)。在一些实施例中,第一金属层沉积至约5μm至约10μm的厚度。
转至图7,在第一金属层30上方的开口75中形成第二金属层25。在一些实施例中,第二金属层25形成金属的柱25,与铜或铜合金至焊料合金的可焊性相比,该金属具有至焊料合金的更小的可焊性或润湿性。
在一些实施例中,第二金属层25的高度D1大于第一金属层30的高度D2。在一些实施例中,第二金属层25的高度D1介于10μm至约30μm的范围内且大于10μm。在一些实施例中,第二金属层25的直径在从约5μm至约40μm的范围内。在一些实施例中,第二金属层25的直径在从约20μm至约25μm的范围内。在一些实施例中,第一金属层30在第二金属层25和凸块下金属40的上表面之间具有约5μm至约10μm的高度D2。在一些实施例中,第二金属层25的高度D1与第一金属层30的高度D2的比率(D1/D2)在从约1.5/1至约6/1的范围内。在一些实施例中,第二金属层25的高度D1与第一金属层30的高度D2的比率(D1/D2)在从约3/1至约5/1的范围内。在一些实施例中,第二金属层25的高度D1大于第一金属层30的高度D2。
在一些实施例中,第二金属层或柱25主要由选自铝、铬、铁、锰、镁、钼、镍、铌、钽、钛、钨、锌以及它们的合金组成的组的金属形成。在一些实施例中,第二金属层或柱25由镍基材料形成。在一些实施例中,镍基材料包括镍和含有50mol%或更多镍的镍合金。在一些实施例中,第二金属层或柱25通过合适的金属沉积操作形成,合适的金属沉积操作包括电镀或化学镀、包括溅射的物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、热蒸发和电子束蒸发。
如图8所示,在一些实施例中,随后在第二金属层25上方的开口中形成焊料层35。在一些实施例中,焊料层35包括共晶焊料,诸如选自AgSn、SnAgCu、PbSn和CuSn组成的组的合金。可以使用其它合适的焊料,只要相对于铜或铜合金至焊料的可焊性,该柱具有至焊料的更低的可焊性(润湿性)。在一些实施例中,焊料层35的厚度为约2μm至约10μm。在一些实施例中,从光刻胶层65之上去除过量的焊料。
如图9所示,随后去除光刻胶层65,以暴露焊料层35、柱25和第一金属层30的侧壁。在一些实施例中,使用合适的光刻胶剥离剂去除光刻胶层65。然后,诸如通过合适的蚀刻操作去除凸块下金属40的暴露部分。
在一些实施例中,如图10A所示,在光刻胶层65的去除之后,回流焊料层35以形成平滑的半球形状,以提供具有多个凸块结构55的半导体器件10。图10A是沿着图10B的平面图的线B-B的截面图。通过将焊料加热至其软化和流动的温度来回流焊料层35。
图10B是示出半导体器件10上的凸块结构55的行-列布置的平面图。示出了3×3布置的凸块结构,但是本发明不限于3×3布置。包括更少或更多数量的行或列的凸块结构的其它布置包括在本发明的范围内。例如,该布置可以是10×10布置或更多数量的列和行。凸块结构的布置不限于矩形布置。在一些实施例中,其它布置包括交错的行和列,其中,每个凸块结构紧邻六个其它凸块结构。在其它实施例中,凸块结构布置为同心圆布置。在其它实施例中,凸块结构布置在衬底的外围周围或衬底的中心部分中。在其它实施例中,凸块结构是不规则间隔的。在一些实施例中,在衬底上形成多达约10,000个凸块结构。
在一些实施例中,如平面图所示,凸块结构55的直径D3在从约5μm至约40μm的范围内。在一些实施例中,凸块结构55的直径D3在从约20μm至约25μm的范围内。在一些实施例中,多个凸块结构55布置为行-列布置,该行-列布置在X方向上具有从一个凸块结构55的中心至相邻凸块结构55的中心的约15μm至约60μm的间距S1。在一些实施例中,多个凸块结构55在X方向上具有从一个凸块结构55的中心至相邻凸块结构55的中心的约25μm至约40μm的间距S1。在一些实施例中,多个凸块结构55在Y方向上具有从一个凸块结构55的中心至相邻凸块结构55的中心的约15μm至约60μm的间距S2。在一些实施例中,多个凸块结构55在Y方向上具有从一个凸块结构55的中心至相邻凸块结构55的中心的约25μm至约40μm的间距S2。
在一些实施例中,凸块结构的直径D3与X方向上的间距S1的比率在从约1/12至约8/9的范围内。在一些实施例中,凸块结构的直径D3与X方向上的间距S1的比率在从约1/3至约2/3的范围内。在一些实施例中,凸块结构的直径D3与Y方向上的间距S2的比率在从约1/12至约8/9的范围内。在一些实施例中,凸块结构的直径D3与Y方向上的间距S2的比率在从约1/3至约2/3的范围内。在一些实施例中,X方向上的间距S1与Y方向上的间距S2基本相同。在一些实施例中,X方向上的间距S1大于Y方向上的间距S2。在一些实施例中,X方向上的间距S1小于Y方向上的间距S2。
应该理解,图10A和图10B所示的器件经历进一步半导体工艺以形成诸如外部接触件、介电层、集成至模块等的各个部件。
图11是示出根据本发明的实施例的制造半导体器件的另一方法200的流程图。在操作S210中,在第一和第二衬底上方形成铜或铜合金层。铜或铜合金层可以通过合适的金属沉积操作形成,合适的金属沉积操作包括电镀或化学镀、包括溅射的物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、热蒸发或电子束蒸发。在操作S220中,在衬底上的每个铜或铜合金上方形成与铜或铜合金至焊料合金的可焊性相比具有更低的可焊性的金属(具有大于约10μm的厚度)。在一些实施例中,铜或铜合金层具有高达约30μm的厚度。在一些实施例中,焊料合金选自由AgSn、SnAgCu、PbSn和CuSn组成的组。比铜或铜合金具有更低的可焊性的金属层可以通过合适的金属沉积操作形成,合适的金属沉积操作包括电镀或化学镀、包括溅射的物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、热蒸发或电子束蒸发。随后在操作S230中,在衬底上的比铜或铜合金具有更低的可焊性的每个金属层上方形成焊料层,从而在第一衬底和第二衬底的每个上形成凸块结构。
随后在操作S240中,将第一衬底和第二衬底布置为使得第一衬底上的凸块结构和第二衬底上的凸块结构彼此相对并且彼此对准。接下来,在操作S250中,使第一衬底上的凸块结构和第二衬底上的凸块结构彼此接触。然后,在操作S260中,对凸块施加能量,使得凸块结构上的焊料层流动,并且使第一衬底上的凸块结构和第二衬底上的凸块结构熔合在一起。
图12至图15示出了根据本发明的实施例的将两个衬底15、15’上的凸块结构55、55’熔合在一起的方法。如图12所示,第一半导体器件10和第二半导体器件10’包括根据图2A至图10B中描述的操作形成的多个凸块结构55。第二半导体器件10’定向为使得第一半导体器件10中的凸块结构55的焊料层35面向第二半导体器件10’中的凸块结构55’的焊料层35’并且与第二半导体器件10’中的凸块结构55’的焊料层35’对准。在一些实施例中,第二半导体器件10’是其中形成有电路155’的封装衬底、中介层或衬底。
如图13所示,第一半导体器件10的凸块结构55和第二半导体器件10’的凸块结构55’彼此接触并且施加能量以使焊料层35、35’软化并且相互流入,并且然后熔合以在去除施加的能量时,在第一半导体器件10和第二半导体器件10’连接的位置的焊点90处形成金属间键。在实施例中,在衬底熔合在一起之后,第一衬底15通过柱/焊料/柱连接件接合至第二衬底15’,从而形成半导体器件80,半导体器件80是第一半导体器件10和第二半导体器件10’的组合。在一些实施例中,能量是热能、超声能量或热能和超声能量的组合。在一些实施例中,热能由加热的空气、红外加热灯或激光器供应。在一些实施例中,超声能量由超声换能器施加。
为了增加良率并且延长半导体器件80的寿命,在一些实施例中,如图14所示,在结合的衬底15、15’之间形成底部填充材料95。底部填充材料将焊料互连件嵌入在底部填充材料内。底部填充材料95机械地连接衬底15、15’并且减小焊点90上的应力,以改进器件良率和寿命。
在一些实施例中,底部填充材料95是可热固化的液态聚合物树脂。可以将底部填充材料95施加至第一衬底15和第二衬底15’之间的区的边缘,并且然后通过毛细管作用将底部填充材料95吸入第一衬底15和第二衬底15’之间的空隙中。在一些实施例中,实施底部填充材料的若干施加以完全填充空隙。在一些实施例中,通过在施加底部填充材料95之前对空隙施加真空来辅助底部填充材料95的施加。在一些实施例中,通过将底部填充聚合物树脂加热至低于树脂的固化点的温度以降低其粘度来辅助底部填充操作。
在一些实施例中,底部填充材料是液态树脂。在一些实施例中,包括诸如硅氧烷、环氧树脂和聚酰胺的热固性模塑料的多种树脂可以用作底部填充材料。环氧树脂包括酚醛环氧树脂。底部填充树脂可以可选地含有填料,诸如二氧化硅、氧化铝、滑石等。
图15是示出根据本发明的另一实施例的制造具有凸块结构55a的半导体器件10a的方法300的流程图。图16中示出了根据图15的方法300形成的半导体器件10a。半导体器件10a具有衬底15和设置在衬底15上的至少一个凸块结构55a。在操作S310中,在衬底15上方沉积凸块下金属40。在一些实施例中,凸块下金属40包括钛基层和/或铜基层。在一些实施例中,凸块下金属40具有约5nm至约500nm的厚度。在S320中,在沉积凸块下金属之后,在凸块下金属上方形成金属层以形成柱25,与铜或铜合金至焊料合金的可焊性相比,金属层具有至焊料合金的更低的可焊性,并且具有从凸块下金属40的上表面测量的大于10μm的高度D3。在一些实施例中,柱25是通过合适的金属沉积操作形成的镍基材料,合适的金属沉积操作包括电镀或化学镀、包括溅射的物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、热蒸发或电子束蒸发。随后在操作S330中,在镍基层25上形成焊料层35,从而形成凸块结构55a。
应该理解,图16所示的器件经历进一步半导体工艺以形成诸如外部接触件、介电层、集成至模块等的各个部件。
图17是示出根据本发明的另一实施例的制造具有凸块结构55b的半导体器件10b的方法400的流程图。图18中示出了根据图17的方法400形成的半导体器件10b。图18是根据本发明的另一实施例的具有至少一个凸块结构55b的半导体器件10b的示意图。在操作S410中,在衬底15上方形成钛基层40a。在操作S420中,在钛基层40a上方沉积铜基层40b。因此,形成包括多个层40a、40b的凸块下金属40。在一些实施例中,通过溅射沉积钛基层40a和铜基层40b。在一些实施例中,钛基层40a的厚度为约5nm至约100nm。在其它实施例中,钛基层40a的厚度为约20nm至约70nm。在一些实施例中,铜基层40b的厚度为约5nm至约500nm。在其它实施例中,铜基层40b的厚度为约10nm至约100nm。在其它实施例中,铜基层40b的厚度为约20nm至约70nm。在实施例中,钛基层是溅射沉积的Ti或TiW层,其厚度在从约20nm至约70nm的范围内。
在操作S430中,在形成凸块下金属40之后,在凸块下金属40上方形成铜或铜合金层30。在一些实施例中,铜或铜合金层通过电镀或化学镀形成至从凸块下金属40的上表面测量的约5μm至约10μm的高度D4。在操作S440中,在铜或铜合金层30上方形成金属层以形成柱25,与铜或铜合金至焊料合金的可焊性相比,金属层具有至焊料合金的更低的可焊性,并且具有大于10μm的高度D5。在一些实施例中,柱25具有高达30μm的高度。在一些实施例中,柱25是通过本文先前公开的合适的金属沉积操作形成的镍基材料。随后在操作S450中,在柱25上形成焊料层35,从而形成凸块结构55b。
在一些实施例中,钛基层40a和铜基层40b覆盖接合焊盘20和衬底15的上表面,并且然后使用合适的光刻和蚀刻操作来图案化钛基层40a和铜基层40b,以在接合焊盘20上方形成多个凸块下金属40。然后围绕凸块下金属40形成绝缘层60。在一些实施例中,凸块下金属40以行-列布置而布置为具有约15μm至约60μm的间距。
在一些实施例中,形成与铜或铜合金至焊料合金的可焊性相比具有至焊料合金的更低的可焊性的金属层25包括:在衬底15和多个凸块下金属上方形成光刻胶层,光刻图案化光刻胶层以形成暴露多个凸块下金属的多个开口,在多个开口中沉积金属,在多个开口中的金属上方沉积焊料层,以及去除光刻胶层,与图5至图10B中公开的操作类似。
应该理解,图18所示的器件经历进一步半导体工艺以形成诸如外部接触件、介电层、集成至模块等的各个部件。
图19是示出根据本发明的另一实施例的制造半导体器件10c的另一方法500的流程图。如图20所示,半导体器件10c包括衬底15和设置在衬底15上的至少一个凸块结构55c。在操作S510中,在凸块下金属40上方形成铜或铜合金层30。在一些实施例中,铜或铜合金层形成为从凸块下金属40的上表面测量的约5μm至约10μm的高度D6。在操作S520中,在铜或铜合金层上方形成金属层以形成柱25,与铜或铜合金至焊料合金的可焊性相比,金属层具有至焊料合金的更低的可焊性,并且具有大于10μm的高度D7。在一些实施例中,柱25具有高达30μm的高度。在一些实施例中,柱25是通过本文先前公开的合适的金属沉积操作形成的镍基材料。接下来,在操作S530中,在柱25上方形成饰面层150。在操作S540中,在形成饰面层150之后,在饰面层150上方形成焊料层35,从而形成凸块结构55c。
在一些实施例中,饰面层150是金属层。饰面层150可以由镍形成,但是可以添加其它金属。在一些实施例中,饰面层150由化学镀镍化学镀钯浸金(ENEPIG)形成,饰面层150包括镍层、位于镍层上的钯层和位于钯层上的金层。金层可以使用浸镀形成。在其它实施例中,饰面层150由其它已知的饰面材料和方法形成,其它已知的饰面材料和方法包括但不限于化学镀镍浸金(ENIG)、直接浸金(DIG)等。在一些实施例中,饰面层基本不含铜。如本文使用的,基本不含铜意味着如果在饰面层中存在任何铜,则其仅以杂质水平存在。形成饰面层150的方法包括化学镀、浸渍等。饰面层150与下面的柱25形成大的界面区,从而改进柱25和焊料层35之间的接合。在一些实施例中,饰面层150的厚度在从约5nm至约100nm的范围内。
应该理解,图20所示的器件经历进一步半导体工艺以形成诸如外部接触件、介电层、集成至模块等的各个部件。
在接合工艺期间,焊料可以沿着柱(诸如铜柱)快速向下流动,同时在铜柱和焊料中的锡之间形成金属间化合物/合金。沿着柱快速向下流动可能在焊料接合件中产生空隙。对柱使用比铜或铜合金具有更低的可焊性(或润湿性)的金属减慢了金属间化合物的形成和焊料从柱的向下流动,从而抑制焊料接合件中空隙的形成。因为抑制了焊料沿着凸块结构的侧向下流动,所述焊料在焊接操作期间保留在焊点区中,从而防止在焊点中形成空隙。此外,由于比铜或铜合金具有更低的可焊性(或润湿性)的金属抑制了由于焊料沿着凸块结构的侧向下流动引起的焊料溢出和短路的形成问题。根据本发明的器件和方法改进了半导体器件的可靠性,特别是随着凸块结构的尺寸和间距减小。
应该理解,不是所有的优势都已经在此处讨论,没有特定的优势对所有实施例都是需要的,并且其它是实施例可以提供不同的优势。
本发明的实施例是半导体器件,半导体器件包括衬底和设置在衬底上方的至少一个凸块结构。至少一个凸块结构包括设置在衬底上方的由金属形成的柱,与铜或铜合金至焊料合金相比,该金属具有至焊料合金的更低的可焊性,并且焊料合金形成在金属的上表面正上方并且与金属的上表面接触,该金属比铜或铜合金具有更低的可焊性。该柱具有大于10μm的高度。在实施例中,半导体器件包括位于柱和衬底之间的铜或铜合金层,其中,柱的高度大于铜或铜合金层的高度。在实施例中,铜或铜合金层具有5μm至10μm的高度。在实施例中,柱的高度与铜或铜合金的高度的比率在1.5/1至6/1的范围。在实施例中,柱的高度与或铜或铜合金的高度的比率在3/1至5/1的范围。在实施例中,柱主要由选自铝、铬、铁、锰、镁、钼、镍、铌、钽、钛、钨、锌以及它们的合金组成的组的金属形成。在实施例中,柱的高度在从大于10μm至30μm的范围内。在实施例中,柱的直径在从5μm至40μm的范围内。在实施例中,柱的直径在从20μm至25μm的范围内。在实施例中,半导体器件包括设置在衬底和凸块结构之间的凸块下金属。在实施例中,多个凸块结构以行-列布置布置为具有在从15μm至60μm的范围的间距。
本公开的另一实施例是半导体器件,半导体器件包括第一衬底和第二衬底,该第一衬底包括第一电路。第一衬底通过包括设置在第一柱和第二柱之间的焊料层的连接件连接至第二衬底。第一柱由镍基材料形成并且具有大于10μm的高度。在实施例中,半导体器件包括设置在第一柱和衬底之间的铜或铜合金层,其中,第一柱的高度大于铜或铜合金层的高度。在实施例中,铜或铜合金层具有5μm至10μm的高度。在实施例中,第一柱的高度与铜或铜合金层的高度的比率在1.5/1至的6/1范围。在实施例中,第一柱或第二柱的直径在从5μm至40μm的范围。在实施例中,半导体器件包括位于第一柱和焊料层之间的基本不含铜的饰面层。
本发明的另一实施例是具有凸块结构的半导体器件,半导体器件包括衬底和设置在衬底上的至少一个凸块结构。至少一个凸块结构包括由镍基材料形成并且具有大于10μm的高度的柱,以及形成在柱的上表面正上方并且与柱的上表面接触的焊料合金。在实施例中,半导体器件包括位于柱和衬底之间的铜或铜合金层,其中,柱的高度与铜或铜合金层的高度的比率在1.5/1至6/1的范围。在实施例中,柱的高度在从大于10μm至30μm的范围。
本公开的另一实施例是制造半导体器件的方法,包括在衬底上方形成光刻胶层,以及图案化光刻胶层以形成暴露衬底的多个开口。在多个开口中沉积比铜或铜合金材料具有更低的可焊性的金属。在多个开口中的比铜或铜合金具有更低的可焊性的金属上方形成焊料层,以及去除光刻胶层。该焊料层与比铜或铜合金材料具有更低的可焊性的金属直接接触。在实施例中,该方法包括在多个开口中沉积比铜或铜合金具有更低的可焊性的金属层之前,在多个开口中沉积铜或铜合金材料,其中,比铜或铜合金材料具有更低的可焊性的金属的高度大于铜或铜合金材料的高度。在实施例中,该方法包括在衬底和比铜或铜合金材料具有更低的可焊性的金属之间形成钛基层。在实施例中,通过溅射形成钛基层。在实施例中,在钛基层上方形成溅射沉积的铜基层。在实施例中,该方法包括在溅射沉积的铜基层上电镀或化学镀铜或铜合金材料。在实施例中,相对于铜或铜合金与焊料合金相比具有更低的可焊性的金属具有大于10μm至30μm的高度。在实施例中,比铜或铜合金具有更低的可焊性的金属通过电镀或化学镀敷沉积在多个开口中。在实施例中,该方法包括:在衬底上方形成钛基层,在钛基层上方形成铜基层,以及蚀刻钛基层和铜基层以形成以行-列布置而布置为具有在从15μm至60μm的范围的间距的多个凸块下金属。
本公开的另一实施例是制造半导体器件的方法,包括图案化设置在第一衬底上方的光刻胶层以形成暴露第一衬底的部分的开口。在开口中沉积相对于铜或铜合金与焊料相比具有更低的可焊性的金属层。比铜或铜合金具有更低的可焊性的金属层具有大于10μm的高度。在比铜或铜合金具有更低的可焊性的金属层上方形成焊料层。去除光刻胶层,从而在第一衬底上形成多个第一凸块结构。第一衬底和具有多个第二凸块结构的第二衬底布置为使得第一凸块结构和第二凸块结构彼此相对并且彼此对准。使第一凸块结构和第二凸块结构彼此接触,并且对第一凸块结构和第二凸块结构施加能量,使得凸块结构上的焊料流动并且使第一凸块结构和第二凸块结构熔合在一起。在实施例中,该方法包括在开口中沉积铜或铜合金层,其中,比铜或铜合金具有更低的可焊性的金属层的高度大于铜或铜合金层的高度。在实施例中,能量是热能、超声能量或热能和超声能量的组合。在实施例中,在第一和第二凸块熔合在一起之后,第一衬底通过柱/焊料/柱连接件接合至第二衬底。在实施例中,比铜或铜合金具有更低的可焊性的金属主要由选自铝、铬、铁、锰、镁、钼、镍、铌、钽、钛、钨、锌以及它们的合金组成的组的金属形成。在实施例中,该方法包括在比铜或铜合金具有更低的可焊性的金属层和第一衬底之间形成厚度为约5μm至10μm的Cu层。
本发明的另一实施例是制造半导体器件的方法,包括在衬底上沉积钛基层。在钛基层上方沉积高度大于10μm的镍基层。在镍基层的上表面正上方形成与镍基层的上表面接触的焊料层。在实施例中,通过溅射沉积钛基层。在实施例中,该方法包括在钛基层上方溅射沉积铜基层。在实施例中,该方法包括在溅射沉积的铜基层上电镀或化学镀铜或铜合金层。在实施例中,镍基层的高度与铜或铜合金层的高度的比率在从1.5/1至6/1的范围。
根据本发明的一些实施例,提供了一种半导体器件,包括:衬底;以及至少一个凸块结构,设置在所述衬底上方,其中,所述至少一个凸块结构包括:柱,设置在所述衬底上方,由金属形成,与铜或铜合金至焊料合金的可焊性相比,所述金属具有至焊料合金的更低的可焊性;以及焊料合金,形成在比铜或铜合金具有更低的可焊性的所述金属的上表面正上方并且与所述金属的上表面接触;其中,所述柱具有大于10μm的高度。
在上述半导体器件中,还包括,位于所述柱和所述衬底之间的铜或铜合金层,其中,所述柱的高度大于所述铜或铜合金层的高度。
在上述半导体器件中,所述铜或铜合金层具有5μm至10μm的高度。
在上述半导体器件中,所述柱的高度与所述铜或铜合金层的高度的比率在1.5/1至6/1的范围内。
在上述半导体器件中,所述柱的高度与所述铜或铜合金层的高度的比率在3/1至5/1的范围内。
在上述半导体器件中,所述柱主要由选自铝、铬、铁、锰、镁、钼、镍、铌、钽、钛、钨、锌以及它们的合金的金属形成。
在上述半导体器件中,所述柱的高度大于10μm并且在从10μm至30μm的范围内。
在上述半导体器件中,所述柱的直径在从5μm至40μm的范围内。
在上述半导体器件中,所述柱的直径在从20μm至25μm的范围内。
在上述半导体器件中,还包括,设置在所述衬底和所述凸块结构之间的凸块下金属。
在上述半导体器件中,多个所述凸块结构布置为具有行-列布置且具有在从15μm至60μm的范围的间距。
根据本发明的另一些实施例,还提供了一种半导体器件,包括:第一衬底,包括第一电路;以及第二衬底;其中,所述第一衬底通过包括设置在第一柱和第二柱之间的焊料层的连接件连接至所述第二衬底,以及所述第一柱由镍基材料形成并且具有大于10μm的高度。
在上述半导体器件中,还包括,设置在所述第一柱和所述衬底之间的铜或铜合金层,其中,所述第一柱的高度大于所述铜或铜合金层的高度。
在上述半导体器件中,所述铜或铜合金层具有5μm至10μm的高度。
在上述半导体器件中,所述第一柱的高度与所述铜或铜合金层的高度的比率在1.5/1至6/1的范围内。
在上述半导体器件中,所述第一柱或所述第二柱的直径在从5μm至40μm的范围内。
在上述半导体器件中,还包括,位于所述第一柱和所述焊料层之间的不含铜的饰面层。
根据本发明的又一些实施例,还提供了一种制造半导体器件的方法,包括:在衬底上方形成光刻胶层;图案化所述光刻胶层以形成暴露所述衬底的多个开口;在所述多个开口中沉积比铜或铜合金材料具有更低的可焊性的金属;在所述多个开口中的所述金属上方形成焊料层,所述金属比所述铜或铜合金材料具有更低的可焊性;以及去除所述光刻胶层,其中,所述焊料层与比所述铜或铜合金材料具有更低的可焊性的金属直接接触。
在上述方法中,还包括,在所述多个开口中沉积比所述铜或铜合金具有更低的可焊性的所述金属之前,在所述多个开口中沉积铜或铜合金材料,其中,比所述铜或铜合金材料具有更低的可焊性的所述金属的高度大于所述铜或铜合金材料的高度。
在上述方法中,与所述铜或铜合金材料至焊料合金的可焊性相比,具有至焊料合金的更低的可焊性的所述金属具有大于10μm并且在从10μm至30μm的高度。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (20)
1.一种半导体器件,包括:
衬底;以及
至少一个凸块结构,设置在所述衬底上方,
其中,所述至少一个凸块结构包括:
柱,设置在所述衬底上方,由金属形成,与铜或铜合金至焊料合金的可焊性相比,所述金属具有至焊料合金的更低的可焊性;
焊料合金,形成在比铜或铜合金具有更低的可焊性的所述金属的上表面正上方并且与所述金属的上表面接触;和
铜或铜合金层,位于所述柱和所述衬底之间,其中,所述柱具有大于10μm的高度,并且所述柱的高度大于所述铜或铜合金层的高度。
2.根据权利要求1所述的半导体器件,其中,所述焊料合金包括共晶焊料且具有2μm至10μm的厚度。
3.根据权利要求1所述的半导体器件,其中,所述铜或铜合金层具有5μm至10μm的高度。
4.根据权利要求1所述的半导体器件,其中,所述柱的高度与所述铜或铜合金层的高度的比率在1.5/1至6/1的范围内。
5.根据权利要求1所述的半导体器件,其中,所述柱的高度与所述铜或铜合金层的高度的比率在3/1至5/1的范围内。
6.根据权利要求1所述的半导体器件,其中,所述柱主要由选自铝、铬、铁、锰、镁、钼、镍、铌、钽、钛、钨、锌以及它们的合金的金属形成。
7.根据权利要求1所述的半导体器件,其中,所述柱的高度大于10μm并且在从10μm至30μm的范围内。
8.根据权利要求1所述的半导体器件,其中,所述柱的直径在从5μm至40μm的范围内。
9.根据权利要求8所述的半导体器件,其中,所述柱的直径在从20μm至25μm的范围内。
10.根据权利要求1所述的半导体器件,还包括,设置在所述衬底和所述凸块结构之间的凸块下金属。
11.根据权利要求1所述的半导体器件,其中,多个所述凸块结构布置为具有行-列布置且具有在从15μm至60μm的范围的间距。
12.一种半导体器件,包括:
第一衬底,包括第一电路;第二
衬底;以及
设置在第一柱和所述第一衬底之间的铜或铜合金层,
其中,所述第一衬底通过包括设置在第一柱和第二柱之间的焊料层的连接件连接至所述第二衬底,以及所述第一柱由镍基材料形成并且具有大于10μm的高度,所述第一柱的高度大于所述铜或铜合金层的高度。
13.根据权利要求12所述的半导体器件,其中,所述焊料层包括共晶焊料且具有2μm至10μm的厚度。
14.根据权利要求12所述的半导体器件,其中,所述铜或铜合金层具有5μm至10μm的高度。
15.根据权利要求12所述的半导体器件,其中,所述第一柱的高度与所述铜或铜合金层的高度的比率在1.5/1至6/1的范围内。
16.根据权利要求12所述的半导体器件,其中,所述第一柱或所述第二柱的直径在从5μm至40μm的范围内。
17.根据权利要求12所述的半导体器件,还包括,位于所述第一柱和所述焊料层之间的不含铜的饰面层。
18.一种制造半导体器件的方法,包括:
在衬底上方形成光刻胶层;
图案化所述光刻胶层以形成暴露所述衬底的多个开口;
在所述多个开口中沉积铜或铜合金材料;
在所述多个开口中的所述铜或铜合金材料上沉积比所述铜或铜合金材料具有更低的可焊性的金属;
在所述多个开口中的所述金属上方形成焊料层,所述金属比所述铜或铜合金材料具有更低的可焊性;以及
去除所述光刻胶层,
其中,所述焊料层与比所述铜或铜合金材料具有更低的可焊性的金属直接接触,比所述铜或铜合金材料具有更低的可焊性的所述金属的高度大于所述铜或铜合金材料的高度。
19.根据权利要求18所述的方法,其中,所述焊料层包括共晶焊料且具有2μm至10μm的厚度。
20.根据权利要求18所述的方法,其中,与所述铜或铜合金材料至焊料合金的可焊性相比,具有至焊料合金的更低的可焊性的所述金属具有大于10μm并且在从10μm至30μm的高度。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762591534P | 2017-11-28 | 2017-11-28 | |
US62/591,534 | 2017-11-28 | ||
US16/169,753 | 2018-10-24 | ||
US16/169,753 US11127704B2 (en) | 2017-11-28 | 2018-10-24 | Semiconductor device with bump structure and method of making semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109979903A CN109979903A (zh) | 2019-07-05 |
CN109979903B true CN109979903B (zh) | 2021-07-13 |
Family
ID=66442205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811426233.2A Active CN109979903B (zh) | 2017-11-28 | 2018-11-27 | 具有凸块结构的半导体器件和制造半导体器件的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11127704B2 (zh) |
KR (3) | KR20190062268A (zh) |
CN (1) | CN109979903B (zh) |
DE (1) | DE102018127167A1 (zh) |
TW (1) | TWI720371B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10756162B2 (en) * | 2018-08-31 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with magnetic element |
JP7319808B2 (ja) * | 2019-03-29 | 2023-08-02 | ローム株式会社 | 半導体装置および半導体パッケージ |
KR20210024869A (ko) * | 2019-08-26 | 2021-03-08 | 삼성전자주식회사 | 반도체 칩 적층 구조, 반도체 패키지 및 이들의 제조 방법 |
DE102021105572A1 (de) * | 2020-03-31 | 2021-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mikroelektromechanisches system und verfahren zu seiner herstellung |
US11502056B2 (en) | 2020-07-08 | 2022-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Joint structure in semiconductor package and manufacturing method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004510351A (ja) * | 2000-09-29 | 2004-04-02 | エリプシズ リミテッド | ハンダ継手用障壁層の形成方法 |
CN102315182A (zh) * | 2010-07-08 | 2012-01-11 | 台湾积体电路制造股份有限公司 | 半导体芯片及其制造方法 |
CN103779297A (zh) * | 2012-10-22 | 2014-05-07 | 台湾积体电路制造股份有限公司 | 金属凸块接合结构 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG107600A1 (en) * | 2002-06-27 | 2004-12-29 | Agency Science Tech & Res | Multilayer substrate metallization for ic interconnection |
TWI378540B (en) * | 2006-10-14 | 2012-12-01 | Advanpack Solutions Pte Ltd | Chip and manufacturing method thereof |
US8269345B2 (en) | 2007-10-11 | 2012-09-18 | Maxim Integrated Products, Inc. | Bump I/O contact for semiconductor device |
US20090108443A1 (en) | 2007-10-30 | 2009-04-30 | Monolithic Power Systems, Inc. | Flip-Chip Interconnect Structure |
KR101037832B1 (ko) | 2008-05-09 | 2011-05-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US8659155B2 (en) * | 2009-11-05 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps |
US8637392B2 (en) | 2010-02-05 | 2014-01-28 | International Business Machines Corporation | Solder interconnect with non-wettable sidewall pillars and methods of manufacture |
US8492891B2 (en) | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
US8901736B2 (en) | 2010-05-28 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strength of micro-bump joints |
US8232193B2 (en) | 2010-07-08 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming Cu pillar capped by barrier layer |
US8405199B2 (en) * | 2010-07-08 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pillar for semiconductor substrate and method of manufacture |
KR20120056051A (ko) * | 2010-11-24 | 2012-06-01 | 삼성전자주식회사 | 반도체 패키지의 제조 방법 및 반도체 패키지 |
CN103515341B (zh) * | 2012-06-20 | 2016-12-21 | 讯忆科技股份有限公司 | 晶圆焊垫的化镀镍凸块结构及其制造方法 |
JP6015240B2 (ja) * | 2012-08-24 | 2016-10-26 | Tdk株式会社 | 端子構造及び半導体素子 |
US8970035B2 (en) * | 2012-08-31 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures for semiconductor package |
KR101416596B1 (ko) | 2012-09-04 | 2014-07-08 | 에스티에스반도체통신 주식회사 | 반도체 패키지 및 그 제조방법 |
JP5592459B2 (ja) | 2012-11-07 | 2014-09-17 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
US9299680B2 (en) | 2013-03-14 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure having dies with connectors |
US8957524B2 (en) * | 2013-03-15 | 2015-02-17 | Globalfoundries Inc. | Pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure |
US9559071B2 (en) * | 2013-06-26 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming hybrid bonding structures with elongated bumps |
US9147661B1 (en) | 2014-02-03 | 2015-09-29 | Xilinx, Inc. | Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same |
US20150262949A1 (en) * | 2014-03-14 | 2015-09-17 | Lsi Corporation | Method for Fabricating Equal Height Metal Pillars of Different Diameters |
US9520370B2 (en) | 2014-05-20 | 2016-12-13 | Micron Technology, Inc. | Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures |
US9875980B2 (en) | 2014-05-23 | 2018-01-23 | Amkor Technology, Inc. | Copper pillar sidewall protection |
JP2015226046A (ja) | 2014-05-30 | 2015-12-14 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、電子機器 |
TWI488244B (zh) | 2014-07-25 | 2015-06-11 | Chipbond Technology Corp | 具有凸塊結構的基板及其製造方法 |
KR20160061236A (ko) * | 2014-11-20 | 2016-05-31 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
JP2016225466A (ja) * | 2015-05-29 | 2016-12-28 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
US9806052B2 (en) | 2015-09-15 | 2017-10-31 | Qualcomm Incorporated | Semiconductor package interconnect |
-
2018
- 2018-10-24 US US16/169,753 patent/US11127704B2/en active Active
- 2018-10-31 DE DE102018127167.0A patent/DE102018127167A1/de active Granted
- 2018-11-27 KR KR1020180148358A patent/KR20190062268A/ko active Application Filing
- 2018-11-27 TW TW107142209A patent/TWI720371B/zh active
- 2018-11-27 CN CN201811426233.2A patent/CN109979903B/zh active Active
-
2021
- 2021-07-27 KR KR1020210098706A patent/KR20210096044A/ko active Application Filing
-
2022
- 2022-10-20 KR KR1020220135497A patent/KR102650296B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004510351A (ja) * | 2000-09-29 | 2004-04-02 | エリプシズ リミテッド | ハンダ継手用障壁層の形成方法 |
CN102315182A (zh) * | 2010-07-08 | 2012-01-11 | 台湾积体电路制造股份有限公司 | 半导体芯片及其制造方法 |
CN103779297A (zh) * | 2012-10-22 | 2014-05-07 | 台湾积体电路制造股份有限公司 | 金属凸块接合结构 |
Also Published As
Publication number | Publication date |
---|---|
KR20210096044A (ko) | 2021-08-04 |
DE102018127167A1 (de) | 2019-05-29 |
KR20190062268A (ko) | 2019-06-05 |
KR20220147562A (ko) | 2022-11-03 |
TW201926563A (zh) | 2019-07-01 |
KR102650296B1 (ko) | 2024-03-21 |
US20190164920A1 (en) | 2019-05-30 |
US11127704B2 (en) | 2021-09-21 |
TWI720371B (zh) | 2021-03-01 |
CN109979903A (zh) | 2019-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109979903B (zh) | 具有凸块结构的半导体器件和制造半导体器件的方法 | |
US10290600B2 (en) | Dummy flip chip bumps for reducing stress | |
TWI423357B (zh) | 積體電路元件的形成方法 | |
US6417089B1 (en) | Method of forming solder bumps with reduced undercutting of under bump metallurgy (UBM) | |
CN104269390B (zh) | 半导体组件及制造半导体组件的方法 | |
US7932169B2 (en) | Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers | |
TWI498978B (zh) | 在半導體封裝中有內部中心柱的焊接凸塊 | |
TWI440106B (zh) | 倒裝晶片互連結構 | |
EP1387402A2 (en) | Wafer-level method for fine-pitch, high aspect ratio chip interconnect | |
Koh et al. | Copper pillar bump technology progress overview | |
US7112522B1 (en) | Method to increase bump height and achieve robust bump structure | |
US20080099925A1 (en) | Solder pillar bumping and a method of making the same | |
US20070087544A1 (en) | Method for forming improved bump structure | |
KR20120045005A (ko) | 수직 필라 상호 접속 방법 및 구조체 | |
TWI512927B (zh) | 具有晶圓級封裝之自對準結構的半導體裝置與其製造方法 | |
WO2013192054A1 (en) | Semiconductor chip with expansive underbump metallization structures | |
JP2009147220A (ja) | 半導体装置の製造方法及び半導体装置 | |
TWI713170B (zh) | 半導體封裝結構及其製作方法 | |
CN101194361A (zh) | 层序列及制造层序列的方法 | |
EP2075834A1 (en) | Solder bumps for flip chip bonding with higher density | |
KR101758999B1 (ko) | 반도체 디바이스 및 그 제조 방법 | |
CN112420534B (zh) | 形成半导体封装件的方法及半导体封装件 | |
US20240047397A1 (en) | Bump structure and method of making the same | |
TWI837728B (zh) | 半導體裝置及其製造方法 | |
US20240113060A1 (en) | Heterogeneous solder bump structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |