CN112420534B - 形成半导体封装件的方法及半导体封装件 - Google Patents

形成半导体封装件的方法及半导体封装件 Download PDF

Info

Publication number
CN112420534B
CN112420534B CN202011359779.8A CN202011359779A CN112420534B CN 112420534 B CN112420534 B CN 112420534B CN 202011359779 A CN202011359779 A CN 202011359779A CN 112420534 B CN112420534 B CN 112420534B
Authority
CN
China
Prior art keywords
layer
metal
forming
photoresist layer
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011359779.8A
Other languages
English (en)
Other versions
CN112420534A (zh
Inventor
李维平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Yibu Semiconductor Co ltd
Original Assignee
Shanghai Yibu Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Yibu Semiconductor Co ltd filed Critical Shanghai Yibu Semiconductor Co ltd
Priority to CN202011359779.8A priority Critical patent/CN112420534B/zh
Publication of CN112420534A publication Critical patent/CN112420534A/zh
Application granted granted Critical
Publication of CN112420534B publication Critical patent/CN112420534B/zh
Priority to KR1020210164048A priority patent/KR20220074765A/ko
Priority to US17/535,988 priority patent/US20220173063A1/en
Priority to TW110144183A priority patent/TW202221803A/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03901—Methods of manufacturing bonding areas involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/03902—Multiple masking steps
    • H01L2224/03903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H01L2224/11622—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13311—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供了形成半导体封装件的方法及半导体封装件，方法包括：提供半导体器件，半导体器件至少包括：半导体晶圆和位于半导体晶圆上方的至少两个金属焊盘；在半导体器件的上方形成晶种层；在晶种层的上方形成第一光刻胶层；在第一光刻胶层中形成第一开口，其中，第一开口位于第一金属焊盘的至少一部分的正上方；在第一开口中形成第一高度的第一金属部件；去除第一光刻胶层；在晶种层之上形成第二光刻胶层；在第二光刻胶层中形成第二开口，其中，第二开口位于第二金属焊盘的至少一部分的正上方；在第二开口中形成第二高度的第二金属部件；去除第二光刻胶层。利用上述方法，能够对不同尺寸的金属凸块进行高度控制。

Description

形成半导体封装件的方法及半导体封装件
技术领域
本发明属于半导体领域，具体涉及形成半导体封装件的方法及半导体封装件。
背景技术
本部分旨在为权利要求书中陈述的本发明的实施方式提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
在半导体封装领域，晶圆凸块(wafer bumping)通常形成为统一尺寸，这是因为在同一晶圆上难以对不同尺寸凸块的高度进行控制，在电镀工艺中大尺寸凸块通常比小尺寸凸块镀得更快，造成凸块高度的不均匀，影响芯片良品率。
发明内容
针对上述现有技术中存在的问题，提出了形成半导体封装件的方法及半导体封装件，利用这种方法及封装件，能够解决上述问题。
本发明提供了以下方案。
第一方面，提供一种形成半导体封装件的方法，包括：提供半导体器件，半导体器件至少包括：半导体晶圆和位于半导体晶圆上方的至少两个金属焊盘；在半导体器件的上方形成晶种层，晶种层与每个金属焊盘电连接；在晶种层的上方形成第一光刻胶层；在第一光刻胶层中形成第一开口以暴露晶种层，其中，第一开口位于至少两个金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；在第一开口中形成第一高度的第一金属部件；去除第一光刻胶层；去除第一光刻胶层之后，在晶种层之上形成第二光刻胶层；在第二光刻胶层中形成第二开口以暴露晶种层，其中，第二开口位于至少两个金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方；在第二开口中形成第二高度的第二金属部件；去除第二光刻胶层。
在一些实施例中，方法还包括：在半导体晶圆和至少两个金属焊盘的上方形成图案化的钝化层，钝化层将每个金属焊盘的至少一部分暴露出来；晶种层至少覆盖在每个金属焊盘的暴露表面。
在一些实施例中，形成图案化的钝化层之后，方法还包括：在钝化层的表面形成聚合物层。
在一些实施例中，方法还包括：在聚合物层和至少两个金属焊盘的暴露表面上溅射金属材料以形成晶种层；以及，在去除第二光刻胶层之后，蚀刻去除晶种层的曝光部分。
在一些实施例中，方法还包括：在晶种层上方沉淀第一厚度的第一光刻胶层，在第一光刻胶层上方放置用于图案化第一光刻胶层的第一掩模层以形成第一开口；以及，去除第一光刻胶层之后，在晶种层上方沉淀第二厚度的第二光刻胶层，在第二光刻胶层上方放置用于图案化第二光刻胶层的第二掩模层以形成第二开口。
在一些实施例中，还包括：在去除第一光刻胶层之后，在晶种层的上方形成完全覆盖第一金属部件的第二光刻胶层。
在一些实施例中，第一金属部件和第二金属部件的粗细度不同。
在一些实施例中，第一金属部件和第二金属部件均为凸块下金属。
第二方面，提供一种半导体封装件，包括：利用如第一方面的方法封装得到的半导体封装件。
第三方面，提供一种半导体封装件，包括：半导体器件，其至少包括：半导体晶圆和位于半导体晶圆上方的至少两个金属焊盘；晶种层，形成在半导体器件的上方表面且与每个金属焊盘电连接；第一金属部件，其具有第一高度，形成在晶种层的上方且位于至少两个金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；第二金属部件，其具有第二高度，形成在晶种层的上方且位于至少两个金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方。
在一些实施例中，还包括：钝化层，形成在半导体晶圆和至少两个金属焊盘的上方，其中，钝化层中的图案化开口将每个金属焊盘的至少一部分暴露出来；晶种层至少覆盖在每个金属焊盘的暴露表面。
在一些实施例中，还包括：形成在钝化层的表面的聚合物层。
在一些实施例中，第一金属部件和第二金属部件的粗细度不同。
在一些实施例中，第一高度小于第二高度。
在一些实施例中，第一金属部件和第二金属部件均为凸块下金属。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果：通过上述封装方法，针对半导体晶圆上的不同尺寸的多个金属部件，实现了可控制的凸块高度，对于在同一封装中需实现高密度互连布线的ASIC和小型芯片而言非常有价值。
应当理解，上述说明仅是本发明技术方案的概述，以便能够更清楚地了解本发明的技术手段，从而可依照说明书的内容予以实施。为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举例说明本发明的具体实施方式。
附图说明
通过阅读下文的示例性实施例的详细描述，本领域普通技术人员将明白本文所述的优点和益处以及其他优点和益处。附图仅用于示出示例性实施例的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的标号表示相同的部件。在附图中：
图1为根据本发明一实施例的形成半导体封装件的方法的流程示意图；
图2至图11为根据本发明一实施例在形成封装件的过程中的中间阶段的截面示意图。
在附图中，相同或对应的标号表示相同或对应的部分。
附图标记：半导体晶圆(Semiconductor wafer)-20，第一金属焊盘(The firstmetal pad)-31,第二金属焊盘(The second metal pad)-32,钝化层(Passivationlayer)-41，聚合物层(Polymer layer)-42,晶种层(Seed layer)-43，第一光刻胶层(Thefirst photo resist layer)-51，第一掩模层(The first mask layer)-52，第一开口(Thefirst opening)-53，第一凸块下金属(The first UBM)-61，第二凸块下金属(The secondUBM)-62，第二光刻胶层(The second photo resist layer)-71，第二掩模层(The secondmask layer)-72，第二开口(The second opening)-73，铜柱(Cu pillar)-611、621，镍层(Ni layer)-612、622，膏状软钎焊料-613、623
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
应理解，诸如“包括”或“具有”等术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不旨在排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在的可能性。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据本发明的一些实施例，提供了一种技术方案来解决技术问题。该技术问题具体涉及：通常而言，晶圆凸块(wafer bumping)形成为具有统一尺寸，凸块间距可以进行调整变化，但凸块的尺寸通常固定为一个值，这是由于大尺寸凸块在电镀过程中往往比小尺寸凸块镀得更快，进而造成凸块高度的不均匀，芯片良品率降低。换言之，在同一晶圆上的不同尺寸凸块的凸块高度难以控制。本公开实施例目的在于解决这种不同尺寸的金属凸块的高度控制问题。
另外还需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。
图1是示出根据本发明一些实施例的形成半导体封装件的方法的流程图。图2至图11分别是示意性地示出根据本一些实施例的形成半导体封装件的各个中间阶段的结构横截面示意图。以下参考图1以及图2至图11描述本发明实施例的半导体封装件的制造过程。
参考图1，形成半导体封装件的方法可以包括步骤101～110：
在步骤101，提供半导体器件；
其中，半导体器件至少包括：半导体晶圆20和位于半导体晶圆20之上的至少两个金属焊盘，比如，图2示出的第一金属焊盘31和第二金属焊盘32；
参考图2，上述半导体器件的形成步骤可以包括：提供半导体晶圆20；其中，半导体晶圆20例如可以是硅晶圆(Si wafer)。将至少两个金属焊盘耦合至半导体晶圆20之上；金属焊盘可以使用包括铜、铝、银、金、钛、其任何组合或者本领域中已知的任何其他适当材料；金属焊盘之间的尺寸可以彼此不同，比如可以是尺寸较小的第一金属焊盘3 1和尺寸较大的第二金属焊盘32，可以将尺寸不同的两个金属焊盘以一定的间距设置在硅晶圆之上，金属焊盘彼此之间互不接触。
在一些实施例中，上述半导体器件的形成步骤可以还包括：在半导体晶圆20和至少两个金属焊盘的上方形成图案化的钝化层41，钝化层41将每个金属焊盘的至少一部分暴露出来。其中，钝化层41覆盖半导体晶圆20的一部分和每个金属焊盘的一部分。参考图2，可以在半导体晶圆20的上方形成钝化层41，该钝化层41覆盖第一金属焊盘31和第二金属焊盘32的边缘部分，该钝化层41中形成的图案化开口将每个金属焊盘的中心部分暴露出来。钝化层41可以使用包括SiO2,SiNx，磷硅玻璃(PSG)或本领域中已知的适应于在芯片表面进行钝化处理的任何适当材料。根据一些实施例，图案化的钝化层41在每个金属焊盘的上方形成第三开口(未示出)。
在一些实施例中，可以在钝化层41的上方表面和侧表面形成聚合物层42。聚合物层42可以包括光敏由诸如聚酰亚胺(PI)、聚苯并恶唑(PBO)、苯并环丁烯(BCB)或其任何组合或者本领域中已知的任何其他适当材料等的聚合物形成。聚合物层42可以耦合到钝化层4110并且与第一金属焊盘31、第二金属焊盘32接触。具有覆盖聚合物层42的钝化层41的集电成路芯片具有很低的漏电流、较强的机械性能以及耐化学腐蚀性能。同时，也可有效地遮挡潮气，增加元器件的抗潮湿能力，从而改善了芯片的电学性能，降低了生产成本。参考图3，可以在钝化层41的暴露表面覆盖聚合物层42，聚合物层42延伸至钝化层41在金属焊盘处形成的开口中，并使每个金属焊盘的中心部分保持暴露状态。
在步骤102，在半导体器件的上方形成晶种层43。其中，晶种层43与每个金属焊盘电连接，
根据本发明的一些实施例，晶种层43是包括多个层的复合层。例如，该晶种层43可以包括处于下层的钛层和处于上层的铜层，由此可以分别与每个金属焊盘电连接。根据可选实施例，晶种层43也可以是单层，例如，其可以是铜层。可以理解，该晶种层43还可以使用其他合适的导电材料。
参考图4，可以在聚合物层42和两个金属焊盘的暴露表面上溅射金属材料以形成晶种层43，该晶种层43可包括处于下层的钛层和处于上层的铜层。应当理解，在后续的封装步骤中需要将晶种层43的暴露表面蚀刻去除，以避免发生电路故障，具体将在步骤110之后描述。
在步骤103，在晶种层43的上方形成第一光刻胶层51。
在步骤104，在第一光刻胶层51中形成第一开口53以暴露晶种层43。
其中，第一开口53位于第一金属焊盘31的至少一部分的正上方。
在一些实施例中，参考图5，可以在晶种层43上方沉淀第一厚度的第一光刻胶层51，在第一光刻胶层51上方放置用于图案化第一光刻胶层51的第一掩模层52，以形成第一开口53，具体而言，可以在提供的半导体器件和晶种层43的上方铺满光刻胶，以形成第一厚度的第一光刻胶层51，可以依据所需的设置在第一金属焊盘31之上的金属部件的高度尺寸确定该第一厚度。接下来将第一掩模层52放置在第一光刻胶层51上方。第一掩模层52可以是光刻掩模，其包括允许光通过的透明部分，以及用于阻挡光通过的不透明部分，光束投射在第一掩模层52上，从而曝光第一光刻胶层51位于透明部分正下方的部分，并且未曝光第一光刻胶层51位于不透明部分正下方的其它部分，从而形成该第一开口53。可以依据所需的第一金属焊盘31的凸块下金属(UBM)的底部尺寸确定第一开口53的开口面积。
在步骤105，在第一开口53中形成第一高度的第一金属部件；
在一些实施例中，参考图6，该第一金属部件可以为第一凸块下金属(Under-bumpmetal，简称UBM)61。在诸如晶圆级封装(WLP)的传统封装技术中、再分布层(RDL)可以形成在半导体晶圆上方并电连接至半导体晶圆中的有源器件。然后可以形成诸如位于凸块下金属(UBM)上的焊料球的外部输入/输出(I/O)焊盘(pad)，以通过再分布层(RDL)电连接至半导体晶圆。可选地，该第一金属部件还可以为其它用于提供芯片电气互连的金属接口。本实施例以凸块下金属为例进行描述，本申请对此不作具体限制。
参考图6，在晶种层43的上方且在第一开口53中形成第一高度的第一凸块下金属61,通常情况下，实施电镀工艺在该第一开口53中填满金属材料以形成该第一凸块下金属61。换言之，该第一高度大致等同于第一光刻胶层51在第三开口处的第一厚度。第一凸块下金属61的底部通过晶种层43与第一金属焊盘31电连接。根据本发明的一些实施例，第一凸块下金属61的形成步骤具体可以包括：在晶种层43之上且在该第一开口53中电镀形成含铜(Cu)层，含铜(Cu)层例如可以为铜柱611，在该含铜(Cu)层的上方形成含镍(Ni)层612，在该含镍(Ni)层612的上方形成膏状软钎焊料613，具体可以为锡银化合物层(例如SnAg1.8％)。
在步骤106，去除第一光刻胶层51；例如，可以在光刻胶剥离工艺中去除第一光刻胶层51，并且产生的结构如图7所示。
在步骤107，去除第一光刻胶层51之后，在晶种层43的上方形成第二光刻胶层71。
在一些实施例中，参考图8，在去除第一光刻胶层51之后，在晶种层43的上方形成完全覆盖第一金属部件的第二光刻胶层71，在图示中该第一金属部件为第一凸块下金属61。在这种情况下，第二光刻胶层71比该第一凸块下金属61更高，因此其被光刻胶覆盖并保护。
在步骤108，在第二光刻胶层71中形成第二开口73以暴露晶种层43。
其中，参考图8，第二开口73位于第二金属焊盘32的至少一部分的正上方。
在一些实施例中，参考图8，与第一开口53的形成工艺相同或相似，去除第一光刻胶层51之后，在晶种层43上方沉淀第二厚度的第二光刻胶层71，在第二光刻胶层71上方放置用于图案化第二光刻胶层71的第二掩模层72以形成第二开口73。具体而言，去除第一光刻胶层51之后，再次在晶种层43之上铺满光刻胶以形成第二厚度的第二光刻胶层71，可以依据所需的设置在第二金属焊盘32之上的第二金属部件的高度尺寸确定该第二厚度。接下来将第二掩模层72放置在第二光刻胶层71上方。第二掩模层72同样可以是光刻掩模，其包括允许光通过的透明部分，以及用于阻挡光通过的不透明部分，该透明部分可以设置在第二金属焊盘32的至少部分的正上方，光束投射在第二掩模层72上，从而曝光第二光刻胶层71位于透明部分正下方的部分，也即大致位于第二金属焊盘32正上方的晶种层43，并且未曝光第二光刻胶层71位于不透明部分正下方的其它部分，从而形成该第二开口73。可以依据所需的第二金属焊盘32上的第二金属部件的底部尺寸自由确定第二开口73的开口面积。
在步骤109，在第二开口73中形成第二高度的第二金属部件；
在一些实施例中，参考图9，该第二金属部件可以为第二凸块下金属62。可选地，该第二金属部件还可以为其它用于提供芯片电气互连的金属接口。本实施例以凸块下金属为例进行描述，本申请对此不作具体限制。
参考图9，与第一凸块下金属62的形成工艺相同或相似，接下来在晶种层的上方且第二开口73中形成第二高度的第二凸块下金属62,通常情况下，实施电镀工艺在该第二开口73中填满金属材料以形成该第二凸块下金属62。换言之，该第二高度大致等同于第二光刻胶层71在第三开口处的第二厚度。第二凸块下金属62的底部通过晶种层43与第二金属焊盘32电连接。根据本发明的二些实施例，第二凸块下金属62的形成步骤具体可以包括：在晶种层43之上且在该第二开口73中电镀形成含铜(Cu)层621，含铜(Cu)层例如可以为铜柱，在该含铜(Cu)层621的上方形成含镍(Ni)层622，在该含镍(Ni)层622的上方形成膏状软钎焊料613，具体可以为锡银化合物层(例如SnAg1.8％)，例如SnAg1.8％。
在步骤110，去除第二光刻胶层71。例如，与第一光刻胶层51的去除工艺相同或相似，可以在光刻胶剥离工艺中去除第二光刻胶层71，并且产生的结构如图10所示。
在一些实施例中，参考图11，接下来通过蚀刻去除晶种层43的先前由光刻胶覆盖的曝光部分，同时保留晶种层43的由第一凸块下金属61和第二凸块下金属62覆盖的未曝光部分。
通过回流(reflow)焊工艺，重新熔化预先分配到金属焊盘顶部的膏状软钎焊料613和623，通过融化材料的液体表面张力产生如图11所示的结构，最终形成焊料凸点。
可以理解，如果尺寸较大的第二金属焊盘32希望具有较低的金属部件的高度，可以对上述部分步骤进行颠倒，也即先打开第二金属焊盘32处的掩模开口以形成第二金属焊盘32上的第二金属部件(在图示中为第二凸块下金属62)，而后打开第一金属焊盘31处的掩模开口以形成第一金属焊盘31上的第一金属部件(在图示中为第一凸块下金属61)，此处不再赘述。
上述实施例对单个的第一金属部件和第二金属部件的情况进行了详细描述。应当理解，基于上述封装方法的精神，可以封装得到其中包括尺寸、高度均不同的多个第一金属部件和第二金属部件的半导体封装件。在另外的实施例中，可以形成两种以上的尺寸、高度不同的金属部件，在此不再赘述。
根据以上实施例的各个方面，通过采用了新的封装结构设计和独特的工艺流程，能够在晶圆上形成多种尺寸不同、且凸点高度受控制的晶圆凸点，这对于使用同一封装中的高密度互连布线的ASIC裸芯片和小型芯片的集成而言非常有价值。
本发明还提供了一种封装件，其采用如上述实施例的方法制造成形。
参考图10，本发明还提供了一种封装件，其包括：第三方面，提供一种半导体封装件，包括：半导体器件，其至少包括：半导体晶圆和位于半导体晶圆上方的至少两个金属焊盘；晶种层，形成在半导体器件的上方表面且与每个金属焊盘电连接；第一金属部件，其具有第一高度，形成在晶种层的上方且位于至少两个金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；第二金属部件，其具有第二高度，形成在晶种层的上方且位于至少两个金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方。
在一些实施例中，还包括：钝化层，形成在半导体晶圆和至少两个金属焊盘的上方，其中，钝化层中的图案化开口将每个金属焊盘的至少一部分暴露出来；晶种层至少覆盖在每个金属焊盘的暴露表面。
在一些实施例中，还包括：形成在钝化层的表面的聚合物层。
在一些实施例中，第一金属部件和第二金属部件的粗细度不同。
在一些实施例中，第一高度小于第二高度。
在一些实施例中，第一金属部件和第二金属部件为凸块下金属。
虽然已经参考若干具体实施方式描述了本发明的精神和原理，但是应该理解，本发明并不限于所公开的具体实施方式，对各方面的划分也不意味着这些方面中的特征不能组合以进行受益，这种划分仅是为了表述的方便。本发明旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。

Claims (8)

1.一种形成半导体封装件的方法，其特征在于，包括：
提供半导体器件，所述半导体器件至少包括：半导体晶圆和位于所述半导体晶圆上方的至少两个金属焊盘；
在所述半导体器件的上方形成晶种层，所述晶种层与每个所述金属焊盘电连接；
在所述晶种层的上方形成第一光刻胶层；在所述第一光刻胶层中形成第一开口以暴露所述晶种层，其中，所述第一开口位于所述至少两个金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；在所述第一开口中形成第一高度的第一金属部件；去除所述第一光刻胶层；
去除所述第一光刻胶层之后，在所述晶种层之上形成第二光刻胶层；在所述第二光刻胶层中形成第二开口以暴露所述晶种层，其中，所述第二开口位于所述至少两个金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方；在所述第二开口中形成第二高度的第二金属部件，所述第二高度不同于所述第一高度；去除所述第二光刻胶层。
2.根据权利要求1所述的方法，其特征在于，所述方法还包括：
在所述半导体晶圆和所述至少两个金属焊盘的上方形成图案化的钝化层，所述钝化层将每个所述金属焊盘的至少一部分暴露出来；
所述晶种层至少覆盖在每个所述金属焊盘的暴露表面。
3.根据权利要求2所述的方法，其特征在于，形成图案化的钝化层之后，所述方法还包括：在所述钝化层的表面形成聚合物层。
4.根据权利要求3所述的方法，其特征在于，所述方法还包括：
在所述聚合物层和所述至少两个金属焊盘的暴露表面上溅射金属材料以形成所述晶种层；以及，
在去除所述第二光刻胶层之后，蚀刻去除所述晶种层的曝光部分。
5.根据权利要求1所述的方法，其特征在于，所述方法还包括：
在所述晶种层上方沉淀第一厚度的所述第一光刻胶层，在所述第一光刻胶层上方放置用于图案化所述第一光刻胶层的第一掩模层以形成所述第一开口；以及，
去除所述第一光刻胶层之后，在所述晶种层上方沉淀第二厚度的所述第二光刻胶层，在所述第二光刻胶层上方放置用于图案化所述第二光刻胶层的第二掩模层以形成所述第二开口。
6.根据权利要求1所述的方法，其特征在于，还包括：
在所述去除所述第一光刻胶层之后，在所述晶种层的上方形成完全覆盖所述第一金属部件的所述第二光刻胶层。
7.根据权利要求1所述的方法，其特征在于，所述第一金属部件和所述第二金属部件的粗细度不同。
8.根据权利要求1所述的方法，其特征在于，所述第一金属部件和所述第二金属部件均为凸块下金属。
CN202011359779.8A 2020-11-27 2020-11-27 形成半导体封装件的方法及半导体封装件 Active CN112420534B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202011359779.8A CN112420534B (zh) 2020-11-27 2020-11-27 形成半导体封装件的方法及半导体封装件
KR1020210164048A KR20220074765A (ko) 2020-11-27 2021-11-25 반도체 패키지 형성 방법 및 반도체 패키지
US17/535,988 US20220173063A1 (en) 2020-11-27 2021-11-26 Method for Forming Semiconductor Package and Semiconductor Package
TW110144183A TW202221803A (zh) 2020-11-27 2021-11-26 形成半導體封裝件的方法及半導體封裝件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011359779.8A CN112420534B (zh) 2020-11-27 2020-11-27 形成半导体封装件的方法及半导体封装件

Publications (2)

Publication Number Publication Date
CN112420534A CN112420534A (zh) 2021-02-26
CN112420534B true CN112420534B (zh) 2021-11-23

Family

ID=74842938

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011359779.8A Active CN112420534B (zh) 2020-11-27 2020-11-27 形成半导体封装件的方法及半导体封装件

Country Status (4)

Country Link
US (1) US20220173063A1 (zh)
KR (1) KR20220074765A (zh)
CN (1) CN112420534B (zh)
TW (1) TW202221803A (zh)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
US8836146B2 (en) * 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same
TW201023314A (en) * 2008-12-02 2010-06-16 Aflash Technology Co Ltd Semiconductor chip packaging structure
US8294265B1 (en) * 2010-03-31 2012-10-23 Amkor Technology, Inc. Semiconductor device for improving electrical and mechanical connectivity of conductive pillers and method therefor
KR101404464B1 (ko) * 2012-09-12 2014-06-10 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨 패키지 제조용 도금 디바이스 및 이것을 이용한 웨이퍼 레벨 패키지 제조 방법
JP2014241320A (ja) * 2013-06-11 2014-12-25 ソニー株式会社 半導体装置、半導体装置の製造方法
US20150262949A1 (en) * 2014-03-14 2015-09-17 Lsi Corporation Method for Fabricating Equal Height Metal Pillars of Different Diameters
US9754905B1 (en) * 2016-10-13 2017-09-05 International Business Machines Corporation Final passivation for wafer level warpage and ULK stress reduction
US10593640B2 (en) * 2018-04-18 2020-03-17 Texas Instruments Incorporated Flip chip integrated circuit packages with spacers
DE102018207537A1 (de) * 2018-05-15 2019-11-21 Robert Bosch Gmbh Verbundanordnung aus drei gestapelten Fügepartnern
US11469198B2 (en) * 2018-07-16 2022-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device manufacturing method and associated semiconductor die
CN210296353U (zh) * 2019-09-11 2020-04-10 中国电子科技集团公司第五十八研究所 一种三维立体集成封装结构
US11201136B2 (en) * 2020-03-10 2021-12-14 International Business Machines Corporation High bandwidth module

Also Published As

Publication number Publication date
CN112420534A (zh) 2021-02-26
KR20220074765A (ko) 2022-06-03
US20220173063A1 (en) 2022-06-02
TW202221803A (zh) 2022-06-01

Similar Documents

Publication Publication Date Title
US10153240B2 (en) Method of packaging semiconductor devices
KR100319813B1 (ko) 유비엠 언더컷을 개선한 솔더 범프의 형성 방법
US7977789B2 (en) Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
TWI582930B (zh) 積體電路裝置及封裝組件
TWI498978B (zh) 在半導體封裝中有內部中心柱的焊接凸塊
US6407459B2 (en) Chip scale package
KR100605314B1 (ko) 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법
KR101611772B1 (ko) 반도체 디바이스를 패키징하는 방법 및 장치
US9343415B2 (en) Copper post structure for wafer level chip scale package
US9048149B2 (en) Self-alignment structure for wafer level chip scale package
US20130099380A1 (en) Wafer level chip scale package device and manufacturing method therof
CN109979903B (zh) 具有凸块结构的半导体器件和制造半导体器件的方法
US20220208669A1 (en) Method for Forming Semiconductor Package and Semiconductor Package
WO2007064073A1 (en) Bump with multiple vias for semiconductor package, method of fabrication method thereof, and semiconductor package using the same
US6723630B2 (en) Solder ball fabrication process
KR100790527B1 (ko) 웨이퍼레벨 패키지 및 그 제조 방법
CN111682006A (zh) 一种半导体封装结构及其制造方法
CN112420534B (zh) 形成半导体封装件的方法及半导体封装件
US20050064625A1 (en) Method for mounting passive components on wafer
US11955447B2 (en) Semiconductor chip having stepped conductive pillars
US9466577B2 (en) Semiconductor interconnect structure with stacked vias separated by signal line and method therefor
US20230317577A1 (en) Fine pitch chip interconnect structure for bump bridge and high temperature storage improvement and methods for forming the same
JP2009135345A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant