SG107600A1 - Multilayer substrate metallization for ic interconnection - Google Patents
Multilayer substrate metallization for ic interconnectionInfo
- Publication number
- SG107600A1 SG107600A1 SG200203893A SG200203893A SG107600A1 SG 107600 A1 SG107600 A1 SG 107600A1 SG 200203893 A SG200203893 A SG 200203893A SG 200203893 A SG200203893 A SG 200203893A SG 107600 A1 SG107600 A1 SG 107600A1
- Authority
- SG
- Singapore
- Prior art keywords
- layer
- substrate
- interconnection
- metallization
- multilayer substrate
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
A substrate metallization for soldering, with a Pb-free solder or a eutectic SnPb solder (4), to a thin film under-bump-metallization (UBM) of a Si die, comprising: a substrate (1), a layer of Cu (20) formed on a portion of the substrate (1), a layer of Ni (21) formed on the Cu layer (20), an oxidation protection layer (22), and a Ni-barrier layer (23), between the Ni layer (21)and the oxidation protection layer (22), adapted to inhibit diffusion of Ni from the Ni layer (21) to the solder (4) during a reflow process or during high temperature storage.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG200203893A SG107600A1 (en) | 2002-06-27 | 2002-06-27 | Multilayer substrate metallization for ic interconnection |
PCT/SG2003/000154 WO2004004003A1 (en) | 2002-06-27 | 2003-06-26 | Multilayer substrate metallization for ic interconnection |
AU2003251281A AU2003251281A1 (en) | 2002-06-27 | 2003-06-26 | Multilayer substrate metallization for ic interconnection |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG200203893A SG107600A1 (en) | 2002-06-27 | 2002-06-27 | Multilayer substrate metallization for ic interconnection |
Publications (1)
Publication Number | Publication Date |
---|---|
SG107600A1 true SG107600A1 (en) | 2004-12-29 |
Family
ID=29997744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200203893A SG107600A1 (en) | 2002-06-27 | 2002-06-27 | Multilayer substrate metallization for ic interconnection |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU2003251281A1 (en) |
SG (1) | SG107600A1 (en) |
WO (1) | WO2004004003A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8659155B2 (en) | 2009-11-05 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps |
US9227257B2 (en) | 2012-04-24 | 2016-01-05 | Seagate Technology Llc | Laser subassembly metallization for heat assisted magnetic recording |
US10692830B2 (en) | 2017-10-05 | 2020-06-23 | Texas Instruments Incorporated | Multilayers of nickel alloys as diffusion barrier layers |
US11127704B2 (en) * | 2017-11-28 | 2021-09-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with bump structure and method of making semiconductor device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5449955A (en) * | 1994-04-01 | 1995-09-12 | At&T Corp. | Film circuit metal system for use with bumped IC packages |
US6352634B1 (en) * | 1998-06-10 | 2002-03-05 | W. C. Heraeus Gmbh & Co. Kg | Method for producing a lead-free substrate |
US6445069B1 (en) * | 2001-01-22 | 2002-09-03 | Flip Chip Technologies, L.L.C. | Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor |
-
2002
- 2002-06-27 SG SG200203893A patent/SG107600A1/en unknown
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2003
- 2003-06-26 WO PCT/SG2003/000154 patent/WO2004004003A1/en not_active Application Discontinuation
- 2003-06-26 AU AU2003251281A patent/AU2003251281A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
AU2003251281A1 (en) | 2004-01-19 |
WO2004004003A8 (en) | 2004-04-15 |
WO2004004003A1 (en) | 2004-01-08 |
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