TWI720371B - 半導體裝置及其製作方法 - Google Patents
半導體裝置及其製作方法 Download PDFInfo
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- TWI720371B TWI720371B TW107142209A TW107142209A TWI720371B TW I720371 B TWI720371 B TW I720371B TW 107142209 A TW107142209 A TW 107142209A TW 107142209 A TW107142209 A TW 107142209A TW I720371 B TWI720371 B TW I720371B
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Abstract
一種半導體裝置包括基底及設置於基底之上的至少一個凸塊結構。所述至少一個凸塊結構包括由金屬形成的柱,所述金屬對設置於基底之上的焊料合金的可焊性低於銅或銅合金。焊料合金直接形成於可焊性低於銅或銅合金的金屬的上表面之上且接觸金屬的上表面。柱具有大於10微米的高度。
Description
本發明的實施例是有關於半導體裝置及其製作方法。
由於具有更優效能的消費型裝置因應於消費者需求而已變得愈來愈小,因此該些裝置的個別組件的大小亦必須減小。構成諸如行動電話、電腦平板等消費型裝置的主要組件的半導體裝置已變得愈來愈小。半導體製造技術的進步(諸如,形成半導體裝置之間的連接)已滿足半導體裝置大小的減小。
由於電子行業基於矽穿孔(through-Si-vias,TSV)技術而開發出三維積體電路(three dimensional integrated circuit,3D IC),因此正在活躍地研究用於對堆疊晶片進行內連的凸塊的處理及凸塊的可靠性。在凸塊大小減小的過程中,凸塊的直徑減小至較倒裝晶片焊料接點的直徑小約一個量級,且體積較倒裝晶片焊料接點小約1000倍。焊料接點的大小愈小,凸塊焊料接點發生故障的可能性愈高。
本發明實施例的一種半導體裝置,包括基底以及至少一個凸塊結構。至少一個凸塊結構設置於基底之上,其中至少一個凸塊結構包括柱以及焊料合金。柱由金屬形成,所述金屬對設置於基底之上的焊料合金的可焊性低於銅或銅合金。焊料合金直接形成於可焊性低於銅或銅合金的金屬的上表面之上且接觸金屬的上表面。柱具有大於10微米的高度。
本發明實施例的一種半導體裝置,包括第一基底以及第二基底。第一基底包括第一電路系統。第一基底經由包括焊料層的連接件而連接至第二基底,焊料層設置於第一柱與第二柱之間,且其中第一柱是由鎳系材料形成,具有大於10微米的高度。
本發明實施例的一種製作半導體裝置的方法,包括:在基底之上形成光阻層;將光阻層圖案化以形成多個開口,多個開口暴露出基底;在多個開口中沈積可焊性低於銅或銅合金材料的金屬;在多個開口中的可焊性低於銅或銅合金材料的金屬之上形成焊料層;以及移除光阻層,其中焊料層直接接觸可焊性低於銅或銅合金材料的金屬。
10、10’、10a、10b、10c、80:半導體裝置
12、12’、15、15’:基底
20、20’:接合接墊
25、25’:第二金屬層/柱
30、30’:第一金屬層/銅或銅合金層
35、35’:焊料層
40、40’:凸塊下金屬化物
40a:鈦系層
40b:銅系層
55、55’、55a、55b、55c:凸塊結構
60、60’:絕緣層
65:光阻層
75:開口
90:焊料接點
95:底部填充材料
150:終飾層
155、155’:電路系統
160、160’:裝置
165、165’:內連結構
170、170’:絕緣層
200、300、400、500:方法
A-A、B-B:線
D1、D2、D3、D4、D5、D6、D7:高度
S1、S2:節距
S210、S220、S230、S240、S250、S260、S310、S320S、330、
S410、S420、S430、S440、S450、S510、S520、S530、S540:操作
X、Y:方向
結合附圖進行閱讀,自以下詳細說明更好地理解本發明。需強調,根據行業中的標準慣例,各種特徵並不按比例繪製,而是僅用於說明目的。事實上,為論述清晰起見,可任意地增大
或減小各種特徵的尺寸。
圖1是根據本發明實施例的凸塊結構的示意圖。
圖2A及圖2B說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者。圖2A是平面圖,且圖2B是沿著圖2A所示的線A-A的剖視圖。
圖3是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖4是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖5是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖6是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖7是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖8是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖9是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖10A及圖10B說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者。圖10A是沿著圖10B所示平面圖的線B-B的剖視圖。
圖11是說明根據本發明實施例的製作半導體裝置的方法的流程圖。
圖12是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖13是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖14是說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者的剖視圖。
圖15是說明根據本發明實施例的製作半導體裝置的方法的流程圖。
圖16是根據本發明實施例的凸塊結構的示意圖。
圖17是說明根據本發明實施例的製作半導體裝置的方法的流程圖。
圖18是根據本發明實施例的凸塊結構的示意圖。
圖19是說明根據本發明實施例的製作半導體裝置的方法的流程圖。
圖20是根據本發明實施例的凸塊的示意圖。
應理解,以下揭露內容提供諸多不同的實施例或實例以實施本發明的不同特徵。下文闡述組件及排列的具體實施例或實例以使本發明簡潔。當然,該些僅僅是實例,並不旨在進行限制。
舉例而言,元件的尺寸並不僅限於所揭露的範圍或值,而是可根據製程條件及/或所期望的裝置性質而定。此外,在以下說明中,第一特徵形成於第二特徵之上或形成於第二特徵上可包括第一特徵與第二特徵形成為直接接觸的實施例,且亦可包括額外特徵可介於第一特徵與第二特徵之間而形成以使第一特徵與第二特徵不可直接接觸的實施例。為簡潔及清晰起見,可按照不同比例任意地繪製各種特徵。
此外,為便於說明起見,本文中可使用諸如「在…下方」、「在…之下」、「下部」、「在…上方」、「上部」等空間相對用語來闡述一個元件或特徵與另外的元件或特徵之間的關係,如圖中所示。空間相對用語旨在囊括除圖中所繪示的定向之外的裝置在使用或操作中的不同定向。可以其他方式對裝置進行定向(旋轉90度或處於其他定向),且可相應地對本文中所使用的空間相對描述符類似地加以解釋。另外,用語「由…製作」可意指「包含」或「由…組成」。
圖1是根據本發明實施例的凸塊結構的示意圖。半導體裝置10具有基底15及設置於基底15上的至少一個凸塊結構55。接合接墊20設置於基底15上。接合接墊20電性連接至基底15的電路系統。凸塊結構55經由接合接墊20連接至基底15的電路系統。所述至少一個凸塊結構55包括主要由金屬形成的柱25,所述金屬對焊料合金的可焊性(solderability)(可濕性(wettability))低於銅或銅合金。換言之,可焊性(或可濕性)低於銅或銅合金
的所述金屬不太可能在金屬與焊料合金的界面處與焊料合金的成分形成金屬間化合物(或合金)。由於柱具有較銅或銅合金低的可焊性,因此焊料順著柱的側面的流動受到抑制。在一些實施例中,柱25是由鎳系材料形成。在一些實施例中,鎳系材料包含鎳以及含50摩爾百分比(mol%)或高於50摩爾百分比(mol%)的鎳的鎳合金。在一些實施例中,凸塊結構55僅包括一個鎳系層25。在一些實施例中,半導體裝置10包括設置於柱25與基底15之間的接合接墊20上的凸塊下金屬化物(under bump metallization)40。
在一些實施例中,凸塊結構55包括設置於柱25與凸塊下金屬化物40之間的銅或銅合金層30。在一些實施例中,選擇具有較低可焊性(或可濕性)的金屬,以使金屬間化合物的形成極緩慢,藉此防止焊料沿柱25的高度移動而接觸下方的銅或銅合金層30。在一些實施例中,絕緣層60形成於基底15之上且環繞凸塊下金屬化物40。
在一些實施例中,接合接墊20是由適合的導電金屬及/或其多個層形成,所述導電金屬包括鋁、銅、銀、金,鎳、鎢、鈦、其合金。
在一些實施例中,凸塊結構55包括設置於柱25上的焊料層35。在一些實施例中,焊料層35是由諸如AgSn、SnAgCu、PbSn及CuSn等含錫合金形成。在一些實施例中,焊料層35直接實體接觸柱25的上表面。在一些實施例中,焊料層35不直接實體接觸銅或銅合金層30。
在一些實施例中,柱25具有大於10微米至約30微米的高度D1。在柱高度D1大於10微米時,柱25所具有的高度足以抑制焊料順著凸塊迅速流動而在焊料接合區形成空隙或足以抑制焊料接觸其他半導體裝置特徵而造成短路。柱高度D1大於典型的頂蓋層(cap layer)高度。頂蓋層在傳統的凸塊結構中用作障壁層來防止銅或銅合金層中的銅擴散至焊料層中。在柱高度大於約30微米時,積體電路中的裝置密度會由於積體電路組件之間的間隔增大而減小。在一些實施例中,柱25具有介於約5微米至約40微米範圍內的直徑。在一些實施例中,柱25具有介於約20微米至約25微米範圍內的直徑。在實施例中,半導體裝置10包括位於柱25與凸塊下金屬化物40的上表面之間的銅或銅合金層30,銅或銅合金層30具有約5微米至約10微米的高度D2。在一些實施例中,柱25的高度D1大於銅或銅合金層30的高度D2。在一些實施例中,柱25的高度D1對銅或銅合金層30的高度D2的比率(D1/D2)介於約6/1至約1.5/1範圍內。在一些實施例中,柱25的高度D1對銅或銅合金層30的高度D2的比率(D1/D2)介於約5/1至約3/1範圍內。在一些實施例中,柱25的高度D1對銅或銅合金層30的高度D2的比率(D1/D2)介於約4/1至約2/1範圍內。
在一些實施例中,在給定高度處,凸塊結構55的側壁的材料組成物與凸塊結構55的內部部分的材料組成物實質上相同。換言之,在一些實施例中,在凸塊結構55的側壁上不存在特意形
成的層。舉例而言,在一些實施例中,在柱25的側壁上不存在特意形成的鈍化層,諸如氮化物層。
在一些實施例中,半導體裝置10是其中包括諸如電晶體等主動裝置的裝置晶粒。在其他實施例中,半導體裝置10包括上方形成有裝置晶粒的封裝基底或中介物(interposer)。在一些實施例中,凸塊結構55用於將半導體晶片或晶粒接合至中介物、封裝基底或另一半導體晶片或晶粒。
圖2A及圖2B說明根據本發明實施例的製作半導體裝置的方法的各種操作中的一者。圖2A是平面圖,且圖2B是沿著圖2A所示線A-A的剖視圖。如圖2A中所示,上方將形成有凸塊的多個接合接墊20排列於基底15的表面上。接合接墊20是由適合的導電金屬及/或其多個層形成,所述導電金屬包括鋁、銅、銀、金,鎳、鎢、鈦、其合金。接合接墊是藉由適合的金屬沈積操作形成,所述金屬沈積操作包括:電鍍或化學鍍、包括濺鍍在內的物理氣相沈積(physical vapor deposition,PVD)、化學氣相沈積(chemical vapor deposition,CVD)、原子層沈積(atomic layer deposition,ALD)、熱蒸鍍或電子束蒸鍍。在一些實施例中,接合接墊20以列-行排列方式排列。
圖3至圖10B是說明根據本發明實施例的製作半導體裝置的方法的各個階段的剖視圖。在一些實施例中,在接合接墊及絕緣層60之上形成凸塊下金屬化物40,如圖3中所示。
在一些實施例中,在基底12上設置包括裝置160的電路
系統155。在一些實施例中,裝置160包括電晶體、電容器、電感器、電阻器等。在一些實施例中,接合接墊20及凸塊結構55經由包括接線層及通孔的下方內連結構165電性耦合至電路系統155。內連結構165的接線層及通孔可由銅或銅合金、鋁、鎢、鎳、或任何其他適合的金屬形成。可使用鑲嵌製程來形成接線層及通孔。在一些實施例中,電路系統155嵌入於絕緣層170中,諸如層間介電(interlayer dielectric,ILD)層或金屬間介電(intermetal dielectric,IMD)層。
在一些實施例中,基底15包括半導體基座12。半導體基座12由選自以下所組成的群組中的至少一者形成:矽、金剛石、鍺、SiGe、SiGeSn、SiGeC、GeSn、SiSn、GaAs、InGaAs、InAs、InP、InSb、GaAsP、GaInP及SiC。在一些實施例中,半導體基座12是矽晶圓。
在一些實施例中,在基底15之上形成絕緣層60。在一些實施例中,絕緣層60是氧化物層。在一些實施例中,使用適合的微影及蝕刻操作來將絕緣層60圖案化以形成開口,在所述開口中沈積凸塊下金屬化物40。在一些實施例中,凸塊下金屬化物是藉由適合的金屬沈積操作形成,所述金屬沈積操作包括:電鍍或化學鍍、包括濺鍍在內的物理氣相沈積(PVD)、化學氣相沈積(CVD)、原子層沈積(ALD)、熱蒸鍍及電子束蒸鍍。在一些實施例中,在形成凸塊下金屬化物之前,在接合接墊上沈積晶種層(未繪示)。在一些實施例中,凸塊下金屬化物40延伸於絕緣層
60之上,且藉由諸如化學機械研磨(chemical mechanical polishing,CMP)等適合的操作來移除多餘的凸塊下金屬化物。
在實施例中,凸塊下金屬化物40包括設置於接墊20上的鈦系層及設置於鈦系層上的濺鍍沈積的銅系層。鈦系材料包括鈦以及含50摩爾百分比(mol%)或高於50摩爾百分比(mol%)的鈦的鈦合金及鈦化合物。銅系材料包括銅以及含50摩爾百分比(mol%)或高於50百分比(mol摩爾%)的銅的銅合金及銅化合物。在實施例中,鈦系層是厚度介於20奈米至70奈米範圍內的Ti或TiW的濺鍍沈積層。
接下來,在本發明的一些實施例中,在凸塊下金屬化物40及絕緣層60之上形成光阻層65,如圖4中所示。光阻層65可以是正性光阻或負性光阻。當光阻是正性光阻時,光阻的曝光於光化輻射下的部分在顯影操作期間可溶於顯影劑中且被移除。當光阻是負性光阻時,光阻的曝光於光化輻射下的部分在顯影操作期間不可溶於顯影劑中且存留於裝置上,而未曝光於光化輻射下的部分被移除。在一些實施例中,光化輻射是:紫外線輻射,包括i線輻射(i-line radiation)及g線輻射輻射(g-line radiation)、及深紫外線輻射(deep ultraviolet radiation)、極紫外線(extreme ultraviolet,EUV)輻射;以及電子束輻射。在一些實施例中,光化輻射是由以下產生:汞弧燈(mercury arc lamp)或包括ArF及KrF準分子雷射(excimer laser)在內的雷射;及雷射激發錫電漿。
隨後,使光阻層65選擇性地曝光於光化輻射下並進行顯
影以形成多個開口75,所述多個開口75暴露出凸塊下金屬化物40,如圖5中所示。在一些實施例中,開口75實質上是直徑介於約10微米至約40微米範圍內的圓形。在一些實施例中,開口75具有介於約20微米至約25微米範圍內的直徑。
在一些實施例中,隨後在凸塊下金屬化物40之上的開口75中形成第一金屬層30,如圖6中所示。在一些實施例中,第一金屬層30是銅或銅合金。第一金屬層30可藉由適合的金屬沈積操作來形成,所述金屬沈積操作包括電鍍或化學鍍、包括濺鍍在內的物理氣相沈積(PVD)、化學氣相沈積(CVD)、原子層沈積(ALD)、熱蒸鍍及電子束蒸鍍。在一些實施例中,在形成第一金屬層之前,在凸塊下金屬化物上沈積晶種層(未繪示)。在一些實施例中,第一金屬層被沈積達約5微米至約10微米的厚度。
談及圖7,在第一金屬層30之上的開口75中形成第二金屬層25。在一些實施例中,第二金屬層25形成柱25,柱25是由對焊料合金的可焊性或可濕性低於銅或銅合金的金屬所形成。
在一些實施例中,第二金屬層25的高度D1大於第一金屬層30的高度D2。在一些實施例中,第二金屬層25的高度D1大於10微米至約30微米。在一些實施例中,第二金屬層25具有介於約5微米至約40微米範圍內的直徑。在一些實施例中,第二金屬層25具有介於約20微米至約25微米範圍內的直徑。在一些實施例中,第一金屬層30在第二金屬層25與凸塊下金屬化物40的上表面之間具有約5微米至約10微米的高度D2。在一些實施
例中,第二金屬層25的高度D1對第一金屬層30的高度D2的比率(D1/D2)介於約6/1至約1.5/1範圍內。在一些實施例中,第二金屬層25的高度D1對第一金屬層30的高度D2的比率(D1/D2)介於約5/1至約3/1範圍內。在一些實施例中,第二金屬層25的高度D1大於第一金屬層30的高度D2。
在一些實施例中,第二金屬層或柱25主要由選自以下所組成的群組的金屬形成:鋁、鉻、鐵、錳、鎂、鉬、鎳、鈮、鉭、鈦、鎢、鋅及其合金。在一些實施例中,第二金屬層或柱25是由鎳系材料形成。在一些實施例中,鎳系材料包括鎳以及含50摩爾百分比(mol%)或高於50摩爾百分比(mol%)的鎳的鎳合金。在一些實施例中,第二金屬層或柱25是藉由適合的金屬沈積操作形成,所述金屬沈積操作包括:電鍍或化學鍍、包括濺鍍在內的物理氣相沈積(PVD)、化學氣相沈積(CVD)、原子層沈積(ALD)、熱蒸鍍及電子束蒸鍍。
如圖8中所示,在一些實施例中,隨後在第二金屬層25之上的開口中形成焊料層35。在一些實施例中,焊料層35包括共晶焊料(eutectic solder),諸如選自AgSn、SnAgCu、PbSn及CuSn所組成的群組的合金。可使用其他適合的焊料,只要柱對焊料的可焊性(可濕性)低於銅或銅合金即可。在一些實施例中,焊料層35的厚度是約2微米至約10微米。在一些實施例中,自光阻層65上方移除多餘的焊料。
如圖9中所示,隨後移除光阻層65以暴露出焊料層35
的側壁、柱25的側壁及第一金屬層30的側壁。在一些實施例中,使用適合的光阻剝離器來移除光阻層65。然後,諸如藉由適合的蝕刻操作來移除凸塊下金屬化物40的暴露部分。
在一些實施例中,如圖10A中所示,在移除了光阻層65之後,使焊料層35回流以形成光滑的半球形狀來提供具有多個凸塊結構55的半導體裝置10。圖10A是沿著圖10B所示平面圖的線B-B的剖視圖。藉由將焊料加熱至使焊料軟化並流動的溫度來使焊料層35回流。
圖10B是繪示半導體裝置10上的凸塊結構55的列-行排列的平面圖。雖然繪示了凸塊結構的3×3排列,但本發明並不僅限於3×3排列。包括更少或更多的凸塊結構列或凸塊結構行的其他排列包括於本發明的範疇中。舉例而言,排列可以是10×10排列,或更多的行及列。凸塊結構的排列並不僅限於矩形排列。在一些實施例中,其他排列包括交錯的列及行,在交錯的列及行中每一凸塊結構緊鄰六個其他的凸塊結構。在其他實施例中,凸塊結構是以同心圓排列形式排列。在其他實施例中,凸塊結構被排列於基底的周邊周圍或被排列於基底的中心部分中。在其他實施例中,凸塊結構的間隔是不規則的。在一些實施例中,多達約10,000個凸塊結構形成於基底上。
在一些實施例中,凸塊結構55具有介於約5微米至約40微米範圍內的直徑D3,如在平面圖中所見。在一些實施例中,凸塊結構55具有介於約20微米至約25微米範圍內的直徑D3。在
一些實施例中,所述多個凸塊結構55是以在X方向上自一個凸塊結構55的中心至鄰近凸塊結構55的中心的節距(pitch)S1為約15微米至約60微米的列-行排列形式排列。在一些實施例中,所述多個凸塊結構55在X方向上具有自一個凸塊結構55的中心至鄰近凸塊結構55的中心約25微米至約40微米的節距S1。在一些實施例中,所述多個凸塊結構55在Y方向上具有自一個凸塊結構55的中心至鄰近凸塊結構55的中心約15微米至約60微米的節距S2。在一些實施例中,所述多個凸塊結構55在Y方向上具有自一個凸塊結構55的中心至鄰近凸塊結構55的中心約25微米至約40微米的節距S2。
在一些實施例中,凸塊結構的直徑D3對X方向上的節距S1的比率介於約1/12至約8/9範圍內。在一些實施例中,凸塊結構的直徑D3對X方向上的節距S1的比率介於約1/3至約2/3範圍內。在一些實施例中,凸塊結構的直徑D3對Y方向上的節距S2的比率介於約1/12至約8/9範圍內。在一些實施例中,凸塊結構的直徑D3對Y方向上的節距S2的比率介於約1/3至約2/3範圍內。在一些實施例中,X方向上的節距S1與Y方向上的節距S2實質上相同。在一些實施例中,X方向上的節距S1大於Y方向上的節距S2。在一些實施例中,X方向上的節距S1小於Y方向上的節距S2。
應理解,圖10A及圖10B中所示的裝置經過了另外的半導體製程以形成各種特徵,諸如外部接點、介電層、至模組中的
整合(integration into module)等。
圖11是說明根據本發明實施例的製作半導體裝置的另一方法200的流程圖。在操作S210中,在第一基底及第二基底之上形成銅或銅合金層。銅或銅合金層可藉由適合的金屬沈積操作來形成,所述金屬沈積操作包括電鍍或化學鍍、包括濺鍍在內的物理氣相沈積(PVD)、化學氣相沈積(CVD)、原子層沈積(ALD)、熱蒸鍍及電子束蒸鍍。在操作S220中,在位於基底上的每一銅或銅合金層之上形成對焊料合金的可焊性低於銅或銅合金的具有大於10微米厚度的金屬。在一些實施例中,銅或銅合金層具有高達約30微米的厚度。在一些實施例中,焊料合金選自AgSn、SnAgCu、PbSn及CuSn所組成的群組。可焊性低於銅或銅合金的金屬層可藉由適合的金屬沈積操作來形成,所述金屬沈積操作包括電鍍或化學鍍、包括濺鍍在內的物理氣相沈積(PVD)、化學氣相沈積(CVD)、原子層沈積(ALD)、熱蒸鍍及電子束蒸鍍。隨後在操作S230中,在可焊性低於位於基底上的銅或銅合金的每一金屬層之上形成焊料層,藉此在第一基底及第二基底中的每一者上形成凸塊結構。
隨後在操作S240中,擺置第一基底及第二基底以使位於第一基底上的凸塊結構與位於第二基底上的凸塊結構面向彼此且彼此對齊。接下來,在操作S250中,使位於第一基底上的凸塊結構與位於第二基底上的凸塊結構彼此接觸。然後在操作S260中,對凸塊施加能量以使凸塊結構上的焊料層流動且將位於第一基底
上的凸塊結構與位於第二基底上的凸塊結構熔融在一起。
圖12至圖15說明根據本發明實施例將位於兩個基底15與15’上的凸塊結構55與55’熔融在一起的方法。如圖12中所示,第一半導體裝置10及第二半導體裝置10’包括根據圖2A至圖10B中所述的操作而形成多個凸塊結構55。將第二半導體裝置10’定向成使得第一半導體裝置10中的凸塊結構55的焊料層35面向第二半導體裝置10’中的凸塊結構55’的焊料層35’且與焊料層35’對齊。在一些實施例中,第二半導體裝置10’是封裝基底、中介物或其中未形成電路系統155’的基底。
使第一半導體裝置10的凸塊結構55與第二半導體裝置10’的凸塊結構55彼此接觸並施加能量以使焊料層35與35’軟化並流動至彼此中,且然後熔融以在焊料接點90處形成金屬間接合,當能量被移除時第一半導體裝置10與第二半導體裝置10’在焊料接點90處結合,如圖13中所示。在實施例中,在基底熔融在一起之後,第一基底15經由柱/焊料/柱連接接合至第二基底15’進而形成半導體裝置80,半導體裝置80是第一半導體裝置10與第二半導體裝置10’的組合。在一些實施例中,所述能量是熱能量、超音波能量或熱能量與超音波能量的組合。在一些實施例中,藉由被加熱的空氣、紅外線加熱燈或雷射來供應熱能量。在一些實施例中,藉由超音波換能器來施加超音波能量。
為提高半導體裝置80的良率且延長半導體裝置80的壽命,在一些實施例中,在結合的基底15與15’之間形成底部填充
材料95,如圖14中所示。底部填充材料將焊料內連線嵌入於底部填充材料內。底部填充材料95機械地耦合基底15與15’且減小焊料接點90上的應力以提高裝置的良率及壽命。
在一些實施例中,底部填充材料95是熱可固化液體聚合物樹脂。可將底部填充材料95施加至第一基底15與第二基底15’之間的區域的邊緣,且然後藉由毛細管作用將底部填充材料95汲取至第一基底15與第二基底15’之間的空隙中。在一些實施例中,多次執行底部填充材料的施加以完全填充所述空隙。在一些實施例中,在施加底部填充材料95之前,藉由在空隙上施加真空來輔助底部填充材料95的施加。在一些實施例中,藉由將底部填充聚合物樹脂加熱至較樹脂固化點低的溫度來輔助底部填充操作以減小底部填充聚合物樹脂的黏性。
在一些實施例中,底部填充材料是液體樹脂。在一些實施例中,各種樹脂可用作底部填充材料,包括諸如矽酮、環氧樹脂及聚醯胺等熱固性模製化合物。環氧樹脂包括酚醛環氧樹脂。底部填充樹脂可視需要含有填充劑,諸如二氧化矽、氧化鋁、滑石等。
圖15是說明根據本發明另一實施例的製作具有凸塊結構55a的半導體裝置10a的方法300的流程圖。圖16中繪示根據圖15的方法300而形成的半導體裝置10a。半導體裝置10a具有基底15及設置於基底15上的至少一個凸塊結構55a。在操作S310中,在基底15之上沈積凸塊下金屬化物40。在一些實施例中,凸
塊下金屬化物40包括鈦系層及/或銅系層。在一些實施例中,凸塊下金屬化物40具有約5奈米至約500奈米的厚度。在沈積了凸塊下金屬化物之後,在操作S320中,在凸塊下金屬化物之上形成對焊料合金的可焊性低於銅或銅合金的金屬層以形成柱25,自凸塊下金屬化物40的上表面量測所述金屬層具有大於10微米的高度D3。在一些實施例中,柱25是藉由適合的金屬沈積操作形成的鎳系材料,所述金屬沈積操作包括電鍍或化學鍍、包括濺鍍在內的物理氣相沈積(PVD)、化學氣相沈積(CVD)、原子層沈積(ALD)、熱蒸鍍及電子束蒸鍍。隨後在操作S330中,在鎳系層25上形成焊料層35,藉此形成凸塊結構55a。
應理解,圖16中所示的裝置經過另外的半導體製程以形成各種特徵,諸如外部接點、介電層、至模組中的整合等。
圖17是說明根據本發明另一實施例的製作具有凸塊結構55b的半導體裝置10b的方法400的流程圖。圖18中繪示根據圖17的方法400而形成的半導體裝置10b。圖18是根據本發明另一實施例具有至少一個凸塊結構55b的半導體裝置10b的示意圖。在操作S410中,在基底15之上形成鈦系層40a。在操作S420中,在鈦系層40a之上沈積銅系層40b。因此形成包括多個層40a與40b的凸塊下金屬化物40。在一些實施例中,藉由濺鍍來沈積鈦系層40a及銅系層40b。在一些實施例中,鈦系層40a的厚度為約5奈米至約100奈米。在其他實施例中,鈦系層40a的厚度為約20奈米至約70奈米。在一些實施例中,銅系層40b的厚度為約5
奈米至約500奈米。在其他實施例中,銅系層40b的厚度為約10奈米至約100奈米。在其他實施例中,銅系層40b的厚度為約20奈米至約70奈米。在實施例中,鈦系層是厚度介於約20奈米至約70奈米範圍內的Ti或TiW的濺鍍沈積層。
在形成了凸塊下金屬化物40之後,在操作S430中,在凸塊下金屬化物40之上形成銅或銅合金層30。在一些實施例中,藉由電鍍或化學鍍將銅或銅合金層形成達自凸塊下金屬化物40的上表面量測約5微米至約10微米的高度D4。在操作S440中,在銅或銅合金層30之上形成對焊料合金的可焊性低於銅或銅合金的金屬層以形成柱25,所述金屬層具有大於10微米的高度D5。在一些實施例中,柱25具有高達30微米的高度。在一些實施例中,柱25是藉由本文中先前所揭露的適合的金屬沈積操作形成的鎳系材料。隨後在操作S450中,在柱25上形成焊料層35,藉此形成凸塊結構55b。
在一些實施例中,鈦系層40a及銅系層40b覆蓋接合接墊20的上表面及基底15的上表面,且然後使用適合的微影及蝕刻操作來將鈦系層40a及銅系層40b圖案化以在接合接墊20之上形成多個凸塊下金屬化物40。然後,環繞凸塊下金屬化物40而形成絕緣層60。在一些實施例中,凸塊下金屬化物40以節距為約15微米至約60微米的列-行排列形式排列。
在一些實施例中,形成對焊料合金的可焊性低於銅或銅合金的金屬層包括:在基底15及所述多個凸塊下金屬化物之上形
成光阻層,利用微影技術將光阻層圖案化以形成暴露出所述多個凸塊下金屬化物的多個開口,在所述多個開口中沈積金屬,在所述多個開口中的金屬之上沈積焊料層,及移除光阻層,此類似於圖5至圖10中所揭露的操作。
應理解,圖18中所示的裝置經過另外的半導體製程以形成各種特徵,諸如外部接點、介電層、至模組中的整合等。
圖19是說明根據本發明另一實施例的製作半導體裝置10c的另一方法500的流程圖。半導體裝置10c包括基底15及設置於基底15上的至少一個凸塊結構55c,如圖20中所示。在操作S510中,在凸塊下金屬化物40之上形成銅或銅合金層30。在一些實施例中,自凸塊下金屬化物40的上表面進行量測,銅或銅合金層形成達約5微米至約10微米的高度D6。在操作S520中,在銅或銅合金層之上形成對焊料合金的可焊性低於銅或銅合金的金屬層以形成柱25,所述金屬層具有大於10微米的高度D7。在一些實施例中,柱25具有高達30微米的高度。在一些實施例中,柱25是藉由本文中先前所揭露的適合的金屬沈積操作形成的鎳系材料。接下來在操作S530中,在柱25之上形成終飾層(finish layer)150。在形成終飾層150之後,在操作S540中,在終飾層150之上形成焊料層35,藉此形成凸塊結構55c。
在一些實施例中,終飾層150是金屬層。終飾層150可由鎳形成,但亦可添加其他金屬。在一些實施例中,終飾層150由化學鍍鎳鈀浸金(electroless nickel electroless palladium
immersion gold,ENEPIG)形成,終飾層150包括鎳層、位於鎳層上的鈀層及位於鈀層上的金層。可使用浸鍍來形成金層。在其他實施例中,終飾層150由其他已知的終飾材料及其他已知的方法形成,所述其他已知的方法包括但不限於化學鍍鎳浸金(ENIG)、直接浸金(DIG)等。在一些實施例中,終飾層實質上不含銅。如本文中所使用,實質上不含銅意味著若在終飾層中存在任何銅,則僅在雜質級(impurity level)下才存在。形成終飾層150的方法包括化學鍍、浸沒等。終飾層150與下方的柱25形成大的界面面積,藉此加強柱25與焊料層35之間的接合。在一些實施例中,終飾層150具有介於約5奈米至約100奈米範圍內的厚度。
應理解,圖20中所示的裝置經過另外的半導體製程以形成各種特徵,諸如外部接點、介電層、至模組中的整合等。
在接合製程期間,焊料可順著柱(諸如銅柱)快速流動,此時會在銅柱與焊料中的錫之間形成金屬間化合物/合金。順著柱迅速流動可能會在焊料接合中形成空隙。可焊性(或可濕性)低於柱的銅或銅合金的金屬會減慢金屬間化合物的形成且減慢焊料順著柱的流動,藉此抑制空隙形成於焊料接合中。由於焊料順著凸塊結構的側面的流動受到抑制,因此在焊接操作期間焊料保持於焊料接點區域中,藉此防止空隙形成於焊料接點中。另外,可焊性(或可濕性)低於銅或銅合金的金屬會抑制由於焊料順著凸塊結構的側面流動而導致的焊料溢流及形成短路的問題。特別是
隨著凸塊結構的大小及節距減小,根據本發明的裝置及方法會提高半導體裝置的可靠性。
應理解,並非所有優勢皆在本文中加以必要論述,不存在所有的實施例或實例皆需要的特定優勢,且其他實施例或實例可提供不同的優勢。
本發明的實施例是一種半導體裝置,所述半導體裝置包括基底及設置於所述基底之上的至少一個凸塊結構。所述至少一個凸塊結構包括:柱,由對設置於所述基底之上的焊料合金的可焊性低於銅或銅合金的金屬形成;及焊料合金,直接形成於可焊性低於銅或銅合金的所述金屬的上表面之上且接觸所述金屬的所述上表面。所述柱具有大於10微米的高度。在實施例中,所述半導體裝置包括位於所述柱與所述基底之間的銅或銅合金層,其中所述柱的所述高度大於所述銅或銅合金層的高度。在實施例中,所述銅或銅合金層具有5微米至10微米的高度。在實施例中,所述柱的所述高度對所述銅或銅合金層的所述高度的比率介於6/1至1.5/1範圍內。在實施例中,所述柱的所述高度對所述銅或銅合金層的所述高度的比率介於5/1至3/1範圍內。在實施例中,所述柱主要由選自以下所組成的群組的金屬形成:鋁、鉻、鐵、錳、鎂、鉬、鎳、鈮、鉭、鈦、鎢、鋅及其合金。在實施例中,所述柱的所述高度介於大於10微米至30微米範圍內。在實施例中,所述柱具有介於5微米至40微米範圍內的直徑。在實施例中,所述柱具有介於20微米至25微米範圍內的直徑。在實施例中,所
述半導體裝置包括設置於所述基底與所述凸塊結構之間的凸塊下金屬化物。在實施例中,所述多個凸塊結構以節距介於15微米至60微米範圍內的列-行排列方式排列。
本發明的另一實施例是一種半導體裝置,所述半導體裝置包括第一基底及第二基底,所述第一基底包括第一電路系統。所述第一基底經由包括焊料層的連接件而連接至所述第二基底,所述焊料層設置於第一柱與第二柱之間。所述第一柱是由鎳系材料形成,具有大於10微米的高度。在實施例中,所述半導體裝置包括設置於所述第一柱與所述基底之間的銅或銅合金層,其中所述第一柱的所述高度大於所述銅或銅合金層的高度。在實施例中,所述銅或銅合金層具有5微米至10微米的高度。在實施例中,所述第一柱的所述高度對所述銅或銅合金層的所述高度的比率介於6/1至1.5/1範圍內。在實施例中,所述第一柱或所述第二柱具有介於5微米至40微米範圍內的直徑。在實施例中,所述半導體裝置包括位於所述第一柱與所述焊料層之間的實質上不含銅的終飾層。
本發明的另一實施例是一種具有凸塊結構的半導體裝置,所述半導體裝置包括基底及設置於所述基底之上的至少一個凸塊結構。所述至少一個凸塊結構包括:柱,由鎳系材料形成,具有大於10微米的高度;及焊料合金,直接形成於所述柱的上表面之上且接觸所述柱的所述上表面。在實施例中,所述半導體裝置包括位於所述柱與所述基底之間的銅或銅合金層,其中所述柱
的所述高度對所述銅或銅合金層的所述高度的比率介於6/1至1.5/1範圍內。在實施例中,所述柱的高度介於大於10微米至30微米範圍內。
本發明的另一實施例是一種製作半導體裝置的方法,所述方法包括:在基底之上形成光阻層;及將所述光阻層圖案化以形成多個開口,所述多個開口暴露出所述基底。在所述多個開口中沈積可焊性低於銅或銅合金材料的金屬。在所述多個開口中的可焊性低於銅或銅合金材料的所述金屬之上形成焊料層,並移除所述光阻層。所述焊料層直接接觸可焊性低於銅或銅合金材料的所述金屬。在實施例中,所述方法包括:在所述多個開口中沈積可焊性低於銅或銅合金材料的所述金屬層之前,在所述多個開口中沈積銅或銅合金材料,其中可焊性低於銅或銅合金材料的所述金屬的高度大於所述銅或銅合金材料的高度。在實施例中,所述方法包括在所述基底與可焊性低於所述銅或銅合金材料的所述金屬之間形成鈦系層。在實施例中,所述鈦系層是藉由濺鍍形成。在實施例中,在所述鈦系層之上形成濺鍍沈積的銅系層。在實施例中,所述方法包括在所述濺鍍沈積的銅系層上電鍍或化學鍍銅或銅合金材料。在實施例中,對焊料合金的可焊性低於銅或銅合金的金屬具有大於10微米至30微米的高度。在實施例中,可焊性低於銅或銅合金的所述金屬是藉由電鍍或化學鍍沈積於所述多個開口中。在實施例中,所述方法包括:在所述基底之上形成鈦系層,在所述鈦系層之上形成銅系層,及蝕刻所述鈦系層及所述
銅系層以形成多個凸塊下金屬化物,所述多個凸塊下金屬化物以節距介於15微米至60微米範圍內的列-行排列形式排列。
本發明的另一實施例是一種製作半導體裝置的方法,所述方法包括:將設置於第一基底之上的光阻層圖案化以形成開口,所述開口暴露出所述第一基底的一部分。在所述開口中沈積對焊料合金的可焊性低於銅或銅合金的金屬層。可焊性低於銅或銅合金的所述金屬層具有大於10微米的高度。在可焊性低於銅或銅合金的金屬層之上形成焊料層。移除光阻層,藉此在第一基底上形成多個第一凸塊結構。將所述第一基底及具有多個第二凸塊結構的第二基底擺置成使得所述第一凸塊結構與所述第二凸塊結構面向彼此且彼此對齊。使所述第一凸塊結構與所述第二凸塊結構彼此接觸,且對第一凸塊結構及第二凸塊結構施加能量以使所述凸塊結構上的焊料流動且所述第一凸塊結構與所述第二凸塊結構熔融在一起。在實施例中,所述方法包括:在所述開口中沈積銅或銅合金層,其中可焊性低於銅或銅合金的所述金屬層的高度大於所述銅或銅合金層的高度。在實施例中,所述能量是熱能量、超音波能量、或熱能量與超音波能量的組合。在實施例中,在第一凸塊結構與第二凸塊結構熔融在一起之後,所述第一基底經由柱/焊料/柱連接接合至所述第二基底。在實施例中,可焊性低於銅或銅合金的金屬主要由選自以下所組成的群組的金屬形成:鋁、鉻、鐵、錳、鎂、鉬、鎳、鈮、鉭、鈦、鎢、鋅、及其合金。在實施例中,所述方法包括:在可焊性低於銅或銅合金的金屬層與
第一基底之間形成厚度為約5微米至10微米的銅層。
本發明的另一實施例是一種製作半導體裝置的方法,所述方法包括在基底上沈積鈦系層。在所述鈦系層之上沈積高度大於10微米的鎳系層。在所述鎳系層的上表面上直接形成焊料層且所述焊料層接觸所述鎳系層的上表面。在實施例中,所述鈦系層是藉由濺鍍沈積而成。在實施例中,所述方法包括在鈦系層之上濺鍍沈積的銅系層。在實施例中,所述方法包括在所述濺鍍沈積的銅系層上電鍍或化學鍍銅或銅合金層。在實施例中,鎳系層的高度對銅或銅合金層的高度的比率介於6/1至1.5/1範圍內。
前述內容概述數個實施例或實例的特徵,以使熟習此項技術者可更好地理解本發明的態樣。熟習此項技術者應瞭解,其可容易地使用本發明作為設計或修改其他製程及結構以達到與本文中所引入的實施例或實例相同的目的及/或達成相同的優勢的基礎。熟習此項技術者亦應意識到,該些等效構造並不背離本發明的精神及範疇,且其可在不背離本發明的精神及範疇的情況下在本文中做出各種改變、替代及變更。
10‧‧‧半導體裝置
15‧‧‧基底
20‧‧‧接合接墊
25‧‧‧第二金屬層/柱
30‧‧‧第一金屬層/銅或銅合金層
35‧‧‧焊料層
40‧‧‧凸塊下金屬化物
55‧‧‧凸塊結構
60‧‧‧絕緣層
D1、D2‧‧‧高度
Claims (9)
- 一種半導體裝置,包括:基底;以及至少一個凸塊結構,設置於所述基底之上,其中所述至少一個凸塊結構包括:柱,由金屬形成,所述金屬對設置於所述基底之上的焊料合金的可焊性低於銅或銅合金;焊料合金,直接形成於可焊性低於銅或銅合金的所述金屬的上表面之上且接觸所述金屬的所述上表面,其中所述焊料合金具有彎曲表面;以及銅或銅合金層,位於所述柱與所述基底之間且接觸所述柱,其中所述柱的高度大於所述銅或銅合金層的高度,且所述銅或銅合金層具有線性側壁。
- 如申請專利範圍第1項所述的半導體裝置,其中所述柱的所述高度大於10微米。
- 如申請專利範圍第1項所述的半導體裝置,其中所述柱主要由選自以下所組成的群組的金屬所形成:鋁、鉻、鐵、錳、鎂、鉬、鎳、鈮、鉭、鈦、鎢、鋅及其合金。
- 如申請專利範圍第1項所述的半導體裝置,更包括設置於所述基底與所述凸塊結構之間的凸塊下金屬化物。
- 一種半導體裝置,包括:第一基底,包括第一電路系統; 第二基底,其中所述第一基底經由包括焊料層的連接件而連接至所述第二基底,所述焊料層設置於第一柱與第二柱之間,且其中所述第一柱是由鎳系材料形成,具有大於10微米的高度;以及銅或銅合金層,設置於所述第一柱與所述第一基底之間,其中所述第一柱的所述高度大於所述銅或銅合金層的高度,所述焊料層具有彎曲表面,且所述銅或銅合金層具有線性側壁。
- 如申請專利範圍第5項所述的半導體裝置,其中所述第一柱或所述第二柱具有介於5微米至40微米範圍內的直徑。
- 如申請專利範圍第5項所述的半導體裝置,更包括位於所述第一柱與所述焊料層之間的實質上不含銅的終飾層。
- 一種製作半導體裝置的方法,包括:在基底之上形成光阻層;將所述光阻層圖案化以形成多個開口,所述多個開口暴露出所述基底;在所述多個開口中沈積可焊性低於銅或銅合金材料的金屬,在所述多個開口中沈積可焊性低於銅或銅合金材料的所述金屬之前,在所述多個開口中沈積銅或銅合金材料,其中可焊性低於銅或銅合金材料的所述金屬的高度大於所述銅或銅合金材料的高度;在所述多個開口中的可焊性低於銅或銅合金材料的所述金屬 之上形成焊料層;以及移除所述光阻層,其中所述焊料層直接接觸可焊性低於銅或銅合金材料的所述金屬。
- 如申請專利範圍第8項所述的方法,其中可焊性低於銅或銅合金材料的所述金屬的側壁與所述銅或銅合金材料的側壁對準。
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