CN103594387A - 焊盘侧壁间隔和制造焊盘侧壁间隔的方法 - Google Patents

焊盘侧壁间隔和制造焊盘侧壁间隔的方法 Download PDF

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CN103594387A
CN103594387A CN201310356763.5A CN201310356763A CN103594387A CN 103594387 A CN103594387 A CN 103594387A CN 201310356763 A CN201310356763 A CN 201310356763A CN 103594387 A CN103594387 A CN 103594387A
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photoresist
contact pad
chip
sidewall
carrier
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CN103594387B (zh
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约翰·加特鲍尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明公开了焊盘侧壁间隔和制造接触焊盘侧壁间隔的方法。实施方式包括：在衬底上形成多个接触焊盘，每个接触焊盘具有侧壁；在衬底上形成第一光致抗蚀剂；并且将第一光致抗蚀剂从衬底上去除，从而沿多个接触焊盘的侧壁形成侧壁间隔。

Description

焊盘侧壁间隔和制造焊盘侧壁间隔的方法
技术领域
本发明总体上涉及半导体器件和制造半导体器件的方法。具体地，本发明的实施方式涉及具有侧壁间隔的芯片接触焊盘和制造具有侧壁间隔的芯片接触焊盘的方法。
背景技术
功率半导体器件是用作功率电子线路中的开关或整流器的半导体器件。
功率器件的领域分为两个主要类别：状态完全取决于与其连接的外部功率电路的二端子器件（二极管）；以及状态不仅取决于其外部功率电路，还取决于其驱动端子（栅极或基极）上的信号的三端子器件。晶体管和晶闸管属于该类别。
第二种分类较不明显，但对器件性能具有较强影响：某些器件是例如肖特基二极管和MOSFET的多数载流子器件，而其他器件是例如晶闸管、双极型晶体管和IGBT的少数载流子器件。前者仅使用一种类型的载流子，而后者使用两种（即，电子和空穴）。多数载流子器件较快，但少数载流子的电荷注入允许更好的通态性能。
发明内容
根据本发明的一个实施方式，半导体器件的制造方法包括：在衬底上形成多个接触焊盘，每个接触焊盘具有侧壁；在衬底上形成第一光致抗蚀剂；以及将第一光致抗蚀剂从衬底上去除，从而沿多个接触焊盘的侧壁形成侧壁间隔。
根据本发明的另一个实施方式，半导体器件的制造方法包括：在工件（workpiece）上形成多个芯片接触焊盘，每个芯片接触焊盘具有侧壁；沿多个芯片接触焊盘的侧壁形成第一光致抗蚀剂间隔；通过切割工件形成多个芯片，每个芯片具有芯片接触焊盘。该方法进一步包括：将多个芯片中的一个芯片放置在载体上；将芯片接触焊盘接合至载体的载体接触焊盘；并且用封装材料对芯片接触焊盘进行封装。
根据本发明的另一个实施方式，半导体器件包括具有载体接触焊盘的载体和布置在载体上的芯片，芯片具有芯片接触焊盘和沿着芯片接触焊盘的侧壁的第一光致抗蚀剂侧壁间隔。半导体器件进一步包括将芯片接触焊盘与载体接触焊盘连接的连接元件，以及对芯片的至少一部分进行封装的封装材料。
附图说明
为了更完整地理解本发明及其优点，现在将结合附图对以下描述进行参考，在附图中：
图1示出了常规功率接触焊盘；
图2a示出了在芯片接触焊盘上具有侧壁的封装半导体器件的实施方式；
图2b示出了在芯片接触焊盘上具有侧壁的封装半导体器件的进一步实施方式；
图3示出了芯片的顶表面的一部分的详细视图的实施方式；
图4a示出了半导体器件的制造方法的实施方式的流程图；以及
图4b示出了半导体器件的制造方法的实施方式的流程图。
具体实施方式
下文将对当前优选实施方式的制造和使用进行详细讨论。然而，应理解的是，本发明提供的多个可应用的发明概念可在各种特定环境下实施。所讨论的特定实施方式仅为制造和使用本发明的特定方式的举例说明，并不限定本发明的范围。
将关于特定环境下的实施方式（即，功率接触焊盘的光致抗蚀剂侧壁间隔）来描述本发明。然而，本发明还可应用于其他接触元件的其他类型的侧壁间隔。
图1示出了常规功率接触焊盘120。常规功率接触焊盘120封装在模塑封料（mold compound）140内。常规功率接触焊盘120具有的问题在于，模塑封料无法完全粘合至钝化层110和芯片接触焊盘的侧壁。常规功率接触焊盘120具有的进一步的问题在于，功率接触焊盘周围的聚酰亚胺130的量造成了大量的应力和大量的晶圆翘曲。最后，常规功率接触焊盘120具有的问题在于，模塑封料的粗颗粒无法完全填充相邻功率接触焊盘120之间的小空间125。
因此，本领域中需要侧壁间隔对钝化层和芯片接触焊盘的侧壁提供适当粘合的封装的功率半导体器件。另外，还需要在相邻芯片接触焊盘之间提供适当介电强度（击穿每单位厚度的绝缘体所需的电位）的封装的功率半导体器件。
本发明的实施方式提供了具有光致抗蚀剂侧壁间隔的芯片接触焊盘。本发明的进一步实施方式提供了沿侧壁的下部，而非沿侧壁的上部的侧壁间隔。本发明的另一实施方式提供了彼此面对的靠近地隔开的芯片接触焊盘的侧壁上的侧壁间隔，其中芯片接触焊盘之间的大部分空间用模塑封料填充。
本发明的实施方式提供了通过将正光致抗蚀剂沉积在芯片接触焊盘上，并用散焦光对正光致抗蚀剂曝光而沿芯片接触焊盘形成光致抗蚀剂侧壁间隔的方法。本发明的进一步实施方式提供了通过将负光致抗蚀剂沉积在芯片接触焊盘上并在不对负光致抗蚀剂曝光的情况下使负光致抗蚀剂部分显影，来沿芯片接触焊盘形成光致抗蚀剂侧壁间隔的方法。
优点在于芯片接触焊盘的侧壁间隔可通过在没有光刻掩模的情况下曝光光致抗蚀剂来形成。进一步的优点在于，两个靠近地隔开侧壁间隔之间的介电强度增加并且漏电流减少。最后的优点在于，由于光致抗蚀剂的量有限，晶圆翘曲减小。
图2a示出了封装的功率半导体器件200的实施方式。芯片210布置在载体220上。芯片210具有第一主表面211和第二主表面212。芯片接触焊盘215布置在第一主表面211上。侧壁间隔217设于芯片接触焊盘215的侧壁上。芯片接触焊盘215经由接合线230与载体接触焊盘225电连接。芯片210用模塑封料240封装。
芯片210包括半导体衬底。半导体衬底可以是例如硅或锗的单晶衬底，或例如SiGe、GaAs、InP或SiC的复合衬底。可在半导体衬底上设置一个或多个互连金属化层。金属层的顶表面上布置有钝化层以便密封芯片。钝化层可包括例如SiN。芯片的顶表面是第一主表面211。半导体衬底的底部是芯片的第二主表面212。芯片接触焊盘215布置在芯片210的顶表面211上。
芯片210可包括集成电路（IC）或例如单个半导体器件的分立器件。例如，芯片210可包括例如双极型晶体管、绝缘栅双极型晶体管（IGBT）、功率MOSFET、晶闸管或二极管的功率半导体器件。
载体220可包括衬底、引线框架或印制电路板（PCB）。载体220可包括载体接触焊盘226。载体接触焊盘225包括例如金属的导电材料。例如，载体接触焊盘225包括铜和/或镍。
芯片210附接至载体220。例如，芯片210的第二主表面212用粘合带接合或胶合至载体220的顶表面。备选地，芯片210的第二主表面212使用例如树脂的电绝缘粘合剂接合或胶合至载体220的顶表面。
芯片接触焊盘215经由接合线230与载体接触焊盘225电连接。接合线230可包括铜（Cu）、金（Au）或铝（Al）。接合线230可经由球焊工艺或楔焊工艺与芯片接触焊盘215和/或载体接触焊盘225连接。下文将关于图3来讨论芯片接触焊盘215的实施方式。
模塑封料240封装芯片210并且覆盖在载体220的顶表面上。模塑封料240可包括热固材料或热塑材料。模塑封料可包括粗粒材料颗粒。
在一个实施方式中，芯片210可附接至散热器（未显示）。散热器可设于芯片210与载体220之间。在一个实施方式中，载体220可包括散热器。封装和散热器提供了通过将热量导向外部环境而将热量从芯片210中去除的方法。一般来说，大电流器件具有大的裸片和封装表面积，以及低的热阻。
图2b示出了封装的功率半导体器件250的另一个实施方式。芯片260布置在载体270上。芯片260具有第一主表面261和第二主表面262。芯片接触焊盘265布置在第一主表面261上。侧壁间隔267设于芯片接触焊盘265的侧壁上。芯片接触焊盘265经由焊球280与载体接触焊盘275电连接。芯片260用模塑封料290封装。
除芯片260与载体270之间的电连接之外，图2b的实施方式可包括与关于图2a来描述的相似或相同的材料和元件。在图2b的实施方式中，芯片260使用焊接凸点与载体270电连接。备选地，可使用金凸点、模制立柱（molded stud）或导电聚合物。芯片260通过倒装芯片布置来放置在载体270上，使得第一主表面261面向载体270的顶表面，而第二主表面262背向载体顶表面。焊接凸点可以是铅基或无铅的焊接凸点。
图3示出了图2a和2b的实施方式的芯片210的顶表面211的一部分的详细视图的实施方式。芯片接触焊盘320布置在钝化层312上。芯片接触焊盘320可通过接触通孔与互连金属化层堆叠的顶部金属电连接。芯片接触焊盘320可由金属制成。例如，芯片接触焊盘320可包括铜（Cu）层321。备选地，芯片接触焊盘320可包括铜合金层321，该铜合金层321包括预定比例的Cr、Al、Si、Ti、Fe、Ag和/或P。
芯片接触焊盘320进一步包括金属材料层堆叠322。金属材料层堆叠322可封装铜层或铜合金层321。金属材料层堆叠322可包括至少一种金属材料。金属材料层堆叠322的第二层324可以是可选的钯（Pd）层或可选的钯合金层。金属材料层堆叠322的第三层325可以是可选的金（Au）层或可选的金合金层。金属材料层堆叠322可包括多于三个的金属层。
芯片接触焊盘可以包括约20μm至约500μm的宽度d1和约1μm至约50μm的高度h。备选地，高度h可以是约6μm至约20μm。从芯片接触焊盘的最上金属层的左侧壁到芯片接触焊盘的最上金属层的右侧壁测量宽度d1。从钝化层的顶表面到芯片接触焊盘的顶表面测量芯片接触焊盘的高度d2。
侧壁间隔332可沿金属材料层堆叠322的第一金属层323、第二金属层324或第三金属层325布置。侧壁间隔332可布置在芯片接触焊盘320的下部，而不是芯片接触焊盘320的上部。例如，侧壁间隔332布置在高度h的偏下30%的部分，或高度h的偏下50%部分。侧壁间隔332可包括绝缘材料。绝缘材料可包括比模塑封料340更高的介电强度（在以下讨论）。绝缘材料可以是正光致抗蚀剂、负光致抗蚀剂、聚酰亚胺或PBO（聚苯并噁唑，Poly-Benz-Oxazole）。在一个实施方式中，侧壁间隔332与可选的钯层324直接相邻（并且如果没有钯层324，则与镍层323直接相邻）地放置。金层325可仅覆盖芯片接触焊盘320的一部分，例如，由侧壁间隔332覆盖的部分之外的部分。
在一个实施方式中，两个芯片接触焊盘320可彼此相邻地放置，并由形成空间237的小宽度d2彼此分隔。侧壁间隔332可能覆盖或可能不覆盖沿两个芯片接触焊盘320之间的钝化层312的整个宽度d2。备选地，钝化层312不覆盖整个宽度d2，且不在宽度d2的中心部分暴露于模塑封料340。
第二侧壁间隔334可沿芯片接触焊盘320的侧壁布置在第一侧壁间隔332上。第二侧壁间隔334可沿侧壁（包括侧壁的上部）布置。第二侧壁间隔334可包括绝缘材料。绝缘材料可包括比模塑封料340更高的介电强度（在以下讨论）。绝缘材料可以是正光致抗蚀剂、负光致抗蚀剂、聚酰亚胺或PBO（聚苯并噁唑）。在一个实施方式中，侧壁间隔334与可选的钯层324直接相邻（如果没有钯层324，则与镍层323直接相邻）。金层325可仅覆盖芯片接触焊盘的一部分，例如，除第一侧壁间隔332和第二侧壁间隔334覆盖的部分之外的部分。第二侧壁间隔334可包括与第一侧壁间隔332相同的材料。
第二侧壁间隔334可仅沿芯片接触焊盘320的外侧壁（例如，不面向空间327的侧壁）布置。第二侧壁间隔334可包括比芯片接触焊盘更高的拓扑。
模塑封料340包围芯片接触焊盘320和第一和第二侧壁间隔332/334。模塑封料340可填充靠近地隔开芯片接触焊盘320之间的大部分空间327。模塑封料340可填充靠近地隔开芯片接触焊盘320之间的空间327的中心部分，并可与钝化层312的一部分的顶表面直接接触。
图4a示出了制造具有带有侧壁间隔的芯片接触焊盘的半导体器件的方法的实施方式的流程图400。在第一步骤410中，在工件上形成多个芯片接触焊盘。工件可以是晶圆、衬底或印制电路板（PCB）。在一个实施方式中，衬底可包括半导体材料或组合物材料，以及布置在其上的一个或多个互连金属化层。钝化层布置在互连金属化层上而芯片接触焊盘布置在钝化层上。芯片接触焊盘通过接触通孔与互连金属化层的最上金属层连接。在另一个实施方式中，衬底可包括由嵌入与例如环氧树脂预浸料坯一起层压的绝缘层的薄金属箔制成的导电层。
在一个实施方式中，铜层或铜合金层在钝化层上掩蔽。例如，通过首先形成晶种层并随后以无电镀处理沉积铜/铜合金，来形成铜或铜合金层。芯片接触焊盘可进一步包括金属材料层堆叠。金属材料层堆叠也可通过无电镀处理形成。金属材料层堆叠可包括镍（Ni）层或镍合金层。金属层堆叠可进一步包括可选的钯（Pd）层或可选的钯合金层。最后，金属层堆叠可包括可选的金层或可选的金合金层。在一个实施方式中，可在形成第一和可选第二侧壁间隔之后形成金或金合金层。备选地，芯片接触焊盘可通过例如电化学镀或物理气相沉积（PVD）的其他沉积处理形成。
随后，在412中，用第一光致抗蚀剂涂覆芯片接触焊盘。第一光致抗蚀剂可以是正光致抗蚀剂。正光致抗蚀剂可布置在或旋涂在芯片接触焊盘上。正光致抗蚀剂是暴露于光线下的光致抗蚀剂的部分变得可溶于显影剂的一种光致抗蚀剂。正光致抗蚀剂可以是聚酰亚胺或PBO。
用散焦光对正光致抗蚀剂曝光（步骤414）。例如，对正光致抗蚀剂曝光，使得沿芯片接触焊盘的侧壁的下部和底部不暴露在光线下。曝光光可在与钝化层的顶表面相距一定距离的位置聚焦。例如，曝光光在芯片接触焊盘的顶表面的水平面的高度h上聚焦。可在不使用光刻掩模的情况下，或者备选地，可在使用不具有任何结构的虚拟光刻掩模的情况下对正光致抗蚀剂曝光。随后使正光致抗蚀剂显影和固化（步骤416）。在一个实施方式中，侧壁间隔形成于芯片接触焊盘的侧壁的下部，而非侧壁的上部。例如，侧壁间隔可位于芯片接触焊盘侧壁的高度h的一半以下的侧壁区域上。
在一个可选步骤中，第一侧壁间隔和芯片接触焊盘涂覆有可选的第二光致抗蚀剂。第二光致抗蚀剂可布置在或旋涂在芯片接触焊盘和第一侧壁间隔上。第二光致抗蚀剂可以是正光致抗蚀剂或负光致抗蚀剂。第二光致抗蚀剂若为正光致抗蚀剂，则对其进行与第一光致抗蚀剂相似的处理，或者，进行与下文进一步所述的负光致抗蚀剂相似的处理。第二光致抗蚀剂可经由光刻掩模来构造。第二光致抗蚀剂可与第一光致抗蚀剂相同或不同。第一和第二侧壁间隔有利地防止了铜或铜合金层和/或镍或镍合金层上的腐蚀性侵蚀。
在下一个步骤418中，将工件分成或切割成多个芯片或裸片。每个芯片包括至少一个芯片接触焊盘，芯片接触焊盘包括第一正光致抗蚀剂侧壁间隔以及可选的第二侧壁间隔。
在下一个步骤420中，将多个芯片中的一个芯片放置在例如半导体衬底、引线框架或印制电路板（PCB）的载体上。芯片可通过胶合或焊接附接到载体。例如，可应用粘合带将芯片附接至载体。在一个实施方式中，芯片在芯片接触焊盘背向载体的情况下接合至载体。在另一个实施方式中，芯片在芯片接触焊盘面向载体的情况下接合至载体。
随后，可将芯片接触焊盘接合至载体的载体接触焊盘（步骤422）。例如，将芯片的芯片接触焊盘丝焊到载体的载体接触焊盘。备选地，将芯片的芯片接触焊盘焊接到载体的载体接触焊盘。在一个实施方式中，当接合铜线时，芯片的芯片接触焊盘可不包括可选的钯层，而当接合铝线时，可包括可选的钯层。可使用或不使用可选的钯层来焊接金线。
最后，在步骤424，用封装材料封装芯片。封装材料可以是模塑封料。模塑封料可包括热固材料或热塑材料。模塑封料可包括粗粒材料。
图4b示出了制造具有带有侧壁间隔的芯片接触焊盘的半导体器件的方法的实施方式的流程图450。在第一步骤430中，多个芯片接触焊盘形成于工件上。工件可以是晶片、衬底或印制电路板（PCB）。在一个实施方式中，衬底可包括半导体材料或化合物材料，以及布置在其上的一个或多个互连金属化层。钝化层布置在互连金属化层上，而芯片接触焊盘布置在钝化层上。芯片接触焊盘通过接触通孔与互连金属化层的最上金属层连接。在另一个实施方式中，衬底可包括由嵌入与例如环氧树脂预浸料坯一起层压的绝缘层的薄金属箔制成的导电层。
在一个实施方式中，铜层或铜合金层在钝化层上掩蔽。例如，通过首先形成晶种层并随后在无电镀处理中沉积铜/铜合金，来形成铜或铜合金层。芯片接触焊盘可进一步包括金属材料层堆叠。金属材料层堆叠也可通过无电镀处理形成。金属材料层堆叠可包括镍（Ni）层或镍合金层。金属层堆叠可进一步包括可选的钯（Pd）层或可选的钯合金层。最后，金属层堆叠可包括可选的金层或可选的金合金层。备选地，芯片接触焊盘可通过例如电化学电镀或物理气相沉积（PVD）的其他沉积处理形成。
接下来，在432中，用第一光致抗蚀剂涂覆芯片接触焊盘。第一光致抗蚀剂可以是负光致抗蚀剂。负光致抗蚀剂可布置在或旋涂在芯片接触焊盘上。负光致抗蚀剂是一种暴露于光线下的光致抗蚀剂部分变得不溶于显影剂的光致抗蚀剂。负光致抗蚀剂可以是聚酰亚胺。
在不对负光致抗蚀剂曝光的情况下使负光致抗蚀剂显影（步骤434）。不使负光致抗蚀剂完全显影。例如，仅使负光致抗蚀剂在高度h上方显影。备选地，使负光致抗蚀剂在高度h的30%以上或50%以上显影。随后对负光致抗蚀剂进行固化（步骤436）。在一个实施方式中，侧壁间隔形成于芯片接触焊盘的侧壁的下部，而非侧壁的上部。例如，侧壁间隔可放置在高度h的50%以下或高度h的30%以下的侧壁上的区域中。
在一个可选的步骤中，芯片接触焊盘和第一侧壁间隔用可选的第二光致抗蚀剂涂覆。第二光致抗蚀剂可布置在或旋涂在芯片接触焊盘和第一侧壁间隔上。第二光致抗蚀剂可以是正光致抗蚀剂或负光致抗蚀剂。第二光致抗蚀剂若为正光致抗蚀剂，则对其进行与图4a的实施方式所述的第一光致抗蚀剂相似的处理，或者，进行与该实施方式所述的负光致抗蚀剂相似的处理。第二光致抗蚀剂可与第一光致抗蚀剂相同或不同。第一和第二侧壁间隔有利地防止了铜或铜合金层和/或镍或镍合金层上的腐蚀性侵蚀。
在下一个步骤438中，将工件分成或切割成多个芯片或裸片。每个芯片包括至少一个芯片接触焊盘，芯片接触焊盘包括第一负光致抗蚀剂侧壁间隔以及可选的第二侧壁间隔。
在下一个步骤440中，将多个芯片中的一个芯片放置在例如半导体衬底、引线框架或印制电路板（PCB）的载体上。芯片可通过胶合或焊接附接在载体上。例如，可应用粘合带将芯片附接在载体上。在一个实施方式中，芯片在芯片接触焊盘背向载体的情况下接合至载体。在另一个实施方式中，芯片在芯片接触焊盘面向载体的情况下接合至载体。
随后，可将芯片接触焊盘接合至载体的载体接触焊盘（步骤442）。例如，将芯片的芯片接触焊盘丝焊或焊接到载体的载体接触焊盘。在一个实施方式中，芯片的芯片接触焊盘在焊接铜线或金线时可不包括可选的钯层，而在焊接铝线时可包括可选的钯层。
最后，在步骤444中，用封装材料封装芯片。封装材料可以是模塑封料。模塑封料可包括热固材料或热塑材料。模塑封料可包括粗粒材料。
尽管对本发明及其优点进行了详细说明，但应理解的是，在不偏离由所附权利要求限定的本发明的实质和范围的条件下，可进行各种改变、替换和变更。
另外，本申请的范围并不限于本说明书所述的处理、机器、制造、组合物、手段、方法和步骤的特定实施方式。本领域的普通技术人员应从本发明的公开中理解，与本文描述的对应实施方式执行基本相同的功能或获得基本相同的结果的，现有的或以后开发的处理、机器、制造、组合物、手段、方法或步骤，可根据本发明来利用。由此，所附权利要求意图在其范围内包括这些处理、机器、制造、组合物、手段、方法或步骤。

Claims (23)

1.一种制造半导体器件的方法，所述方法包括：
在衬底上形成多个接触焊盘，每个接触焊盘具有侧壁；
在所述衬底上形成第一光致抗蚀剂；并且
将所述第一光致抗蚀剂从所述衬底上去除，从而沿所述多个接触焊盘的侧壁形成侧壁间隔。
2.根据权利要求1所述的方法，其中，形成所述第一光致抗蚀剂包括形成正光致抗蚀剂。
3.根据权利要求2所述的方法，其中，去除所述第一光致抗蚀剂包括：用散焦光对所述正光致抗蚀剂曝光，并使所述正光致抗蚀剂显影。
4.根据权利要求1所述的方法，其中，形成所述第一光致抗蚀剂包括形成负光致抗蚀剂。
5.根据权利要求4所述的方法，其中，去除所述第一光致抗蚀剂包括：在不对所述负光致抗蚀剂曝光的情况下使所述负光致抗蚀剂显影。
6.根据权利要求1所述的方法，其中，所述多个接触焊盘中的两个接触焊盘以线宽分隔彼此相邻地放置，所述方法进一步包括：仅沿背向所述线宽的所述两个接触焊盘的侧壁形成第二光致抗蚀剂。
7.根据权利要求1所述的方法，其中，形成所述多个接触焊盘包括：形成掩蔽的铜或铜合金层，并在所述掩蔽的铜或铜合金层上形成金属材料层堆叠，所述金属材料层堆叠包括第一镍（Ni）基层。
8.一种制造半导体器件的方法，所述方法包括：
在工件上形成多个芯片接触焊盘，每个芯片接触焊盘具有侧壁；
沿所述多个芯片接触焊盘的侧壁形成第一光致抗蚀剂间隔；
通过切割所述工件而形成多个芯片，每个芯片具有芯片接触焊盘；
将所述多个芯片中的芯片放置在载体上；
将所述芯片接触焊盘接合至所述载体的载体接触焊盘；并且
用封装材料封装所述芯片接触焊盘。
9.根据权利要求8所述的方法，其中，形成所述第一光致抗蚀剂间隔包括：形成第一正光致抗蚀剂间隔。
10.根据权利要求9所述的方法，其中，形成所述第一正光致抗蚀剂间隔包括：
将所述正光致抗蚀剂布置在所述工件上；
用散焦光对所述正光致抗蚀剂曝光；
使所述正光致抗蚀剂显影；以及
固化所述正光致抗蚀剂。
11.根据权利要求8所述的方法，其中，形成所述第一光致抗蚀剂间隔包括形成第一负光致抗蚀剂间隔。
12.根据权利要求11所述的方法，其中，形成所述第一负光致抗蚀剂间隔包括：
将所述负光致抗蚀剂布置在所述工件上；
在不对所述负光致抗蚀剂曝光的情况下使所述负光致抗蚀剂显影；并且
固化所述负光致抗蚀剂。
13.根据权利要求8所述的方法，进一步包括在所述多个芯片接触焊盘的侧壁上的所述第一光致抗蚀剂间隔上形成第二间隔。
14.根据权利要求13所述的方法，其中，所述第一光致抗蚀剂间隔和所述第二间隔包括同一材料。
15.根据权利要求8所述的方法，其中，形成所述多个芯片接触焊盘包括：形成掩蔽的铜或铜合金层，并在所述掩蔽的铜或铜合金层上形成金属材料层堆叠，所述金属材料层堆叠包括第一镍（Ni）基层和第二金（Au）层。
16.一种半导体器件，包括：
载体，具有载体接触焊盘；
芯片，布置在所述载体上，所述芯片具有芯片接触焊盘和沿着所述芯片接触焊盘的侧壁的第一光致抗蚀剂侧壁间隔。
连接元件，将所述芯片接触焊盘与所述载体接触焊盘连接；以及
封装材料，封装所述芯片的至少一部分。
17.根据权利要求16所述的半导体器件，进一步包括布置在所述第一侧壁间隔上的第二侧壁间隔。
18.根据权利要求17所述的半导体器件，其中，所述第一光致抗蚀剂侧壁间隔包括第一聚酰亚胺，并且其中，所述第二侧壁间隔包括第二聚酰亚胺。
19.根据权利要求18所述的半导体器件，其中，所述第一聚酰亚胺与所述第二聚酰亚胺相同。
20.根据权利要求17所述的半导体器件，其中，所述第一光致抗蚀剂侧壁间隔包括第一PBO（聚苯并噁唑），并且其中，所述第二侧壁间隔包括第二PBO。
21.根据权利要求20所述的半导体器件，其中，所述第一PBO与所述第二PBO相同。
22.根据权利要求16所述的半导体器件，其中，所述连接元件包括配线。
23.根据权利要求16所述的半导体器件，其中，所述芯片是功率半导体芯片。
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