DE102013108813A1 - Anschlussflächen mit Seitenwandabstandshaltern und Verfahren zum Herstellen von Anschlussflächen mit Seitenwandabstandshaltern - Google Patents
Anschlussflächen mit Seitenwandabstandshaltern und Verfahren zum Herstellen von Anschlussflächen mit Seitenwandabstandshaltern Download PDFInfo
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- DE102013108813A1 DE102013108813A1 DE201310108813 DE102013108813A DE102013108813A1 DE 102013108813 A1 DE102013108813 A1 DE 102013108813A1 DE 201310108813 DE201310108813 DE 201310108813 DE 102013108813 A DE102013108813 A DE 102013108813A DE 102013108813 A1 DE102013108813 A1 DE 102013108813A1
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Abstract
Es werden eine Chip-Anschlussfläche (215) und ein Verfahren zum Herstellen einer Chip-Anschlussfläche (215) offenbart. Eine Ausführungsform der vorliegenden Erfindung enthält das Bilden mehrerer Anschlussflächen (215) auf einem Werkstück, wobei jede Anschlussfläche (215) untere Seitenwände und obere Seitenwände besitzt, und das Verringern einer unteren Breite jeder Anschlussfläche (215), so dass eine obere Breite jeder (215) Anschlussfläche größer ist als die untere Breite. Das Verfahren enthält ferner das Bilden eines Photoresists über den mehreren Anschlussflächen (215) und das Entfernen von Abschnitten des Photoresists, um dadurch längs der unteren Seitenwände Seitenwandabstandshalter (217) zu bilden.
Description
- Die vorliegende Erfindung bezieht sich allgemein auf eine Halbleitervorrichtung und auf ein Verfahren zum Herstellen einer Halbleitervorrichtung. Insbesondere beziehen sich Ausführungsformen der Erfindung auf Chip-Anschlussflächen, die Seitenwandabstandshalter besitzen, und auf ein Verfahren zum Herstellen von Chip-Anschlussflächen, die Seitenwandabstandshalter besitzen.
- Leistungshalbleitervorrichtungen sind Halbleitervorrichtungen, die als Schalter oder Gleichrichter in elektronischen Leistungsschaltungen verwendet werden.
- Der Bereich von Leistungsvorrichtungen ist in zwei Hauptkategorien unterteilt: die Zweifachanschluss-Vorrichtungen (Dioden), deren Zustand vollständig von der externen Leistungsschaltung abhängt, mit der sie verbunden sind; und die Dreifachanschluss-Vorrichtungen, deren Zustand nicht nur von ihrer externen Leistungsschaltung, sondern auch von dem Signal an ihrem Ansteuerungsanschluss (Gate oder Basis) abhängt. Zu dieser Kategorie gehören Transistoren und Thyristoren.
- Eine zweite Klassifizierung ist weniger offensichtlich, sie hat jedoch auf die Vorrichtungsleistung einen starken Einfluss: einige Vorrichtungen sind Majoritätsträgervorrichtungen wie etwa eine Schottky-Diode und ein MOSFET, während andere Vorrichtungen Minoritätsträgervorrichtungen wie etwa ein Thyristor, ein Bipolartransistor und ein IGBT sind. Die Ersteren verwenden nur einen Typ von Ladungsträgern, während die Letzteren beide (d. h. Elektronen und Löcher) verwenden. Die Majoritätsträgervorrichtungen sind schneller, hingegen erlaubt die Ladungsinjektion von Minoritätsträgervorrichtungen eine bessere Durchschaltleistung.
- Gemäß einer Ausführungsform der vorliegenden Erfindung weist ein Verfahren zum Herstellen einer Halbleitervorrichtung auf das Bilden mehrerer Anschlussflächen auf einem Werkstück, wobei jede Anschlussfläche untere Seitenwände und obere Seitenwände besitzt, und das Verringern einer unteren Breite jeder Anschlussfläche, so dass eine obere Breite jeder Anschlussfläche größer ist als die untere Breite. Das Verfahren weist ferner das Bilden eines Photoresists auf den mehreren Anschlussflächen und das Entfernen von Abschnitten des Photoresists auf, um dadurch längs der unteren Seitenwände Seitenwandabstandshalter zu bilden.
- In einer Ausgestaltung kann das Bilden des Photoresists das Bilden eines positiven Photoresists aufweisen. In noch einer Ausgestaltung kann das Entfernen des positiven Photoresists das Belichten des positiven Photoresists und das Entwickeln des positiven Photoresists aufweisen. In noch einer Ausgestaltung kann das Belichten des positiven Photoresists das Belichten des positiven Photoresists ohne Verwendung einer Lithographiemaske aufweisen. In noch einer Ausgestaltung kann das Belichten des positiven Photoresists das Belichten des positiven Photoresists mit einer Blind-Lithographiemaske aufweisen. In noch einer Ausgestaltung kann der Photoresist ein Polyimid oder ein PBO (Poly-Benz-Oxazol) sein. In noch einer Ausgestaltung kann das Bilden der mehreren Anschlussflächen das Bilden einer Kupferschicht oder einer Kupferlegierungsschicht und dann das Bilden eines Stapels aus Schichten metallischer Materialien aufweisen, wobei der Stapel aus Schichten metallischer Materialien Nickel (Ni) und Gold (Au) enthält. In noch einer Ausgestaltung kann das Bilden der Kupferschicht das elektrochemische Plattieren des Kupfers umfasst, wobei das Bilden des Stapels aus Schichten metallischer Materialien das elektrochemische Plattieren von Nickel (Ni), dann das elektrochemische Plattieren von Palladium (Pd) und dann das Elektroplattieren von Gold (Au) aufweisen.
- Gemäß einer Ausführungsform der vorliegenden Erfindung weist ein Verfahren zum Herstellen einer Halbleitervorrichtung das Bilden mehrerer Chip-Anschlussflächen auf einem Werkstück auf, wobei jede Chip-Anschlussfläche einen oberen Abschnitt und einen unteren Abschnitt besitzt, wobei der obere Abschnitt von dem unteren Abschnitt seitlich vorsteht und wobei jede Chip-Anschlussfläche obere Seitenwände längs des oberen Abschnitts und untere Seitenwände längs des unteren Abschnitts aufweist. Das Verfahren enthält ferner das Bilden von Photoresist-Abstandshaltern an den unteren Seitenwänden der mehreren Chip-Anschlussflächen, das Bilden mehrerer Chips durch Schneiden des Werkstücks, wobei jeder Chip eine Kontaktierungsanschlussfläche besitzt, und das Anordnen eines Chips der mehreren Chips auf einem Träger. Das Verfahren weist schließlich das Kontaktieren der Chip-Anschlussfläche mit der Träger-Anschlussfläche des Trägers und das Einkapseln des Chips mit einem Einkapselungsmaterial auf.
- In einer Ausgestaltung kann das Bilden des Photoresist-Abstandshalters das Bilden eines positiven Photoresists auf dem Werkstück und das Entfernen von Abschnitten des positiven Photoresists von dem Werkstück und dadurch das Bilden von Abstandshaltern aus positivem Photoresist aufweisen. In noch einer Ausgestaltung kann das Entfernen des positiven Photoresists das Belichten des positiven Photoresists mit Licht, das Entwickeln des positiven Photoresists und das Härten des positiven Photoresists aufweisen. In noch einer Ausgestaltung kann das Belichten des positiven Photoresists mit Licht das Belichten des positiven Photoresists ohne Verwendung einer Lithographiemaske oder das Belichten des positiven Photoresists mit einer Blind-Lithographiemaske aufweisen. In noch einer Ausgestaltung kann der untere Abschnitt der Chip-Anschlussflächen Kupfer oder eine Kupferlegierung enthalten, der obere Abschnitt der Chip-Anschlussflächen einen Stapel aus Schichten metallischer Materialien enthält und der Stapel aus Schichten metallischer Materialien eine Nickelschicht und eine Goldschicht (Au-Schicht) enthält. In noch einer Ausgestaltung kann der Stapel aus Schichten metallischer Materialien ferner eine Palladiumschicht (Pd) enthalten.
- Gemäß einer Ausführungsform der vorliegenden Erfindung enthält eine Halbleitervorrichtung einen Träger, einen auf dem Träger angeordneten Chip und eine erste Chip-Anschlussfläche, die auf dem Chip angeordnet ist, wobei die erste Chip-Anschlussfläche untere Seitenwände und obere Seitenwände besitzt, wobei eine untere Breite der ersten Chip-Anschlussfläche kleiner ist als eine obere Breite der ersten Chip-Anschlussfläche, wobei die untere Breite den unteren Seitenwänden entspricht und die obere Breite den oberen Seitenwänden entspricht. Die Halbleitervorrichtung enthält ferner Photoresist-Seitenwandabstandshalter, die längs der unteren Seitenwände der ersten Chip-Anschlussfläche angeordnet sind, und ein Einkapselungsmaterial, das den Chip einkapselt.
- In einer Ausgestaltung kann die erste Chip-Anschlussfläche eine Kupferschicht oder eine Kupferlegierungsschicht, die die unteren Seitenwände besitzt, aufweisen. In noch einer Ausgestaltung kann die erste Chip-Anschlussfläche einen Stapel aus Schichten metallischer Materialien zwischen den oberen Seitenwänden aufweisen, wobei der Stapel aus Schichten metallischer Materialien eine Nickelschicht (Ni-Schicht) und eine Goldschicht (Au-Schicht) enthält. In noch einer Ausgestaltung können die Photoresist-Seitenwandabstandshalter Seitenwandabstandshalter aus einem positiven Photoresist sein. In noch einer Ausgestaltung kann der Träger eine erste Träger-Anschlussfläche aufweisen und die erste Chip-Anschlussfläche kann mit der ersten Träger-Anschlussfläche elektrisch verbunden sein. In noch einer Ausgestaltung kann der Chip eine zweite Chip-Anschlussfläche aufweisen und der Träger kann eine zweite Träger-Anschlussfläche aufweisen, wobei die zweite Chip-Anschlussfläche mit der zweiten Träger-Anschlussfläche elektrisch verbunden ist und wobei die ersten und die zweiten Chip-Anschlussflächen mit den ersten bzw. zweiten Träger-Anschlussflächen über Drähte elektrisch verbunden sind. In noch einer Ausgestaltung kann der Chip eine zweite Chip-Anschlussfläche aufweisen und der Träger kann eine zweite Träger-Anschlussfläche aufweisen, wobei die zweite Chip-Anschlussfläche mit der zweiten Träger-Anschlussfläche elektrisch verbunden ist und wobei die erste und die zweite Chip-Anschlussfläche mit der ersten bzw. der zweiten Träger-Anschlussfläche über Lötmittel elektrisch verbunden sind.
- Für ein umfassenderes Verständnis der vorliegenden Erfindung und ihrer Vorteile wird nun auf die folgenden Beschreibungen Bezug genommen, die in Verbindung mit den beigefügten Zeichnungen gegeben werden, in denen:
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1 herkömmliche Chip-Anschlussflächen zeigt; -
2a eine Ausführungsform einer in einem Gehäuse verbauten Halbleitervorrichtung mit Seitenwandabstandshaltern auf Chip-Anschlussflächen zeigt; -
2b eine weitere Ausführungsform einer in einem Gehäuse verbauten Halbleitervorrichtung mit Seitenwandabstandshaltern auf Chip-Anschlussflächen zeigt; -
3 eine Ausführungsform einer detaillierten Ansicht eines Abschnitts der oberen Oberfläche eines Chips zeigt; und -
4 einen Ablaufplan einer Ausführungsform eines Verfahrens zum Herstellen einer Halbleitervorrichtung, die Chip-Anschlussflächen mit Seitenwandabstandshaltern besitzt, zeigt. - Im Folgenden werden die Herstellung und die Verwendung der derzeit bevorzugten Ausführungsformen im Einzelnen diskutiert. Es sollte jedoch anerkannt werden, dass die vorliegende Erfindung viele anwendbare erfinderische Konzepte bereitstellt, die in vielen verschiedenen spezifischen Kontexten verkörpert werden können. Die diskutierten spezifischen Ausführungsformen veranschaulichen lediglich spezifische Weisen, um die Erfindung zu schaffen und zu verwenden, während sie den Schutzbereich der Erfindung nicht beschränken.
- Die vorliegende Erfindung wird mit Bezug auf Ausführungsformen in einem spezifischen Kontext, nämlich von Photoresist-Seitenwandabstandshaltern in Leistungskontaktelementen, beschrieben. Die Erfindung kann jedoch auch auf andere Typen von Seitenwandabstandshaltern anderer Kontaktelemente angewendet werden.
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1 veranschaulicht herkömmliche Leistungsanschlussflächen120 . Die herkömmlichen Leistungsanschlussflächen120 sind in eine Gießverbindung140 eingekapselt. Ein Problem bei den herkömmlichen Leistungsanschlussflächen120 besteht darin, dass die Gießverbindung nicht richtig an der Passivierungsschicht110 und an dem Palladiumoxid auf der oberen Oberfläche und an den Seitenwänden der Leistungsanschlussflächen haftet. Ein weiteres Problem bei den herkömmlichen Leistungsanschlussflächen120 besteht darin, dass die groben Partikel der Gießverbindung den Raum125 zwischen eng beabstandeten, benachbarten Leistungsanschlussflächen120 nicht richtig füllen. Schließlich besteht ein Problem bei den herkömmlichen Leistungsanschlussflächen120 darin, dass die Menge an verwendetem Polyimid130 um die herkömmlichen Leistungsanschlussflächen120 eine wesentliche Wafer-Durchbiegung erzeugt. - Daher wird auf dem Gebiet eine in einem Gehäuse verbaute Leistungshalbleitervorrichtung benötigt, in der Seitenwandabstandshalter die richtige Haftung an der Passivierungsschicht und an den Seitenwänden einer Chip-Anschlussfläche bereitstellen und die ferner die richtige dielektrische Festigkeit (elektrisches Potential, das für den Durchbruch des Isolators pro Einheitsdicke erforderlich ist) zwischen benachbarten Chip-Anschlussflächen bereitstellt.
- Eine Ausführungsform der Erfindung schafft eine Chip-Anschlussfläche, die eine Unterschneidung besitzt und daher eine geringere untere Breite und eine größere obere Breite besitzt. Eine Ausführungsform der Erfindung stellt Seitenwandabstandchalter längs Seitenwänden der unteren kleineren Breite, nicht jedoch längs der Seitenwände der oberen größeren Breite bereit. Eine weitere Ausführungsform der Erfindung stellt Seitenwandabstandshalter auf gegenüberliegenden Seitenwänden eng beabstandeter Chip-Anschlussflächen bereit, wobei der größte Teil des Raums zwischen den Chip-Anschlussflächen mit einem Einkapselungsmaterial gefüllt ist.
- Eine Ausführungsform der Erfindung stellt ein Verfahren zum Bilden von Photoresist-Seitenwandabstandshaltern auf Chip-Anschlussflächen durch Ablagern eines positiven Photoresists auf Chip-Anschlussflächen und durch Belichten des positiven Photoresists ohne Verwendung einer Lithographiemaske bereit.
- Ein Vorteil besteht darin, dass die Seitenwandabstandshalter von Chip-Anschlussflächen durch Belichten eines positiven Photoresists ohne Lithographiemaske oder durch Belichten des positiven Photoresists mit einer Blind-Lithographiemaske gebildet werden können. Ein weiterer Vorteil besteht darin, dass die dielektrische Festigkeit erhöht ist und dass die Wafer-Durchbiegung verringert ist, weil weniger Photoresist verwendet wird. Ein letzter Vorteil besteht darin, dass der Seitenwandabstandshalter ohne Verwendung einer Lithographiemaske wohl definiert ist.
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2a zeigt eine Ausführungsform einer in einem Gehäuse verbauten Leistungs-Halbleitervorrichtung200 . Ein Chip210 ist auf einem Träger220 angeordnet. - Der Chip
210 besitzt eine erste Hauptoberfläche211 und eine zweite Hauptoberfläche212 . Chip-Anschlussflächen215 sind auf der ersten Hauptoberfläche211 angeordnet. Seitenwandabstandshalter217 sind an Seitenwänden der Chip-Anschlussflächen215 angeordnet. Die Chip-Anschlussflächen215 sind mit Träger-Anschlussflächen225 über Kontaktierungsdrähte230 elektrisch verbunden. Der Chip210 ist mit einem Einkapselungsmaterial240 wie etwa einer Gießverbindung eingekapselt. - Der Chip
210 enthält ein Halbleitersubstrat. Das Halbleitersubstrat kann ein Einkristallsubstrat wie etwa Silizium oder Germanium oder ein Verbundsubstrat wie etwa SiGe, GaAs, InP oder SiC sein. Auf dem Substrat können eine oder mehrere Zwischenverbindungsmetallisierungsschichten angeordnet sein. Eine Passivierungsschicht ist auf der oberen Oberfläche der Metallisierungsschichten angeordnet, um den Chip zu versiegeln. Die obere Oberfläche des Chips ist die erste Hauptoberfläche211 . Die Unterseite des Substrats ist die zweite Hauptoberfläche212 des Chips. Chip-Anschlussflächen215 sind auf der oberen Oberfläche211 des Chips210 angeordnet. - Der Chip
210 kann eine integrierte Schaltung (IC) oder eine diskrete Vorrichtung wie etwa einen einzelnen Transistor enthalten. Beispielsweise kann der Chip210 eine Leistungshalbleitervorrichtung wie etwa eine Bipolartransistor, einen Bipolartransistor mit isoliertem Gate (IGBT), einen Leistungs-MOSFET, einen Thyristor oder eine Diode enthalten. - Der Träger
220 kann ein Substrat, einen Leiterrahmen oder eine gedruckte Leiterplatte (PCB) enthalten. Der Träger220 kann Träger-Anschlussflächen225 enthalten. Die Träger-Anschlussflächen225 enthalten ein leitendes Material wie etwa ein Metall. - Beispielsweise enthalten die Träger-Anschlussflächen
225 Kupfer und Nickel. - Der Chip
210 ist an dem Träger220 durch Kleben oder Löten befestigt. Beispielsweise ist die zweite Hauptoberfläche212 des Chips210 mit einem Klebeband an der oberen Oberfläche des Trägers220 befestigt oder daran geklebt. Alternativ ist die zweite Hauptoberfläche212 des Chips210 an der oberen Oberfläche des Trägers220 unter Verwendung eines elektrisch isolierenden Klebstoffs wie etwa eines Harzes befestigt oder daran geklebt. - Die Chip-Anschlussflächen
215 sind mit den Träger-Anschlussflächen225 über Kontaktierungsdrähte230 elektrisch verbunden. Die Kontaktierungsdrähte230 können Kupfer (Cu), Gold (Au) oder Aluminium (Al) enthalten. Die Kontaktierungsdrähte230 können mit den Chip-Anschlussflächen215 und/oder den Träger-Anschlussflächen225 mittels eines Kugel- oder Keilkontaktierungsprozesses verbunden sein. Ausführungsformen der Chip-Anschlussflächen215 werden weiter unten mit Bezug auf3 diskutiert. - Ein Einkapselungsmaterial
240 kapselt den Chip210 ein und liegt über der oberen Oberfläche des Trägers220 . Das Einkapselungsmaterial240 kann eine Gießverbindung sein. Die Gießverbindung240 kann ein wärmehärtendes Material oder ein thermoplastisches Material sein. Die Gießverbindung kann grobkörnige Materialpartikel enthalten. - In einer Ausführungsform kann der Chip
210 an einem Kühlkörper befestigt sein. Der Kühlkörper kann zwischen dem Chip210 und dem Träger220 angeordnet sein. In einer Ausführungsform kann der Träger220 den Kühlkörper aufweisen. Der Gehäuseeinbau und die Kühlkörper stellen ein Mittel zum Abführen von Wärme von der Halbleitervorrichtung durch Leiten der Wärme an die äußere Umgebung bereit. Im Allgemeinen haben Vorrichtungen für hohe Ströme eine große Chipfläche und Gehäuseeinbauflächen und einen geringen Wärmewiderstand. -
2b zeigt eine weitere Ausführungsform einer in einem Gehäuse verbauten Leistungshalbleitervorrichtung250 . Auf einem Träger270 ist ein Chip260 angeordnet. Der Chip260 besitzt eine erste Hauptoberfläche261 und eine zweite Hauptoberfläche262 . Auf der zweiten Hauptoberfläche262 sind Chip-Anschlussflächen265 angeordnet. Seitenwandabstandshalter267 sind an Seitenwänden der Chip-Anschlussflächen265 angeordnet. Die Chip-Anschlussflächen265 sind mit Träger-Anschlussflächen275 über Lötkugeln280 elektrisch verbunden. Der Chip260 ist mit einem Einkapselungsmaterial290 wie etwa einer Gießverbindung eingekapselt. - Die Ausführungsform von
2b kann ähnliche oder gleiche Materialien oder Elemente wie mit Bezug auf2a beschrieben mit Ausnahme der elektrischen Verbindung zwischen dem Chip260 und dem Träger270 aufweisen. Beispielsweise kann der Chip260 eine integrierte Schaltung (IC) oder eine diskrete Vorrichtung sein. In der Ausführungsform von2b ist der Chip260 mit dem Träger270 unter Verwendung von Löthöckern elektrisch verbunden. Alternativ können Goldhöcker, gegossene Pfosten oder elektrisch leitende Polymere verwendet werden. Der Chip260 ist auf dem Träger270 in einer Flipchip-Anordnung angeordnet, so dass die erste Hauptoberfläche261 der oberen Oberfläche des Trägers270 zugewandt ist und die zweite Hauptoberfläche262 von der oberen Trägeroberfläche wegweist. Die Löthöcker können Löthöcker auf Bleibasis oder bleifreie Löthöcker sein. -
3 zeigt eine Ausführungsform einer detaillierten Ansicht eines Abschnitts der oberen Oberfläche211 des Chips210 der Ausführungsformen der2a und2b . Auf einer Passivierungsschicht312 sind Chip-Anschlussflächen320 angeordnet. Die Passivierungsschicht312 kann beispielsweise SiN enthalten. Die Chip-Anschlussflächen320 können mit einem oberen Metall des Metallisierungsschichtstapels über ein Kontaktdurchgangsloch elektrisch verbunden sein. - Die Chip-Anschlussflächen
320 können aus einem leitenden Material wie etwa einem Metall hergestellt sein. Beispielsweise können die Chip-Anschlussflächen320 eine Kupferschicht (Cu-Schicht)321 enthalten. Alternativ können die Chip-Anschlussflächen320 eine Kupferlegierungsschicht321 , die einen vorgegebenen Anteil von Cr, Al, Si, Ti, Fe, Ag, Pd und/oder Kombinationen hiervon enthält, umfassen. Die Chip-Anschlussflächen320 enthalten ferner einen Stapel322 aus Schichten metallischer Materialien. Der Stapel322 aus Schichten metallischer Materialien kann wenigstens ein metallisches Material enthalten. Beispielsweise kann eine erste Schicht des Stapels322 aus Schichten metallischer Materialien eine Ni- oder Ni-Legierungsschicht323 sein. Eine zweite Schicht des Stapels aus Schichten metallischer Materialien kann eine optionale Palladium-Schicht (Pd-Schicht) oder eine Palladiumlegierungsschicht324 sein. Eine dritte Schicht des Stapels322 aus Schichten metallischer Materialien kann eine optionale Goldschicht (Au-Schicht) oder eine Goldlegierungsschicht325 sein. Der Stapel322 aus Schichten metallischer Materialien kann mehr als drei Metallschichten umfassen. - Die Kupferschicht
321 kann erste Seitenwände oder untere Seitenwände326 enthalten und der Stapel322 aus Schichten metallischer Materialien kann zweite Seitenwände oder obere Seitenwände327 enthalten. Die Höhe h der ersten Seitenwände326 kann im Bereich von etwa 1 μm bis etwa 50 μm liegen. Alternativ kann die Höhe h der ersten Seitenwände326 im Bereich von etwa 6 μm bis etwa 20 μm liegen. Die Höhe der zweiten Seitenwände327 kann im Bereich von etwa 1 μm bis etwa 10 μm liegen. Die Chip-Anschlussfläche kann eine Pilztopologie haben. Die Kupferschicht321 besitzt eine erste Breite d1 und der Stapel322 aus Schichten metallischer Materialien besitzt eine Breite d2. Die erste Breite d1 unterscheidet sich von der zweiten Breite d2. Insbesondere ist die zweite Breite d2 größer als die erste Breite d1. Der Stapel322 aus Schichten metallischer Materialien der Chip-Anschlussflächen320 kann von der Kupferschicht321 der Chip-Anschlussflächen320 seitlich vorstehen oder über diese überhängen. Beispielsweise liegt die Breite d1 der Kupferschicht321 im Bereich von etwa 20 μm bis etwa 500 μm. Der Überhang hängt auf jeder Seite der Chip-Anschlussflächen320 über die Kupferschicht321 um eine Strecke im Bereich von etwa 0,5 μm bis etwa 1 μm über. - Längs der ersten Seitenwände
326 sind Seitenwandabstandshalter332 angeordnet, sie brauchen jedoch längs der zweiten Seitenwände327 nicht angeordnet zu sein. Die Seitenwandabstandshalter332 können ein Isolatormaterial enthalten. Das Isolatormaterial kann eine höhere dielektrische Festigkeit haben als das Binkapselungsmaterial. Das Isolatormaterial kann ein positiver Resist, z. B. PBO (Poly-Benz-Oxazol) oder ein Polyimid sein. Die Seitenwandabstandshalter332 befinden sich hauptsächlich unter dem Überhang, wo das Belichtungslicht den positiven Photoresist nicht oder nur begrenzt belichtet hat. - Ein Einkapselungsmaterial
340 umgibt die Kontakt-Chip-Anschlussflächen320 und die Seitenwandabstandshalter332 . Das Einkapselungsmaterial340 kann eine Gießverbindung sein. Die Gießverbindung340 kann den größten Teil des Raums zwischen den eng beabstandeten Kontakt-Chip-Anschlussflächen320 füllen. Die Gießverbindung340 kann einen Mittelabschnitt des Raums zwischen den eng beabstandeten Kontakt-Chip-Anschlussflächen füllen. -
4 zeigt einen Ablaufplan400 einer Ausführungsform zum Herstellen einer Halbleitervorrichtung, die Chip-Anschlussflächen mit Seitenwandabstandshaltern besitzt. In einem ersten Schritt410 werden auf einem Werkstück mehrere Chip-Anschlussflächen gebildet. Das Werkstück kann ein Substrat, ein Wafer oder eine gedruckte Leiterplatte (PCB) sein. In einer Ausführungsform kann das Substrat ein Halbleitermaterial oder ein Verbundmaterial und eine oder mehrere darauf angeordnete Zwischenverbindungsmetallisierungsschichten umfassen. Eine Passivierungsschicht ist über den Zwischenverbindungsmetallisierungsschichten angeordnet und die Chip-Anschlussflächen sind auf der Passivierungsschicht angeordnet. Die Chip-Anschlussflächen sind durch ein Kontaktdurchgangsloch mit der obersten Metallschicht der Zwischenverbindungsmetallisierungsschichten verbunden. In einer weiteren Ausführungsform kann das Substrat leitende Schichten, die aus einer dünnen Metallfolie hergestellt sind, die in Isolierschichten eingebettet sind, die beispielsweise mit einer Expoxidharz-Vorimprägnierung laminiert sind, umfassen. - In einer Ausführungsform wird eine Kupferschicht oder eine Kupferlegierungsschicht auf der Passivierungsschicht maskiert. Beispielsweise wird die Kupfer- oder Kupferlegierungsschicht zuerst durch Ausbilden einer Keimschicht und dann durch Ablagern von Kupfer/einer Kupferlegierung in einem elektrochemischen Plattierungsprozess oder einem elektrogalvanischen Plattierungsprozess gebildet. Die Chip-Anschlussflächen können ferner einen Stapel aus Schichten metallischer Materialien enthalten. Der Stapel aus Schichten metallischer Materialien kann auch durch elektrochemisches Plattieren oder elektrogalvanisches Plattieren gebildet werden. Der Stapel aus Schichten metallischer Materialien kann eine Nickelschicht (Ni-Schicht) oder eine Nickellegierungsschicht enthalten. Der Metallschichtstapel kann ferner eine optionale Palladiumschicht (Pd-Schicht) oder eine Palladiumlegierungsschicht enthalten. Schließlich kann der Metallschichtstapel eine optionale Gold- oder Goldlegierungsschicht enthalten. Alternativ können die Chip-Anschlussflächen durch andere Ablagerungsprozesse wie etwa elektrofreie Plattierungs- oder PVD-Prozesse gebildet werden.
- Als Nächstes kann bei
412 die Kupferschicht geätzt werden, nachdem die Chip-Anschlussflächen gebildet worden sind. Das Ätzen ist ein isotropes chemisches Nassätzen. Das chemische Nassätzen ist für die Passivierungsschicht und den Stapel aus Schichten metallischer Materialien selektiv. Das chemische Nassätzen verringert die Breite der Kupferschicht relativ zu der Breite des Stapels aus Schichten metallischer Materialien. Der Stapel aus Schichten metallischer Materialien steht von der Kupferschicht vor oder hängt von dieser über. Der Überhang des Stapels aus Schichten metallischer Materialien hängt von der Kupfer- oder Kupferlegierungsschicht auf jeder Seite um eine Strecke im Bereich von 0,05 μm bis etwa 1 μm über. - Ein Photoresist kann auf den Anschlussflächen angeordnet werden (Schritt
414 ). Der Photoresist kann auf den Chip-Anschlussflächen angeordnet oder darauf geschleudert werden. Der Photoresist kann ein positiver Photoresist sein. Ein positiver Photoresist ist ein Typ eines Photoresists, in dem der Abschnitt des Photoresists, der Licht ausgesetzt wird, löslich wird. - Der Photoresist kann belichtet, entwickelt und gehärtet werden (Schritt
416 ). Der Photoresist kann Licht ausgesetzt werden, ohne eine Photolithographiemaske zu verwenden. Alternativ kann der Photoresist mit einer Blind-Photolithograhiemaske ohne irgendwelchen Strukturen darauf belichtet werden. Das Licht belichtet den Photoresist mit Ausnahme des Bereichs unterhalb des Überhangs. Der Photoresist unter dem Überhang ist eine Schattenzone, wenn der Photoresist belichtet werden. Das Licht kann den Photoresist in der Nähe der Chip-Anschlussflächen nicht ausreichend belichten. In einer Ausführungsform kann das Licht dann, wenn zwei Chip-Anschlussflächen eng voneinander beabstandet sind, den Photoresist zwischen den zwei benachbarten Chip-Anschlussflächen nicht ausreichend belichten, so dass der Photoresist an diesen Stelle nicht löslich wird. In einer Ausführungsform kann der Photoresist nur in einem Bereich unter der oberen Oberfläche der Chip-Anschlussflächen zurückbleiben. - In einer weiteren Ausführungsform wird der positive Photoresist mit defokussiertem Licht belichtet. Der Fokus des Belichtungslichts kann auf ein Niveau der oberen Oberfläche der Chip-Anschlussflächen eingestellt sein. Das Licht kann den Photoresist in der Nähe des Bodens in der Chip-Anschlussflächen nicht ausreichend belichten, so dass der Photoresist in einem späteren Verarbeitungsschritt nicht entfernt wird. Der positive Photoresist wird dann entwickelt und gehärtet. Die Unterschneidung, die während des Ätzens der Kupferschicht erzeugt wird, bildet einen guten Schutz dieser Seitenwände. In einer Ausführungsform sind die Seitenwandabstandshalter nicht an den Seitenwänden des Stapels aus Schichten metallischer Materialien angeordnet.
- Im nächsten Schritt
418 wird das Werkstück vereinzelt oder in mehrere Chips oder Chipelemente geschnitten. Jeder Chip enthält wenigstens eine Chip-Anschlussfläche, die die Photoresist-Seitenwandabstandshalter enthält. Beispielsweise kann eine Diode eine einzelne Chip-Anschlussfläche enthalten, während andere Vorrichtungen zwei oder mehr Chip-Anschlussflächen enthalten können. - Im nächsten Schritt
420 wird ein Chip der mehreren Chips auf einem Träger wie etwa einem Leiterrahmen oder einer gedruckten Leiterplatte (PCB) angeordnet. Die Chips können an dem Träger durch Kleben oder Löten befestigt werden. Beispielsweise kann der Chip an dem Träger durch Aufbringen eines Klebebandes befestigt werden. In einer Ausführungsform wird der Chip an dem Träger so befestigt, dass die Chip-Anschlussflächen von dem Träger wegweisen. In einer weiteren Ausführungsform wird der Chip an dem Träger so befestigt, dass die Chip-Anschlussflächen zu dem Träger weisen. - Dann können die Chip-Anschlussflächen mit den Träger-Anschlussflächen des Trägers kontaktiert werden (Schritt
422 ). Beispielsweise werden die Chip-Anschlussflächen des Chips mit den Träger-Anschlussflächen des Trägers drahtkontaktiert. Alternativ werden die Chip-Anschlussflächen des Chips an die Träger-Anschlussflächen des Trägers gelötet. In einer Ausführungsform enthalten die Chip-Anschlussflächen des Chips, die mit den Träger-Anschlussflächen unter Verwendung von Aluminiumdrähten drahtkontaktiert werden, eine Palladiumschicht in dem Stapel aus Schichten metallischer Materialien, während die Chip-Anschlussflächen, die unter Verwendung von Kupferdrähten mit den Träger-Anschlussflächen drahtkontaktiert werden, keine Palladiumschicht aus den Schichten metallischer Materialien enthalten. - Schließlich wird im Schritt
424 der Chip mit einem Einkapselungsmaterial eingekapselt. Das Einkapselungsmaterial kann eine Gießverbindung sein. Die Gießverbindung kann ein wärmehärtendes Material oder ein thermoplastisches Material enthalten. Die Gießverbindung kann grobkörniges Material enthalten. - Obwohl die vorliegende Erfindung und ihre Vorteile im Einzelnen beschrieben worden sind, können daran selbstverständlich viele verschiedene Änderungen, Ersetzungen und Abwandlungen vorgenommen werden, ohne vom Erfindungsgedanken und vom Schutzbereich der Erfindung, der durch die beigefügten Ansprüche definiert ist, abzuweichen.
- Darüber hinaus ist der Schutzbereich der vorliegenden Anmeldung nicht auf die besonderen Ausführungsformen des Prozesses, der Maschine, der Herstellung, der Materialzusammensetzung, der Mittel, der Verfahren und der Schritte, die in der Beschreibung beschrieben worden sind, eingeschränkt. Da der Durchschnittsfachmann auf dem Gebiet anhand der Offenbarung der vorliegenden Erfindung ohne Weiteres anerkennt, können Prozesse, Maschinen, Herstellung, Materialzusammensetzungen, Mittel, Verfahren oder Schritte, die derzeit existieren oder später entwickelt werden und die im Wesentlichen die gleiche Funktion haben oder im Wesentlichen das gleiche Ergebnis wie die hier beschriebenen entsprechenden Ausführungsformen erzielen, gemäß der Erfindung verwendet werden. Daher sollen die beigefügten Ansprüche innerhalb ihres Schutzumfangs solche Prozesse, Maschinen, Herstellungen, Materialzusammensetzungen, Mittel, Verfahren oder Schritte umfassen.
Claims (21)
- Verfahren zum Herstellen einer Halbleitervorrichtung (
200 ), wobei das Verfahren Folgendes aufweist: Bilden mehrerer Anschlussflächen (215 ) auf einem Werkstück, wobei jede Anschlussfläche (215 ) untere Seitenwände und obere Seitenwände besitzt; Verringern einer unteren Breite jeder Anschlussfläche (215 ), so dass eine obere Breite jeder Anschlussfläche (215 ) größer ist als die untere Breite; Bilden eines Photoresists auf den mehreren Anschlussflächen (215 ); und Entfernen von Abschnitten des Photoresists, um dadurch längs der unteren Seitenwände Seitenwandabstandshalter (217 ) zu bilden. - Verfahren nach Anspruch 1, wobei das Bilden des Photoresists das Bilden eines positiven Photoresists aufweist.
- Verfahren nach Anspruch 2, wobei das Entfernen des positiven Photoresists das Belichten des positiven Photoresists und das Entwickeln des positiven Photoresists aufweist.
- Verfahren nach Anspruch 3, wobei das Belichten des positiven Photoresists das Belichten des positiven Photoresists ohne Verwendung einer Lithographiemaske aufweist.
- Verfahren nach Anspruch 3, wobei das Belichten des positiven Photoresists das Belichten des positiven Photoresists mit einer Blind-Lithographiemaske aufweist.
- Verfahren nach einem der Ansprüche 1 bis 5, wobei der Photoresist ein Polyimid oder ein PBO (Poly-Benz-Oxazol) ist.
- Verfahren nach einem der Ansprüche 1 bis 6, wobei das Bilden der mehreren Anschlussflächen (
215 ) das Bilden einer Kupferschicht oder einer Kupferlegierungsschicht und dann das Bilden eines Stapels aus Schichten metallischer Materialien umfasst, wobei der Stapel aus Schichten metallischer Materialien Nickel (Ni) und Gold (Au) enthält. - Verfahren nach Anspruch 7, wobei das Bilden der Kupferschicht das elektrochemische Plattieren des Kupfers aufweist, wobei das Bilden des Stapels aus Schichten metallischer Materialien das elektrochemische Plattieren von Nickel (Ni), dann das elektrochemische Plattieren von Palladium (Pd) und dann das Elektroplattieren von Gold (Au) aufweist.
- Verfahren zum Herstellen einer Halbleitervorrichtung (
200 ): Bilden mehrerer Chip-Anschlussflächen (215 ) auf einem Werkstück, wobei jede Chip-Anschlussfläche (215 ) einen oberen Abschnitt und einen unteren Abschnitt besitzt, wobei der obere Abschnitt von dem unteren Abschnitt seitlich vorsteht und wobei jede Chip-Anschlussfläche (215 ) obere Seitenwände längs des oberen Abschnitts und untere Seitenwände längs des unteren Abschnitts aufweist; Bilden von Photoresist-Abstandshaltern (217 ) an den unteren Seitenwänden der mehreren Chip-Anschlussflächen (215 ); Bilden mehrerer Chips (210 ) durch Schneiden des Werkstücks, wobei jeder Chip (210 ) eine Chip-Anschlussfläche (215 ) besitzt; Anordnen eines Chips (210 ) der mehreren Chips (210 ) auf einem Träger; Kontaktieren der Chip-Anschlussfläche (215 ) und einer Träger-Anschlussfläche (225 ) des Trägers; und Einkapseln des Chips (210 ) mit einem Einkapselungsmaterial (240 ). - Verfahren nach Anspruch 9, wobei das Bilden des Photoresist-Abstandshalters (
217 ) das Bilden eines positiven Photoresists auf dem Werkstück und das Entfernen von Abschnitten des positiven Photoresists von dem Werkstück und dadurch das Bilden von Abstandshaltern (217 ) aus positivem Photoresist aufweist. - Verfahren nach Anspruch 10, wobei das Entfernen des positiven Photoresists das Belichten des positiven Photoresists mit Licht, das Entwickeln des positiven Photoresists und das Härten des positiven Photoresists aufweist.
- Verfahren nach Anspruch 11, wobei das Belichten des positiven Photoresists mit Licht das Belichten des positiven Photoresists ohne Verwendung einer Lithographiemaske oder das Belichten des positiven Photoresists mit einer Blind-Lithographiemaske aufweist.
- Verfahren nach einem der Ansprüche 9 bis 12, wobei der untere Abschnitt der Chip-Anschlussflächen (
215 ) Kupfer oder eine Kupferlegierung enthält, der obere Abschnitt der Chip-Anschlussflächen (215 ) einen Stapel aus Schichten metallischer Materialien enthält und der Stapel aus Schichten metallischer Materialien eine Nickelschicht und eine Goldschicht (Au-Schicht) enthält. - Verfahren nach Anspruch 13, wobei der Stapel aus Schichten metallischer Materialien ferner eine Palladiumschicht (Pd) enthält.
- Halbleitervorrichtung (
200 ), die Folgendes aufweist: einen Träger; einen Chip (210 ), der auf dem Träger angeordnet ist; eine erste Chip-Anschlussfläche (215 ), die auf dem Chip (210 ) angeordnet ist, wobei die erste Chip-Anschlussfläche (215 ) untere Seitenwände und obere Seitenwände besitzt, wobei eine untere Breite der ersten Chip-Anschlussfläche (215 ) kleiner ist als eine obere Breite der ersten Chip-Anschlussfläche (215 ), wobei die untere Breite den unteren Seitenwänden entspricht und die obere Breite den oberen Seitenwänden entspricht; Photoresist-Seitenwandabstandshalter (217 ), die längs der unteren Seitenwände der ersten Chip-Anschlussfläche (215 ) angeordnet sind; und ein Einkapselungsmaterial (240 ), das den Chip (210 ) einkapselt. - Halbleitervorrichtung (
200 ) nach Anspruch 15, wobei die erste Chip-Anschlussfläche (215 ) eine Kupferschicht oder eine Kupferlegierungsschicht, die die unteren Seitenwände besitzt, aufweist. - Halbleitervorrichtung (
200 ) nach Anspruch 16, wobei die erste Chip-Anschlussfläche (215 ) einen Stapel aus Schichten metallischer Materialien zwischen den oberen Seitenwänden umfasst, wobei der Stapel aus Schichten metallischer Materialien eine Nickelschicht (Ni-Schicht) und eine Goldschicht (Au-Schicht) enthält. - Halbleitervorrichtung (
200 ) nach Anspruch 17, wobei die Photoresist-Seitenwandabstandshalter (217 ) Seitenwandabstandshalter (217 ) aus einem positiven Photoresist sind. - Halbleitervorrichtung (
200 ) nach einem der Ansprüche 15 bis 18, wobei der Träger eine erste Träger-Anschlussfläche (225 ) aufweist und wobei die erste Chip-Anschlussfläche (215 ) mit der ersten Träger-Anschlussfläche (225 ) elektrisch verbunden ist. - Halbleitervorrichtung (
200 ) nach Anspruch 19, wobei der Chip (210 ) eine zweite Chip-Anschlussfläche (215 ) aufweist und wobei der Träger eine zweite Träger-Anschlussfläche (225 ) aufweist, wobei die zweite Chip-Anschlussfläche (215 ) mit der zweiten Träger-Anschlussfläche (225 ) elektrisch verbunden ist und wobei die ersten und die zweiten Chip-Anschlussflächen (215 ) mit den ersten bzw. der zweiten Träger-Anschlussfläche (225 ) über Drähte elektrisch verbunden sind. - Halbleitervorrichtung (
200 ) nach Anspruch 19, wobei der Chip (210 ) eine zweite Chip-Anschlussfläche (215 ) aufweist und der Träger eine zweite Träger-Anschlussfläche (225 ) aufweist, wobei die zweite Chip-Anschlussfläche (215 ) mit der zweiten Träger-Anschlussfläche (225 ) elektrisch verbunden ist und wobei die erste und die zweite Chip-Anschlussfläche (215 ) mit der ersten bzw. der zweiten Träger-Anschlussfläche (225 ) über Lötmittel elektrisch verbunden sind.
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CN105428222A (zh) * | 2015-12-25 | 2016-03-23 | 成都嘉石科技有限公司 | SiC基GaN器件的衬底通孔制作方法 |
CN108010837B (zh) * | 2017-12-12 | 2021-05-04 | 成都海威华芯科技有限公司 | 一种划片道制作工艺 |
JP7214966B2 (ja) * | 2018-03-16 | 2023-01-31 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
EP3890008A1 (de) * | 2020-03-31 | 2021-10-06 | Mitsubishi Electric R&D Centre Europe B.V. | Halbleitermodulanordnung mit einer verbindungsschicht mit einem elastischen gitter zwischen einem halbleiterchip und einem substrat und herstellungsverfahren für eine solche anordnung |
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US20140319689A1 (en) | 2014-10-30 |
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DE102013108813B4 (de) | 2020-10-15 |
CN103594388B (zh) | 2016-10-26 |
US10049994B2 (en) | 2018-08-14 |
US8822327B2 (en) | 2014-09-02 |
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