CN110622299A - 具有预润湿触点侧壁表面的集成电路封装 - Google Patents
具有预润湿触点侧壁表面的集成电路封装 Download PDFInfo
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Abstract
本发明揭示一种集成电路IC封装(100),其包含囊封封装(106),所述囊封封装(106)含有附接到引线框架(104)的集成电路裸片(341)。一组触点(102、103)形成在所述封装(100)上,每一触点具有暴露的触点侧壁表面和暴露的触点下部表面(813、823)。焊料可湿性材料的保护层(814、824)覆盖每一触点侧壁表面。
Description
技术领域
本发明大体来说涉及集成电路封装,且更特定来说涉及一种具有预润湿触点侧壁表面的封装。
背景技术
扁平无引线封装,例如四方扁平无引线(QFN)和双扁平无引线(DFN),将集成电路物理地和电气地连接到印刷电路板上。扁平无引线,也称为微引线框架(MLF)和SON(小轮廓无引线),是一种表面贴装技术,是无需通孔将集成电路(IC)连接到PCB(印刷电路板)的表面的几种封装技术中的一者。扁平无引线为由平面铜引线框架衬底制成的近芯片级塑料囊封封装。封装底部上的周界平台提供与PCB的电气连接。扁平无引线封装包含暴露的散热垫,以改进热从IC转移出且到PCB中。
为确保汽车满足对安全性和高可靠性的现代需求,汽车行业要求原始设备制造商(OEM)对电路板组件执行100%自动外观检查(AVI)。但是四方扁平无引线(QFN)封装没有用于AVI的易于查看的可焊引脚/端子,以确定封装是否已成功焊接到印刷电路板(PCB)上。封装边缘具有裸露的用于端子的铜。这些容易被氧化,这使得侧壁焊料难以润湿。
发明内容
一种集成电路(IC)封装包含囊封封装,所述囊封封装含有附接到引线框架的集成电路裸片。一组触点由引线框架形成,每一触点具有暴露的触点侧壁表面和暴露的触点下部表面。焊料可湿性材料的保护层覆盖每一触点侧壁表面。
在执行自动外观检查(AVI)的方法中,将集成电路(IC)封装焊接到衬底上的衬垫。IC封装具有触点,且触点中的每一者具有下部表面和侧壁表面。可以外观检查IC封装上的触点中的每一者的焊料轮廓。对于IC封装上的触点中的每一者,当焊料轮廓形成实质上覆盖触点侧壁的圆角时,接头可能合格;否则,当焊料轮廓未形成实质上覆盖触点侧壁的圆角时,接头可能会失败。
附图说明
图1为其中触点侧壁已被预镀锡的QFN IC封装的说明。
图2为具有附接的QFN封装的PCB的侧视截面图,说明焊接QFN封装的问题。
图3为可用于形成图1的QFN的引线框架带的俯视图。
图4为图3的引线框架带的部分的更详细的视图。
图5A到5G说明可用于预镀锡图1的QFN的触点侧壁表面的一系列步骤。
图6和7说明在图1的QFN的制作期间喷墨打印机的使用。
图8为焊接到PCB的图1的QFN的侧视图。
图9为说明QFN IC的封装的流程图。
具体实施方式
为了一致性,图式中相同的元件由相同的参考编号表示。
传统的QFN封装可能很难执行100%AVI,因为触点侧壁的焊料覆盖率可能在50%到90%之间变化。OEM可能会由于错误的组装失败而导致良率问题,以及在组装工艺具有显著不良焊接接头的情况下的真正失败,从而带来额外的成本。AVI可以用X射线成像补充,然而,使用X射线机检查良好、可靠的焊接接头会增加更多费用。此外,在一些AVI系统中可能无法使用X射线机。
实施例可包含具有触点侧壁的QFN封装,所述触点侧壁在封装制作期间被预镀锡以允许可被AVI验证的可靠的侧壁焊料覆盖率。
图1为触点侧壁已被预镀锡的QFN IC封装100的说明。图中说明了QFN封装100的底部侧。扁平无引线封装,例如四方扁平无引线(QFN)和双扁平无引线(DFN),将集成电路物理地和电气地连接到印刷电路板上。扁平无引线,也称为微引线框架(MLF)和SON(小轮廓无引线),是一种表面贴装技术,是无需通孔而将IC连接到PCB的表面的几种封装技术之一。扁平无引线为由平面铜引线框架衬底制成的近芯片级塑料囊封封装。封装底部上的周界平台提供与PCB的电气连接。扁平无引线封装包含暴露的散热垫,以改进IC(至PCB)散热。散热垫中的金属通孔可以进一步促进热转移。QFN封装类似于四方扁平封装和球栅阵列。
QFN封装100包含在底部侧上围绕封装的周界排列的一组触点,例如触点102和103。触点中的每一者在QFN封装100的底部侧上具有暴露的表面和暴露的侧壁。散热垫104在QFN 100的底部侧上具有暴露的表面。集成电路裸片(未展示)被安装到散热垫104的另一侧。整个组合件被囊封在模塑料106中,例如各种类型的环氧化合物。QFN在图1中说明,但其它实施例可以使用其它类型的集成电路封装,其可以包含一或多个触点,所述触点可以具有侧壁触点表面。
图2为具有附接的QFN封装211、212的PCB 210的侧视截面图,说明焊接QFN封装的问题。此截面图说明包含触点212的QFN 210的部分和包含触点222的QFN 221的部分。如上文所述,QFN封装中的每一触点具有暴露的触点下部表面213、223和暴露的触点侧壁表面214、224。
在组装PCB 210期间,可以使用焊料将QFN安装到PCB 210,如在215、225处所指示。在组装PCB 210之后,可以使用例如在230处所指示的摄像机来执行AVI工艺。摄像机230可以安装在机械臂上,所述机械臂允许摄像机230在PCB 210的表面上方移动且外观检查每一焊接接头。替代地,可以固定摄像机230,且可以将PCB 210安装在允许移动PCB 210的机械手台上,以便摄像机230可以外观检查PCB210上的每个焊接接头。
当焊接接头,如焊接接头215,形成从铜衬垫216向上延伸触点侧壁表面214且实质上覆盖整个触点侧壁表面的光滑焊接圆角时,可以认为良好的焊接接头已形成在触点212和PCB衬垫216之间。如本文中所使用,术语“实质上覆盖”是指焊接圆角覆盖大部分触点侧壁表面,例如90%到95%。因此,当摄像机230在焊接接头215的视角内时,如在221处所指示,AVI系统可以基于焊接圆角的大小和配置来推断已形成良好的焊接接头。
在触点侧壁表面224上的污染,例如在铜表面上形成的氧化物,可能会抑制焊料润湿性。在此状况下,在焊接操作之后,触点侧壁表面224可以保持暴露。在大多数状况下,只要触头222的底部表面223未被污染,在触头222和PCB衬垫226之间仍将形成良好的接头。然而,在一些状况下,例如当底部表面223上有污染时,或在PCB衬垫226上有污染时,或当施加的焊料不足时,等等,可能无法形成良好的焊接接头。因此,当例如焊接接头225的焊接接头不会芯吸触点侧壁表面224,通过如232处指示的外观检查很难看出在接触点222和PCB衬垫226之间已形成良好的焊接接头。因此,当焊料轮廓不包含覆盖触点侧壁的大部分的圆角时,接头可能会失败。
图3为可用于形成图1的QFN 100的引线框架带340的俯视图。引线框架带340可包含单独引线框架的一或多个阵列。引线框架带340通常由铜片制作,所述铜片被蚀刻或冲压以形成散热垫和触点的图案。引线框架带340可以电镀有锡或另一金属,其将防止铜的氧化并提供易于焊接的下部触点表面。IC裸片可以附接到每一单独的引线框架,例如在341、342处所指示。
图4为引线框架带340的部分的更详细视图。每一单独引线框架包含散热垫,例如散热垫404、405。每一单独引线框架还包含围绕散热垫的一组触点,例如触点402、403。牺牲性的金属带将所有触点连接在一起,且提供机械支撑,直到锯切工艺将其去除为止。IC芯片附接到每一散热垫,例如IC芯片341、342。然后可以执行线接合以将每一IC上的接合衬垫连接到引线框架上的相应触点。然后,整个引线框架带340可以覆盖有一层模塑料以囊封IC。然后可以通过沿着切割线448、449切割将引线框架带340分割为单独封装的IC。
在沿着线448、449切割之前,将邻近引线框架中的触点连接在一起。例如,在沿着切割线449切割之前,触点402和403为单个单元。锯切引线框架带340产生每一QFN封装的触点侧壁;然而,所得触点侧壁为裸露的铜表面。这些裸露的铜触点侧壁经受氧化,这可以阻碍焊料润湿,如关于图2所描述。现在将更详细地描述可用于预镀锡触点侧壁表面的工艺。
图5A到5G说明可用于例如对图1的QFN 100的触点侧壁表面进行预镀锡的一系列步骤。图5A到5G为引线框架带340的部分的截面图,如图4中所展示。图5A说明封装工艺之后的引线框架带340。使用已知的或以后开发的裸片附接工艺将IC裸片341、342附接到相应的散热垫404、405。触点元件401将在图5B中所说明的后续步骤中被切割以形成单独触点402、403。接合线551将IC裸片404上的接合衬垫连接到稍后将变为触点402的触点元件401的部分。类似地,接合线552将IC裸片405上的接合衬垫连接到稍后将变为触点403的触点元件401的部分。已经使用已知的或以后开发的工艺将模塑料506施加到引线框架带340。
图5B说明使用锯562形成部分锯切沟槽563的锯切工艺,所述部分锯切沟槽将触点元件401分成单独触点402、403。锯切工艺在整个引线框架340上沿着每一切割线448、449(如图4中所展示)形成类似的部分锯切沟槽。如上文中所描述,将每一触点元件(例如触点元件401)锯切成单独触点(例如,触点402、403)形成裸露的铜触点侧壁表面。牺牲金属也可以通过部分锯切移除。
部分锯切沟槽563足够深以完全分离触点402、403,并移除每一触点之间的牺牲金属带,但是足够浅以使得经囊封引线框架带340保持为一体。
图5C说出将预镀锡材料565从施配器564沉积到部分锯切沟槽563中的工艺。术语“预镀锡材料”是指可用于在裸露的触点侧壁表面上形成保护层以防止在裸露的触点侧壁表面上形成氧化或其它污染的任何类型的材料。当封装焊接到PCB上时,预镀锡材料的保护层为焊料提供可润湿表面。
预镀锡材料565可为可包含助熔剂的焊膏。在此状况下,施配器564可为MY600焊料喷射打印机,例如,其也可以用于将焊膏点施配到PCB上。
在另一实施例中,预镀锡材料565可为包含银(Ag)纳米颗粒的油墨。银纳米颗粒通常为大小在1nm到100nm之间的银纳米颗粒。虽然经常被描述为“银”,但一些颗粒由大百分比的氧化银组成,因为氧化银具有较大的表面对块体银原子比率。常用的形状为球形的银纳米颗粒;然而,可以使用菱形、八边形或其它形状。
在此状况下,施配器564可为单喷嘴或多喷嘴喷墨施配器。在一些实施例中,喷墨施配器564可具有例如500到1000个喷墨喷嘴。还原气体(例如甲酸)可用于在纳米Ag油墨沉积之前和/或期间清洁裸铜触点侧壁表面。
图5D和5E说明烘烤工艺,在所述工艺中,对沉积的预镀锡材料565进行加热,使得其回流并芯吸触点402、403的触点侧壁表面,以润湿触点侧壁,从而形成预镀锡层566、567,所述预镀锡层用焊料可润湿材料的保护层覆盖每一触点402、403的整个触点侧壁表面。
选择烘烤温度,使其足够高以使预镀锡材料回流,但又不至于损坏囊封材料506。如果预镀锡材料565为焊膏,可以使用大约200℃到280℃范围内的温度。如果预镀锡材料565为纳米Ag,可以使用例如大约150℃到250℃范围内的温度。
仅说明两个触点402、403,但是引线框架带340上的所有触点都以类似的方式处理。
图5F说明填充工艺,其中可以用填充材料568填充部分锯切沟槽563。例如,填充材料568可为类似于模塑料506的环氧化合物。例如,可以使用已知的或以后开发的印刷工艺来施加填充材料568。填充部分锯切沟槽563可以产生例如具有光滑侧的最终QFN封装。
图5G说明锯切工艺,其中通过使用锯571完全锯开切线448、449(如在图4中所展示)来将经囊封引线框架带340分割成单独的QFN封装。
返回参考图5B,部分锯切沟槽563具有宽度574,所述宽度足够宽以移除在囊封之前提供机械支撑的触点中的每一者之间的牺牲金属带。选择锯571以产生具有比部分锯切沟槽563的宽度574窄的宽度573的切口,使得预镀锡层566、567的至少一部分保留在触点402、403的触点侧壁表面上以在每一封装被分割之后形成保护层。
图6为引线框架340的底部表面的部分的放大图。在此实例中,触点的宽度为大约240μm,而触点与触点之间的间距为大约260μm。部分锯切沟槽563的宽度574为大约200μm。
图7说明在图1的QFN的制作期间多头喷墨打印机的使用。如上文中所描述,预镀锡材料565可为包含银(Ag)纳米颗粒的油墨。在此状况下,施配器564可为单喷嘴或多喷嘴喷墨施配器。在一些实施例中,喷墨施配器564可具有例如500到1000个喷墨喷嘴。还原气体(例如甲酸)可用于在纳米Ag油墨沉积之前和/或期间清洁裸铜触点侧壁表面。
图8说明焊接到PCB 810的图1的QFN 100的截面侧视图。QFN包含引线框架,所述引线框架具有散热垫104和围绕散热垫104的一组触点,如由触点102、103所表示。触点中的每一者在QFN封装100的底部侧上具有暴露的表面和暴露的侧壁。例如,触点102具有在QFN封装100的底部侧上的暴露的下部表面813和暴露的触点侧壁814。类似地,触点103具有在QFN封装100的底部侧上的暴露的下部表面823和暴露的触点侧壁824。每一触点侧壁表面已通过关于图5A到5G更详细描述的工艺进行预镀锡。使用已知或以后开发的裸片附接材料854将IC裸片341附接到散热垫104。
触点102通过焊料815连接到PCB 810上的衬垫816。类似地,触点103通过焊料826连接到PCB 810上的衬垫826。散热垫104可以通过焊料830连接到衬垫831。PCB810使用从层压在非导电衬底上的铜片蚀刻的导电迹线、衬垫和其它特征机械地支撑和电气连接电子组件。组件(例如电容器、电阻器或有源装置)通常焊接在PCB上。高级PCB可能含有嵌入衬底中的组件。
PCB 810可为单面(一个铜层)、双面(两个铜层)或多层(外层和内层)。不同层上的导体可与通孔连接。玻璃环氧树脂为主要绝缘衬底;然而,各种实施例可以使用各种类型的已知或以后开发的PCB。
如上文中所描述,通过对QFN 100的触点侧壁表面(例如触点侧壁表面814、824)进行预镀锡,每一接触焊接接头将芯吸触点侧壁表面并形成圆角,如由焊接接头815、825所说明。然后,AVI可能能够可靠地确定是否已形成合适的焊接接头。
图9为说明制作QFN IC的流程图。可以制作半导体晶片以形成一组集成电路,然后可以使用已知或以后开发的处理技术将其分割为单独裸片,如框900中所指示。
然后,可以使用一组已知或以后开发的裸片附接处理将一组裸片附接到单个引线框架带上,并线接合到引线框架带上的触点,如在框902中所指示。
然后,如在框904处所指示,可以使用已知的或以后开发的封装材料,使用模塑料囊封整个引线框架带。
然后,如在框906中所指示,可以部分地锯切经囊封引线框架带,以在每一单独的引线框架之间形成部分锯切沟槽,如关于图4和5B更详细地描述。每一部分锯切沟槽足够深以完全分离邻近单独引线框架之间的触点,并移除每一触点之间的牺牲金属带,但是足够浅以使得经囊封引线框架带保持为一体。
如框908处所指示,可将预镀锡材料从施配器施配到部分锯切沟槽中。预镀锡材料可为可包含助熔剂的焊膏,包含银(Ag)纳米颗粒的油墨等。在纳米Ag油墨沉积之前和/或期间,可以使用还原气体(例如甲酸)来清洁裸铜触点侧壁表面。
如在框910处所指示,可以执行烘烤工艺,其中对沉积的预镀锡材料进行加热,以使其回流并芯吸触点的触点侧壁表面以润湿触点侧壁,且从而形成覆盖每一触点的整个触点侧壁表面的预镀锡层。
如在框912中所指示,可执行回填工艺,其中可以用填充材料填充部分锯切沟槽。例如,填充材料可为类似于在步骤904中使用的模塑料的环氧化合物。例如,可使用已知的或以后开发的印刷工艺来施加填充材料。填充部分锯切沟槽可以产生例如具有光滑侧的最终QFN封装。
如在框914中所指示,可以执行锯切工艺,其中通过使用已知的或以后开发的锯切工艺在每一单独的引线框架之间完全锯切,将经囊封引线框架带分割成单独的QFN封装。在步骤906中形成的部分锯切沟槽具有宽度,所述宽度足够宽以移除在囊封之前提供机械支撑的触点中的每一者之间的牺牲金属带。选择最终锯切工艺以产生宽度比部分锯切沟槽的宽度窄的切口,使得使预镀锡层的至少一部分保留在触点的触点侧壁表面上。
触点侧壁氧化问题的先前解决方案执行部分切割,所述部分切割并未完全分离邻近触点,后续接着进行电镀操作。触点不能完全分离,因为执行电镀需要每一触点的导电性。因此,在分割之后,触点侧壁表面的部分为受到氧化的裸铜。实施例克服了由触点侧壁表面的仅一部分的氧化引起的问题。
其它实施例
本文中将纳米Ag油墨描述为一种预镀锡材料,但也可以使用其它类型的导电油墨,例如锡纳米颗粒、金纳米颗粒等。
本文中描述了基于QFN封装的实例实施例,但其它实施例可以使用其它无引线配置,例如双扁平无引线封装(DFN)、单扁平无引线封装、顶部暴露衬垫无引线封装、薄和超薄无引线封装等。
本文中描述了锯切以将完成的引线框架带分割,但另一实施例可以使用其它技术来分割,例如激光切割、水射流切割等。
本文中描述了铜引线框架带,但其它实施例可以使用由易受氧化的其它导电金属或非金属材料构成的引线框架。
本文中描述了引线框架的表面的镀锡以保护暴露的触点下部表面,但另一实施例可以使用防止引线框架表面的氧化且为焊料可润湿的另一材料来处理引线框架带的表面。
本文中描述了可以具有多个互连层的环氧玻璃印刷电路板,但另一实施例可使用不同的衬底,例如多层陶瓷等。
在本说明书中,术语“耦合”及其派生词意指间接、直接、光学及/或无线电连接。因此,如果第一装置耦合到第二装置,那么所述连接可通过直接电连接,通过经由其它装置及连接的间接电连接,通过光电连接,及/或通过无线电连接。
虽然本文中可以顺序方式呈现并描述方法步骤,但可省略、重复、同时执行及/或以不同于图式中所展示及/或本文中所描述的次序的次序执行所呈现及所描述的步骤中的一或多者。因此,实施例不限于图式中所展示及/或本文中所描述的步骤的特定顺序。
在权利要求书的范围内,修改在所描述的实施例中是可能的,且其它实施例是可能的。
Claims (15)
1.一种集成电路IC封装,其包括:
囊封封装,其含有附接到引线框架的集成电路裸片;
一组触点,每一触点具有暴露的触点侧壁表面和暴露的触点下部表面;及
材料保护层,其覆盖每一触点侧壁表面。
2.根据权利要求1所述的IC封装,其中所述材料保护层包含银纳米颗粒。
3.根据权利要求1所述的IC封装,其中所述材料保护层为焊料。
4.根据权利要求1所述的IC封装,其中所述引线框架为铜。
5.根据权利要求1所述的IC封装,其中每一暴露的触点下部表面覆盖有镀锡。
6.一种方法,其包括:
囊封具有单独引线框架的引线框架带,其中所述引线框架带包含附接到所述单独引线框架的IC裸片,其中至少两个邻近的单独引线框架共享触点元件;
在邻近于所述触点元件的所述经囊封引线框架带中部分地锯切沟槽,以形成触点侧壁表面;
将预镀锡材料沉积到所述沟槽中;
使所述预镀锡材料回流以用所述预镀锡材料覆盖所述触点侧壁表面;及
将所述经囊封引线框架带分成单独IC封装,每一IC封装具有触点侧壁表面,其中所述预镀锡材料在所述触点侧壁表面上形成保护层。
7.根据权利要求6所述的方法,其中所述预镀锡材料层包含银纳米颗粒。
8.根据权利要求6所述的方法,其中所述预镀锡材料层为焊料。
9.根据权利要求6所述的方法,其中所述预镀锡材料为使用喷墨打印机沉积。
10.根据权利要求6所述的方法,其中将所述经囊封框架带分成单独IC封装产生比所述沟槽更薄的切口。
11.根据权利要求6所述的方法,其进一步包括在将所述经囊封引线框架带分成单独IC封装之前回填所述沟槽。
12.一种用于执行自动外观检查AVI的方法,所述方法包括:
将集成电路IC封装焊接到衬底上的衬垫,其中所述IC封装具有触点,且其中所述触点中的每一者具有下部表面和侧壁表面;
外观检查所述IC封装上的触点和所述衬底上的衬垫之间的焊接接头的焊料轮廓;及
当所述焊料轮廓不包含覆盖所述触点侧壁表面的大部分的圆角时,所述接合失败。
13.根据权利要求12所述的方法,其进一步包含:当所述焊料轮廓包括覆盖所述触点侧壁表面的大部分的圆角时,所述接头合格。
14.根据权利要求12所述的方法,其中所述触点中的每一者的所述侧壁表面的大部分被材料保护层覆盖。
15.根据权利要求14所述的方法,其中所述材料保护层包含银纳米颗粒。
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PCT/US2018/038364 WO2018236930A1 (en) | 2017-06-19 | 2018-06-19 | INTEGRATED CIRCUIT BOX HAVING PREHUMIDIFIED CONTACT LATERAL SURFACE SURFACES |
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US11127660B2 (en) | 2018-12-31 | 2021-09-21 | Microchip Technology Incorporated | Surface-mount integrated circuit package with coated surfaces for improved solder connection |
CN110449683B (zh) * | 2019-07-31 | 2021-02-09 | 嘉兴军胜电子科技有限公司 | 一种高可靠应用印制电路板组件qfn装焊预处理方法 |
US20220059439A1 (en) * | 2020-08-21 | 2022-02-24 | Texas Instruments Incorporated | Solder printing |
US20230098907A1 (en) * | 2021-09-30 | 2023-03-30 | Texas Instruments Incorporated | Package geometries to enable visual inspection of solder fillets |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030102526A1 (en) * | 2001-11-30 | 2003-06-05 | Rajen Dias | Backside metallization on sides of microelectronic dice for effective thermal contact with heat dissipation devices |
US20060255102A1 (en) * | 2005-05-11 | 2006-11-16 | Snyder Rick B | Technique for defining a wettable solder joint area for an electronic assembly substrate |
US20140306330A1 (en) * | 2013-03-09 | 2014-10-16 | Adventive Ipbank | Low Profile Leaded Semiconductor Package |
US9177836B1 (en) * | 2014-06-06 | 2015-11-03 | Freescale Semiconductor, Inc. | Packaged integrated circuit device having bent leads |
WO2016081806A1 (en) * | 2014-11-20 | 2016-05-26 | Microchip Technology Incorporated | Qfn package with improved contact pins |
US9373569B1 (en) * | 2015-09-01 | 2016-06-21 | Texas Instruments Incorporation | Flat no-lead packages with electroplated edges |
US20170133302A1 (en) * | 2009-01-29 | 2017-05-11 | Semiconductor Components Industries, Llc | Leadless semiconductor packages, leadframes therefor, and methods of making |
US20170162530A1 (en) * | 2015-12-03 | 2017-06-08 | Texas Instruments Incorporated | Packaged IC with Solderable Sidewalls |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6415397B1 (en) | 1998-04-08 | 2002-07-02 | Kingston Technology Company | Automated multi-PC-motherboard memory-module test system with robotic handler and in-transit visual inspection |
US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
US20050146160A1 (en) | 2003-12-18 | 2005-07-07 | Beauchamp Michael L. | Home utility management vehicle mini van or HUM V Mini Van |
GB0412949D0 (en) * | 2004-06-10 | 2004-07-14 | Inverness Medical Switzerland | Improvements in or relating to lateral flow assay devices |
JP5259978B2 (ja) * | 2006-10-04 | 2013-08-07 | ローム株式会社 | 半導体装置の製造方法 |
US8183095B2 (en) | 2010-03-12 | 2012-05-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation |
US10163766B2 (en) * | 2016-11-21 | 2018-12-25 | Semiconductor Components Industries, Llc | Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks |
US8841758B2 (en) | 2012-06-29 | 2014-09-23 | Freescale Semiconductor, Inc. | Semiconductor device package and method of manufacture |
US8884414B2 (en) | 2013-01-09 | 2014-11-11 | Texas Instruments Incorporated | Integrated circuit module with dual leadframe |
JP6244147B2 (ja) * | 2013-09-18 | 2017-12-06 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置の製造方法 |
US20160172275A1 (en) * | 2014-12-10 | 2016-06-16 | Stmicroelectronics S.R.L. | Package for a surface-mount semiconductor device and manufacturing method thereof |
US11348806B2 (en) * | 2014-12-23 | 2022-05-31 | Texas Instruments Incorporated | Making a flat no-lead package with exposed electroplated side lead surfaces |
US9966326B2 (en) | 2015-03-16 | 2018-05-08 | Unisem (M) Berhad | Lead frames with wettable flanks |
-
2017
- 2017-06-19 US US15/627,141 patent/US10636729B2/en active Active
-
2018
- 2018-06-19 WO PCT/US2018/038364 patent/WO2018236930A1/en active Application Filing
- 2018-06-19 CN CN201880029964.5A patent/CN110622299A/zh active Pending
- 2018-06-19 JP JP2019570362A patent/JP2020524410A/ja active Pending
-
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- 2020-03-20 US US16/825,676 patent/US11217513B2/en active Active
-
2024
- 2024-02-20 JP JP2024023842A patent/JP2024056969A/ja active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030102526A1 (en) * | 2001-11-30 | 2003-06-05 | Rajen Dias | Backside metallization on sides of microelectronic dice for effective thermal contact with heat dissipation devices |
US20060255102A1 (en) * | 2005-05-11 | 2006-11-16 | Snyder Rick B | Technique for defining a wettable solder joint area for an electronic assembly substrate |
US20170133302A1 (en) * | 2009-01-29 | 2017-05-11 | Semiconductor Components Industries, Llc | Leadless semiconductor packages, leadframes therefor, and methods of making |
US20140306330A1 (en) * | 2013-03-09 | 2014-10-16 | Adventive Ipbank | Low Profile Leaded Semiconductor Package |
US9177836B1 (en) * | 2014-06-06 | 2015-11-03 | Freescale Semiconductor, Inc. | Packaged integrated circuit device having bent leads |
WO2016081806A1 (en) * | 2014-11-20 | 2016-05-26 | Microchip Technology Incorporated | Qfn package with improved contact pins |
US9373569B1 (en) * | 2015-09-01 | 2016-06-21 | Texas Instruments Incorporation | Flat no-lead packages with electroplated edges |
US20170162530A1 (en) * | 2015-12-03 | 2017-06-08 | Texas Instruments Incorporated | Packaged IC with Solderable Sidewalls |
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