CN105097563A - 用于半导体芯片封装的侧可润湿电镀 - Google Patents

用于半导体芯片封装的侧可润湿电镀 Download PDF

Info

Publication number
CN105097563A
CN105097563A CN201510504459.XA CN201510504459A CN105097563A CN 105097563 A CN105097563 A CN 105097563A CN 201510504459 A CN201510504459 A CN 201510504459A CN 105097563 A CN105097563 A CN 105097563A
Authority
CN
China
Prior art keywords
pad
encapsulation
lead
solder
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510504459.XA
Other languages
English (en)
Other versions
CN105097563B (zh
Inventor
肯尼思·J·许宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxim Integrated Products Inc
Original Assignee
Maxim Integrated Products Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Maxim Integrated Products Inc filed Critical Maxim Integrated Products Inc
Publication of CN105097563A publication Critical patent/CN105097563A/zh
Application granted granted Critical
Publication of CN105097563B publication Critical patent/CN105097563B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/20—Adhesives in the form of films or foils characterised by their carriers
    • C09J7/22—Plastics; Metallised plastics
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/20—Adhesives in the form of films or foils characterised by their carriers
    • C09J7/28—Metal sheet
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J9/00—Adhesives characterised by their physical nature or the effects produced, e.g. glue sticks
    • C09J9/02—Electrically-conducting adhesives
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/005—Contacting devices
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/02—Tanks; Installations therefor
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/06—Suspending or supporting devices for articles to be coated
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10—Electrodes, e.g. composition, counter electrode
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611—Smooth layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/30—Electroplating: Baths therefor from solutions of tin
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/34—Electroplating: Baths therefor from solutions of lead
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/48—Electroplating: Baths therefor from solutions of gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer
    • Y10T428/2804—Next to metal

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本申请案涉及用于半导体芯片封装的侧可湿润电镀。一种用于通过侧可润湿电镀提供半导体芯片封装的方法包括：从以块格式形成的封装阵列单分半导体芯片封装；将所述半导体芯片封装没入于电镀液浴中；使所述半导体芯片封装的引线焊盘与所述电镀液浴内的导电接触材料接触；将所述导电接触材料连接到阴极电位；将所述电镀液浴内的阳极连接到阳极电位；及对所述半导体芯片封装的所述引线焊盘进行电镀。

Description

用于半导体芯片封装的侧可润湿电镀
本申请是申请日为2011年8月9日、申请号为201110229915.6、发明名称为“用于半导体芯片封装的侧可润湿电镀”的申请的分案申请。
相关申请案交叉参考
本申请案根据35U.S.C.§119(e)请求对在2010年8月9日提出申请且标题为“侧可润湿电镀方法(SideWettablePlatingMethod)”的第61/371,955号美国临时申请案的权益，所述临时申请案以全文引用的方式并入本文中。
技术领域
本发明涉及半导体，尤其涉及一种半导体芯片封装。
背景技术
半导体组合件的一直存在的目标是提供用于包纳/装纳半导体组件的封装，所述半导体组件较小、较薄、较凉爽且以高生产速率制造起来较廉价。一种类型的半导体封装是塑料双列直插式封装(PDIP)。另一种类型的半导体封装是鸥翼式小轮廓(SO)封装。这些半导体封装通常包括从封装的侧延伸的引线(连接器)。其它类型的半导体封装是扁平无引线封装，例如双平面无引线(DFN)及四方扁平无引线(QFN)封装。DFN封装仅在封装底部的周界的两个侧上具有引线焊盘，而QFN封装在封装底部的四个侧上具有引线焊盘。一些DFN及QFN封装大小的范围可从具有三(3)个引线焊盘的1毫米×2毫米(1x2mm)封装到具有六十八(68)个引线焊盘的10毫米×10毫米(10x10mm)封装。
由于引线框架在封装的底部上，因此与具有类似主体大小及引线计数的有引线封装相比，扁平无引线封装可提供优越的热性能。此外，在扁平无引线配置中，裸片附接垫可暴露于封装的底部外部上，从而允许将其直接焊接到印刷电路板，且提供用于热从封装消散掉的直接路径。所暴露的裸片附接垫，通常称作暴露的热垫，可极大地改善热转移离开集成电路封装及热转移到印刷电路板中。然而，当一起制造多个扁平无引线封装且接着将其彼此分离(单分)时，可难以获得到位于IC封装的侧面上的引线焊盘的良好焊接连接，因为在单分之前这些侧部分未经涂覆焊料可润湿材料。此外，可难以使用目视检查技术来检查到引线焊盘的焊接连接。
发明内容
揭示用于通过侧可润湿电镀提供半导体芯片封装的技术。在一个或一个以上实施方案中，所述技术可包括：从以块格式形成的封装阵列单分半导体芯片封装；将所述半导体芯片封装没入于电镀液浴中；使所述半导体芯片封装的引线焊盘与所述电镀液浴内的导电接触材料接触；将所述导电接触材料连接到阴极电位；将所述电镀液浴内的阳极连接到阳极电位；及对所述半导体芯片封装的所述引线焊盘进行电解电镀。
提供本发明内容以按简要形式介绍在下文实施方式进一步描述的概念选择。本发明内容并不打算识别所请求标的物的关键特征或实质特征，也不打算用于协助确定所请求标的物的范围。
附图说明
参照附图来描述实施方式。在所述说明中的不同例项中使用相同参考编号可指示类似或相同条目。
图1是图解说明块格式面板的仰视平面图，多个QFNIC封装已在所述块格式面板上以阵列形成，其中在单分成个别装置之前所述面板上的暴露的热垫及底部焊盘部分已浸渍有焊料或以其它方式电镀有焊料可润湿材料。
图2是图解说明两个QFNIC封装的透视图，其已在暴露的热垫及底部焊盘部分已浸渍有焊料或以其它方式电镀有焊料可润湿材料之后于块格式制造工艺期间单分。
图3A是图解说明形成为阵列的部分的经单分扁平无引线IC封装的未经电镀侧焊盘部分的局部侧立面图。
图3B是图解说明形成为阵列的部分的经单分扁平无引线IC封装的经电镀底部焊盘部分的局部仰视平面图。
图4A是图解说明根据本发明的实例性实施方案的侧可润湿无引线集成电路装置的局部截面侧立面图。
图4B是图解说明根据本发明的实例性实施方案的另一侧可润湿无引线集成电路装置的局部截面侧立面图。
图5是图解说明根据本发明的实例性实施方案用于对IC封装的周界引线焊盘进行电镀的电镀浴槽的图解性视图。
图6是图解说明根据本发明的实例性实施方案的电镀浴槽及具有附加到导电带的周界引线焊盘的若干个IC封装的局部截面侧立面图。
图7是图解说明根据本发明的实例性实施方案用于对IC封装的周界引线焊盘进行电镀的电镀浴槽的图解性视图。
图8是图解说明根据本发明的实例性实施方案用于对IC封装的周界引线焊盘进行电镀的另一电镀浴槽的图解性视图。
图9是图解说明根据本发明的实例性实施方案的电镀浴槽及具有周界引线焊盘的IC封装的图解性视图。
图10是图解说明根据本发明的实例性实施方案的电镀浴槽及具有周界引线焊盘的IC封装的局部截面侧立面图。
图11是图解说明根据本发明的实例性实施方案的另一电镀浴槽及具有周界引线焊盘的IC封装的局部截面侧立面图。
图12是图解说明根据本发明的实例性实施方案用于同时对具有周界引线焊盘的若干个IC封装进行电镀的电镀浴槽的局部截面侧立面图。
图13是图解说明根据本发明的实例性实施方案用于对无引线IC封装的周界引线焊盘进行电镀的方法的框图。
具体实施方式
概述
使用例如DFN(双平面无引线)封装及QFN(四方扁平无引线)封装等扁平无引线集成电路(IC)封装来将IC物理及电连接到印刷电路板。使用术语“扁平无引线”来描述表面安装技术，从而允许在没有通孔等的情况下将IC连接到印刷电路板(PCB)的表面。通常在扁平无引线IC封装的底部上提供无引线连接/端子(引线焊盘)及暴露的热垫以用于将封装连接到PCB。引线焊盘通常位于封装底部的周界处，而暴露的热垫位于封装底部的中心引线焊盘之间。可在面板上以块格式一起形成、模制及电镀个别扁平无引线封装，且在制作之后接着将其单分成单独的装置(例如，通过从所述面板锯割或冲压所述封装)。
现在参照图1，其展示在单分成个别件之前以矩阵/阵列一起形成若干个QFN装置。在此实例中，每一QFN封装在个别IC封装的每一侧上形成有四个引线焊盘2。在单分之前，可由铜或其它导电材料形成的暴露的引线焊盘2及暴露的热垫4可浸渍有焊料或以其它方式电镀有焊料可润湿材料，例如锡、锡/铅合金、金及/或另一焊料可润湿材料。可使用所述焊料可润湿材料来实现焊料与下伏导电材料之间的良好接合，且抑制引线焊盘的氧化。
现在参照图2，其显示已在制造工艺期间经单分的QFNIC封装10。QFN装置10具有一顶部侧表面12(包含大体平面正方形或矩形表面)及若干个邻近侧14。在每一侧面14上，暴露周界引线焊盘16。QFNIC封装10还具有底部侧表面18，其包括由导热材料形成以从封装中的IC消散热的暴露的热垫20。周界引线焊盘16从封装的侧14绕封装的底部边缘22延伸到周界区域上。因此，每一周界引线焊盘16具有侧焊盘部分24及底部焊盘部分26。
现在参照图3A及3B，其展示周界引线焊盘16的未经电镀的侧焊盘部分24及经电镀的底部焊盘部分26。在特定例项中，侧焊盘部分24及底部焊盘部分26可具有范围从大约1毫米的百分之十五(0.15mm)到大约1毫米的十分之四(0.4mm)的宽度28。侧焊盘部分24与底部焊盘部分26的宽度可大致相同或彼此差距在1毫米的十分之三(0.3mm)内。侧焊盘部分24可具有范围从大约1毫米的十分之一(0.1mm)到大约1毫米的十分之三(0.3mm)的高度30。底部焊盘部分26可具有范围从大约1毫米的十分之四(0.4mm)到大约1毫米的十分之七(0.7mm)的长度32。然而，这些尺寸仅以举例的方式提供。举例来说，底部焊盘部分26的长度及宽度可由绕QFNIC封装的周界的底部焊盘部分的间距(间隔)确定，其在不同的配置中可变化。
一般来说，QFNIC封装10形成于面板(例如，如上文所描述)上且焊料可润湿材料施加到暴露的热垫20及所述面板上的周界引线焊盘16的暴露部分。通过此类型的制作技术，周界引线焊盘16的底部焊盘部分26具有施加到其上的焊料可润湿材料。然而，由于单分，侧焊盘部分24将不涂覆或电镀有焊料可润湿材料。因此，在此类型的配置中，侧面14上的侧焊盘部分24可遭受氧化及/或减小的可焊接性。举例来说，侧焊盘部分24可由暴露的铜形成，当使用轻微激活的“免清洗”焊剂焊接工艺等时，所述暴露的铜可氧化且导致侧面的可焊接性不一致。
虽然可使用侵略性/高度活性的焊剂来破坏或分解可在侧焊盘部分24上形成的所得金属氧化物，但所述焊剂的腐蚀性质可限制QFNIC封装10的产品寿命。此外，当制造PCB时，期望使用目视相机检查来检查焊接的接点，例如QFNIC封装的引线焊盘与PCB之间的焊接的连接，以用于质量控制。举例来说，目视相机检查可比像X射线检查等检查技术廉价。然而，当QFNIC封装在侧焊盘或侧面缺乏氧化保护时，由于在外围焊盘处形成的不一致的可润湿性、芯吸或焊角形成，可难以分析QFN焊接的接点。
因此，提供具有绕芯片封装的外围的可焊接或焊料可润湿侧焊盘部分的半导体芯片封装。在若干实施例中，在以块格式制造工艺等单分封装之后于芯片封装的暴露的侧面上形成可焊接表面。因此，可在可焊接性不一致的材料(例如，被氧化的铜侧面)上形成可焊接界面，可焊接性不一致可为制造/制作工艺期间的切割或冲压操作的结果。通过提供向上芯吸焊料的侧面表面，所得侧焊盘部分提供高可靠性及/或焊接接点的易于检查性。此外，此类型的芯片封装可提供较小且较廉价的形式因数，且可用于包括(但不限于)医学、军事、汽车、工业及其它市场(例如，需要长寿命产品的地方)在内的行业中。在一些例项中，半导体芯片封装可配置为DFN型封装。在其它例项中，半导体芯片封装可配置为QFN型封装。然而，仅以举例的方式提供这些配置，且这些配置不打算限制本发明。因此，可以其它配置来实施半导体芯片封装。
一种用于通过侧可润湿电镀提供例如DFN型封装或QFN型封装等半导体芯片封装的方法包括：从以块格式形成的封装阵列单分半导体芯片封装；将所述半导体芯片封装没入于电镀液浴中；使所述半导体芯片封装的引线焊盘与所述电镀液浴内的导电接触材料接触；将所述导电接触材料连接到阴极电位；将所述电镀液浴内的阳极连接到阳极电位；及对所述半导体芯片封装的所述引线焊盘进行电解电镀。导电带包括金属化的背衬、安置于所述金属化的背衬上的粘合剂及嵌入于所述粘合剂中的多个导电粒子，所述多个导电粒子电连接到所述金属化的背衬。导电带还可包括在所述粘合剂上形成为呈块格式的封装阵列的多个经单分半导体芯片封装。
实例性实施方案
图4到12图解说明根据本发明的实例性实施方案的具有侧可润湿电镀的集成电路(IC)封装。如图所示，IC封装包括周界引线焊盘，所述周界引线焊盘具有位于所述IC封装的一个或一个以上侧面上的侧焊盘部分。参照图4A，其描述侧可润湿无引线封装150。无引线封装150包括与散热器、裸片附接垫或中心热垫154热接触的集成电路152。连接导线156以导电方式接合于集成电路152与周界引线焊盘158之间。可使用模制化合物168来电及物理分离周界引线焊盘158与热垫154。每一周界引线焊盘158的外部表面电镀有焊料可润湿材料162，使得焊料可润湿材料162大致覆盖每一周界引线焊盘158的底部表面部分164及外侧表面部分166。所述焊料可润湿电镀还大致覆盖中心热垫154的底部外部表面。在若干实施例中，所述电镀跨越周界引线焊盘158及中心热垫154表面在厚度上合理地均匀。电镀162在无引线封装150的每一周界引线焊盘158上提供底部及侧可润湿表面两者。可使用由模制化合物168形成的覆盖物来覆盖周界引线焊盘158、热垫154的顶部侧以及集成电路152及接合导线156。应注意，仅以举例方式提供侧可润湿无引线封装150，且存在除本文中所描绘的IC封装以外的可用以产生侧可润湿无引线封装的各种封装配置。举例来说，本发明中所描述的技术可应用于QFN及DFN封装等。
现在参照图4B，其描述侧可润湿无引线IC封装300，其中在被单分之前，周界引线焊盘158的底部导电表面及热垫154已涂覆、电镀或以其它方式覆盖有焊料可润湿材料。因此，第一或预先存在的焊料可润湿层302大致覆盖周界引线焊盘158的底部表面164且在若干实施例中热垫154。额外的焊料可润湿电镀的层304大致覆盖每一周界引线焊盘158的暴露的外部侧部分166以及周界引线焊盘158的底部部分上的第一层302及热垫154。通过在无引线封装的每一周界引线焊盘的侧焊盘部分以及底部焊盘部分上提供焊料可润湿电镀，在被焊接到PC板时，每一焊盘具有用于芯吸所述焊料的配置，使得焊料焊角在所述底部焊盘部分下面形成且平滑地延伸或沿所述侧焊盘部分向上芯吸。可更容易地使用目视技术而非较昂贵的x射线技术来检查此类型的焊接接点。
参照图5，其描绘焊料电镀浴槽99。焊料电镀浴槽99包括托盘42，托盘42可包含可用以盛纳电镀液44的任何容器或区域。电镀液44可为商业上可购得的溶液，其包含一种或一种以上目标电镀材料经分解离子(例如，锡离子、铅离子、金离子)及/或在电解质中分解的其它金属/导电材料。定位于托盘42的底部附近处的是形成导电接触材料的导电带90。导电带90包括金属化的背衬92，例如由金属化的铝材料形成的背衬等。将含有导电粒子96的粘合剂94施加到金属化的背衬92。举例来说，粘合剂94可含有银、金或其它导电材料(例如，导电聚合物及/或碳基聚合物)粒子或薄片。
粘合剂94与导电粒子96共同形成电连接到金属化的背衬92的导电粘合剂、导电聚合物、导电胶或导电油脂。在一些例项中，导电带90可包括为大致相同高度或大致在同一平面中的表面特征98，例如波纹或凸块。表面特征98可以阵列或另一形式形成。举例来说，可随机地将表面特征98置于导电带90上。在其它例项中，导电带90可具有大致平滑的表面。
现在参照图6，也可提供阳极48，使得其浸没于电镀液44的表面以下一预定距离处，导电带90上方。在若干实施例中，托盘42可为由导电金属或另一导电材料形成的导电托盘，且可将粘合剂94及导电粒子96施加于其上。可将具有周界引线焊盘70的无引线封装68置于焊料电镀浴槽99的电镀液44中。在若干实施例中，周界引线焊盘70的底部焊盘部分可已经涂覆有锡、锡/铅合金或另一焊料可润湿涂层。在其它实施例中，周界引线焊盘70的侧焊盘部分及底部焊盘部分两者可并非先前已涂覆有焊料可润湿材料。导电粒子96经配置以与无引线封装68的引线焊盘70接触，使得所述引线焊盘处于相同电位。举例来说，可将导电带90施加到无引线封装68的底部及/或侧焊盘部分，且可将金属化的背衬92连接到接地，使得导电粒子96可在电镀工艺期间充当阴极。
当将电压施加到阳极48时，电镀液44中的金属离子将沿阳极48与阴极/导电粒子96之间的电场线移动且将其自身附着或沉积到阴极或具有阴极电位的任何金属。由于周界引线焊盘70与阴极/导电粒子96呈导电关系，因此周界引线焊盘还充当吸引电场线的阴极/离子目标。因此，金属离子可大致均匀地对周界引线焊盘70的底部及侧表面两者进行电镀。应注意，在完成电镀工艺之后，可从电镀液44回收与粘合剂94分离的导电粒子96。此外，可利用蚀刻剂及/或溶剂来从无引线封装68清洗掉粘合剂94。
在一个或一个以上实施例中，导电带90支撑在粘合剂上形成为封装阵列(例如，以块格式制造工艺)的多个半导体芯片封装。此外，导电带可经配置以伸展，同时维持金属化的背衬92与嵌入于粘合剂94中的多个导电粒子96之间的电接触。举例来说，当无引线IC封装的面板粘附到导电带90时，可将所述面板单分成个别装置，同时通过粘附到粘合剂94及连接到导电粒子96而仍保持引线焊盘处于相同电位。
参照图7，其描述焊料电镀浴槽40。焊料电镀浴槽40包括托盘42，托盘42可包含可用以在制造环境或另一类型的环境中盛纳电镀液44的任何容器或区域。电镀液44保持于托盘42内。电镀液44可为商业上可购得的溶液，其包含一种或一种以上目标电镀材料的经分解离子(例如，锡离子、铅离子、金离子)及/或在电解质中分解的其它金属/导电材料。从托盘42的底部延伸或突出的是若干个导电接触材料凸块/凹穴46。每一凸块46由例如钛、金等导电材料或另一耐用导电材料制成。凸块的顶部或峰为大致相同高度或大致在同一平面中。凸块46可以阵列或另一形式组织。也可将凸块46随机地放置在托盘42的底部的表面周围。
凸块46经配置以与无引线IC封装的底部焊盘部分接触。凸块46可为半球形、圆柱形、立方体形、锥形或允许每一凸块46在托盘42的底部上方延伸大致相等距离的另一几何形状。在一些例项中，凸块46可具有在大约1毫米的百分之二(0.02mm)与大约1毫米的百分之二十五(0.25mm)之间的横截面宽度。在一些例项中，凸块46在大小及放置上可足够小，使得在抵靠托盘42的底部放置或按压无引线封装时若干个凸块46可触碰此无引线封装的单个底部焊盘部分。每一凸块46连接到其它凸块，使得凸块46具有相同电位。在若干实施例中，凸块46可形成于可移除地置于托盘42的底部上的丝网、网或另一扁平结构化的装置上。在若干实施例中，阳极48可定位于箱或托盘42的一个或一个以上内部壁上。在其它实施例中，当正在对无引线封装底部及侧焊盘部分进行电镀时，可将阳极48可移除地置于或浸没于电镀液44内。
现在参照图8，其描述焊料电镀浴槽50。除焊料电镀浴槽50具有从托盘42的底部向上延伸的导电接触材料的杆状/头发状结构52外，焊料电镀浴槽50类似于焊料电镀浴槽40。导电杆52可由(例如)钛毛或可在焊料电镀浴槽中使用的另一导电金属形成。在若干实施例中，导电杆52可包含导电细丝或纤维。将杆52浸没于电镀液44下。杆52经连接以使得其处于相同电压电位。还可提供阳极48以使得其浸没于电镀液44的表面以下，在杆状/头发状结构52上方。
在若干实施例中，托盘42可为由导电金属或另一导电材料形成的导电托盘且在其中并入有杆52或凸块46。在若干实施例中，托盘42可不导电且/或凸块46或杆52可连接到搁放或附接到托盘42的底部的常见网或可浸没结构，或其可安装或附接到托盘42的底部的顶部表面。
参照图9，其描述包括托盘62的焊料电镀浴槽60，其中电镀液64填充托盘62的至少一部分。导电接触材料的导电凸块66大致定位于托盘62的底部处或附近。凸块66可并入到搁放或安装于托盘62的底部处的单独结构中，或可为托盘62的部分或附接到托盘62。导电凸块66每一者连接到接地，使得其可在电镀工艺期间充当阴极。可将使周界引线焊盘70定位在其底部表面72周围且定位于至少一个侧表面74上的无引线封装68置于焊料电镀浴槽60的电镀液64中。在若干实施例中，周界引线焊盘70的底部焊盘部分76可已经涂覆有锡、锡/铅合金或另一焊料可润湿涂层。在若干实施例中，周界引线焊盘70的侧焊盘部分78及底部焊盘部分76两者可并非先前已涂覆有焊料可润湿材料。
现在参照图10，将无引线IC封装68浸没于焊料电镀浴槽60内的电镀液64下。无引线封装68的底部72(包括周界引线焊盘70)与若干个导电凸块80电接触，所述若干个导电凸块80每一者保持于所述焊料电镀浴槽的底部处或附近且电连接到接地或阴极电位。在电镀液64内提供阳极82。阳极82可切换地连接到预定电压84。当将预定电压施加到阳极82时，电镀液64中的金属离子将沿阳极82与阴极/导电凸块80之间的电场线移动且将其自身附着或沉积到阴极或具有阴极电位的任何金属。由于周界引线焊盘70与阴极/导电凸块80呈导电关系，因此周界引线焊盘也充当吸引电场线的阴极/离子目标。因此，金属离子可大致均匀地对周界引线焊盘70的底部表面76及侧表面78两者进行电镀。
参照图11，其描述其中周界引线焊盘116在焊料电镀浴槽100中电镀焊料可润湿材料的无引线IC封装108。焊料电镀浴槽100包括部分地填充有电镀液104的托盘102。真空套夹106可用以使用真空/吸力来拾起无引线装置108，且接着将无引线装置108置于溶液104中。真空套夹106可抵靠若干个导电凸块或例如瘤状物、杆、头发状结构、针织导电丝网或浸没的结构110(本文中称作“导电凸块”)等其它导电接触材料按压所述无引线装置，使得每一周界引线焊盘116与至少一个导电凸块110导电接触。套夹106或用以收集及浸没无引线装置108的其它装置可具有附接到其的阳极112。可将阳极112附接或置于套夹106上，使得当所述套夹将无引线装置108浸没时，阳极112也将部分或完全地浸没于电镀液104中。
一旦被浸没，将阳极电压114施加到阳极112。电场线在阳极112与导电凸块110之间形成，导电凸块110接地。由于导电凸块110中的一些导电凸块与周界引线焊盘116导电接触，因此电场线也在阳极112与周界引线焊盘116的侧及底部焊盘部分或表面之间延伸。如果无引线装置108也在无引线装置封装的底部的中心区域中具有传导表面(例如，热散热器)，那么此传导表面也将具有延伸到其的电场线。电镀将在导电凸块110的目标阴极区域、周界焊盘116的表面且在若干实施例中无引线封装108的底部上的中心传导表面或散热器上发生。
在若干实施例中，无引线封装可不完全浸没于电镀液下，如图11中通过电镀液水平104a所展示。在此类型的配置中，可绕浸没的无引线封装的壁或绕其边缘放置阳极112a，只要阳极112a也部分或完全地浸没于电镀液中即可。不管阳极112或112a的放置，电镀将沿从阳极112、112a朝向阴极的电场线发生，其中阴极是分解的离子电镀材料的目标。由于周界引线焊盘116与导电凸块110导电接触，因此周界焊盘的侧及底部表面两者可从源自电镀液104内的所沉积金属离子获得大致均匀的焊料可润湿电镀的涂层。
现在参照图12，其描述若干个无引线封装120、121、122及123，其中IC封装同时浸渍于焊料电镀浴槽125中，以便将所述无引线封装的周界引线焊盘126每一者抵靠位于电镀液托盘130的底部处或附近的导电凸块128按压。一个或一个以上阳极132可位于真空管、套夹、转塔、封装固持装置134或其它多部分载体上且提供靠近于且绕无引线封装120、121、122及123的表面及周界引线焊盘126伸展的电场线。在若干实施例中，可同时将一个到至少大约五百(500)个经单分无引线封装浸渍于单个焊料电镀浴槽125中。然而，在其它实施例中，可将多于五百个封装浸渍于焊料电镀浴槽中。应注意，可将额外的阳极133置于焊料电镀浴槽内且绕无引线封装120、121、122及123。
实例性制作工艺
以下论述描述用于制作具有侧可润湿电镀的引线焊盘的集成电路装置的实例性技术，例如侧可润湿DFN或QFN半导体芯片封装等。图13描绘在一实例性实施方案中用于制作集成电路装置的工艺1300，例如图4到12中所图解说明及上文所描述的实例性集成电路装置68、108、120、121、122、123、150及300。在所图解说明的工艺1300中，从以块格式制造工艺形成的封装阵列单分无引线IC封装(框1320)。在若干实施例中，所述无引线IC封装具有包括一个或一个以上暴露的侧焊盘部分的周界引线焊盘。举例来说，参照图4到12，无引线IC封装68可具有包括暴露于其一个或一个以上侧面上的侧焊盘部分78的周界引线焊盘70。周界引线焊盘70可从封装的侧表面74延伸到所述封装的底部表面72周围的周界区域上，以形成底部焊盘部分76。
另一无引线IC封装108可具有暴露于其一个或一个以上侧面上的周界引线焊盘116。另外的无引线IC封装120、121、122及123可具有暴露于其一个或一个以上侧面上的周界引线焊盘126。其它无引线IC封装150及300可具有暴露于其一个或一个以上侧面上的周界引线焊盘158。周界引线焊盘116、126及158可从其相应IC封装的侧表面延伸到所述封装的底部表面周围的周界区域上，以形成底部焊盘部分，如前文所描述。在若干实施例中，底部焊盘部分的表面可为用以形成周界引线焊盘的暴露的导电材料(例如，如图4A中所图解说明)。在其它实施例中，可在单分之前给底部焊盘部分涂覆、电镀或以其它方式覆盖焊料可润湿材料(例如，如图4B中所图解说明)(框1310)。
接下来，将经单分无引线IC封装部分或完全地没入到电镀液浴中(框1330)。在一些实施方案中，可将经单分IC封装组织成堆叠、容器管或其它储存配置，使得可分配IC封装以对周界引线焊盘进行电镀。可单个地(例如，如图9到11中所图解说明)或以群组方式(例如，如图6及12中所图解说明)分配IC封装。当IC封装经分配时，可使用包括真空吸力组件及/或套夹的装备来拾起及定位所述IC封装。此外，可将所述IC封装装载到转塔、搁架及/或另一类型的固持装置中，以便可将其作为群组移动。然而，仅以举例的方式提供用于移动及定位经单分IC封装的技术，且这些技术不打算限制本发明。因此，可使用各种其它技术来定位IC封装。
继续参照上文所描述的图4到12，可将集成电路装置68、108、120、121、122、123、150及300部分或完全地没入于电镀液浴中，例如焊料电镀浴槽40、50、60、99、100及125。使无引线IC封装的引线焊盘(及在一些情况下暴露的热垫)与所述电镀液浴内的导电接触材料接触(框1340)。举例来说，继续参照上文所描述的集成电路装置68、108、120、121、122、123、150及300，可使经单分IC封装的底部焊盘部分与导电凸块46、66、80、110及128、导电头发状结构52、导电带90等接触。放置或按压外围引线焊盘以使其与导电接触材料接触。将导电接触材料连接到接地或阴极电位(框1350)。因此，经由与导电接触材料的接触将IC封装的引线焊盘设定到阴极或接地电位。将电镀液浴内的阳极连接到阳极电位(框1360)。经由阳极将电位施加到电镀液以形成从阳极到处于阴极电位的引线焊盘的电场线。
以此方式，对无引线IC封装的引线焊盘进行电解电镀(框1370)。分解于电镀液中的金属离子沉积于浸没于电镀液中且与导电接触材料接触的各种周界引线焊盘的侧焊盘部分及底部焊盘部分两者上。在一些量的时间之后，可移除来自阳极的电位，且/或可从电镀材料浴移除IC封装。在若干实施例中，无引线IC封装可保持没入于电镀液浴中达变化量的时间，此取决于所要的电镀厚度。举例来说，在一些特定例项中，对引线焊盘进行电镀可花费从大约一分钟(1分钟)到大约五分钟(5分钟)。在其它例项中，电镀可花费少于一分钟(例如，几秒)或多于五分钟。此外，电镀量可依据与电镀液相关联的电镀液温度及/或其它参数而变化。此外，施加到阳极的电压可依据特定电镀液/电解质组合物而变化。举例来说，在一些特定例项中，可阳极电压可在大约四伏(4V)与大约二十伏(20V)之间。
在一些例项中，可将锡、锡/铅合金或其它焊料可润湿电镀施加到引线焊盘，其中电镀材料具有在大约电镀材料的分子厚度到大约1英寸的百万分之五百(500μin)之间的电镀厚度。应注意，电镀材料可大致平滑且跨越周界引线焊盘及可能的暴露的热垫的表面的几乎一致的厚度。然而，导电接触材料(例如，导电凸块46、66、80、110及128、波纹98及/或导电头发状结构52)接触引线焊盘/热垫处可存在一些表面不规则性。所得焊料可润湿电镀可有助于防止镀层下面的铜或其它金属的氧化，增加IC封装的可焊接性，且允许准确地目视检查IC封装与PCB之间的焊接接点等。
继续参照上文所描述的图4到12，可使用(例如)套夹106或封装固持装置134从电镀液浴移除IC封装。可接着(例如)使用(例如)去离子水或另一冲洗技术来将所述IC封装清洗/冲洗掉电镀液。可接着干燥所述IC封装以准备销售。可将多个IC封装储存于例如储存管、盒、带卷轴等容器中，且可使用其它电子部件销售技术来组织及收集所述多个IC封装。可将这些IC封装群组运送给装置零售商、电子器件制造商、终端用户等。
应注意，随着时间，电镀液浴内的导电接触材料(例如，导电凸块46、66、80、110及128以及导电头发状结构52)可变得电镀有电镀材料，因为其从电镀液内的离子形成。当导电接触材料变得涂有电镀材料时，可从导电接触材料清洗掉电镀材料。举例来说，可将导电接触材料浸没于酸浴中，其可能需要一些额外的擦洗。在此类型的实施方案中，导电接触材料可由硬导电金属材料(例如，钛)构成，以承受所述酸与擦洗过程而导电表面不会被显著腐蚀。然而，也可使用其它导电接触材料，例如金或金合金。在此类型的实施方案中，蚀刻或清洗工艺可从导电接触材料移除金属中的一些。在其它例项中，可加热导电接触材料以熔化掉电镀材料。此外，可使用其它类型的清洗、蚀刻、加热技术等而以其它方式从导电接触材料移除电镀材料。
一旦IC封装的制作已完成，则可通过将IC封装的引线焊盘焊接到PCB上的对应连接器来将IC封装连接到所述PCB(框1380)。举例来说，可将IC封装上的一个或一个以上引线焊盘焊接到PCB上的一个或一个以上连接垫。当将IC封装连接到PCB时，可使用目视检查技术来检查IC封装的引线焊盘与PCB之间的焊接的连接(框1390)。举例来说，当IC封装的侧焊盘部分经电镀时，存在芯吸焊料的良好可能性，使得在底部焊盘部分下面产生焊料焊角，且所述焊料填充平滑地延伸或沿所述侧焊盘部分向上芯吸。可更容易地使用例如相机检查等目视检查技术来检查此类型的配置。
结论
尽管已以专用于结构特征及/或工艺操作的语言描述了标的物，但应理解，在所附权利要求书中界定的标的物未必限制于上文所描述的特定特征或动作。而是，上文所描述的特定特征及动作是作为实施所述权利要求书的实例性形式而揭示。

Claims (7)

1.一种导电带，其包含：
金属化的背衬；
粘合剂，其安置于所述金属化的背衬上；及
多个导电粒子，其嵌入于所述粘合剂中，所述多个导电粒子电连接到所述金属化的背衬。
2.根据权利要求1所述的导电带，其中所述粘合剂及所述多个导电粒子包含导电粘合剂、导电聚合物、导电胶或导电油脂中的至少一者。
3.根据权利要求1所述的导电带，其中所述导电带经配置以伸展，同时维持所述金属化的背衬与嵌入于所述粘合剂中的所述多个导电粒子之间的电接触。
4.根据权利要求1所述的导电带，其进一步包含：
多个半导体芯片封装，其在所述粘合剂上形成为呈块格式的封装阵列。
5.根据权利要求4所述的导电带，其中所述多个半导体芯片封装是经单分的。
6.根据权利要求1所述的导电带，其中所述导电带形成凹坑。
7.根据权利要求1所述的导电带，其中所述多个半导体芯片封装中的每一者包含引线焊盘，所述引线焊盘具有经由嵌入于所述粘合剂中的所述多个导电粒子连接到所述金属化的背衬的底部焊盘部分。
CN201510504459.XA 2010-08-09 2011-08-09 用于半导体芯片封装的侧可润湿电镀 Active CN105097563B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US37195510P 2010-08-09 2010-08-09
US61/371,955 2010-08-09
US13/189,857 2011-07-25
US13/189,857 US8642461B2 (en) 2010-08-09 2011-07-25 Side wettable plating for semiconductor chip package
CN201110229915.6A CN102376588B (zh) 2010-08-09 2011-08-09 用于半导体芯片封装的侧可润湿电镀

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201110229915.6A Division CN102376588B (zh) 2010-08-09 2011-08-09 用于半导体芯片封装的侧可润湿电镀

Publications (2)

Publication Number Publication Date
CN105097563A true CN105097563A (zh) 2015-11-25
CN105097563B CN105097563B (zh) 2019-10-18

Family

ID=45555553

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201510504459.XA Active CN105097563B (zh) 2010-08-09 2011-08-09 用于半导体芯片封装的侧可润湿电镀
CN201110229915.6A Active CN102376588B (zh) 2010-08-09 2011-08-09 用于半导体芯片封装的侧可润湿电镀

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201110229915.6A Active CN102376588B (zh) 2010-08-09 2011-08-09 用于半导体芯片封装的侧可润湿电镀

Country Status (2)

Country Link
US (2) US8642461B2 (zh)
CN (2) CN105097563B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110544636A (zh) * 2019-08-13 2019-12-06 广东芯华微电子技术有限公司 一种提高foplp芯片线路良率的封装方法
CN113035722A (zh) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
US11876003B2 (en) 2019-12-24 2024-01-16 Vishay General Semiconductor, Llc Semiconductor package and packaging process for side-wall plating with a conductive film

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102789994B (zh) 2011-05-18 2016-08-10 飞思卡尔半导体公司 侧面可浸润半导体器件
US8618647B2 (en) 2011-08-01 2013-12-31 Tessera, Inc. Packaged microelectronic elements having blind vias for heat dissipation
US9449890B1 (en) * 2013-05-10 2016-09-20 Amkor Technology, Inc. Methods for temporary bussing of semiconductor package substrates
US8809119B1 (en) * 2013-05-17 2014-08-19 Stats Chippac Ltd. Integrated circuit packaging system with plated leads and method of manufacture thereof
JP6244147B2 (ja) * 2013-09-18 2017-12-06 エスアイアイ・セミコンダクタ株式会社 半導体装置の製造方法
CN105895611B (zh) 2014-12-17 2019-07-12 恩智浦美国有限公司 具有可湿性侧面的无引线方形扁平半导体封装
US11348806B2 (en) * 2014-12-23 2022-05-31 Texas Instruments Incorporated Making a flat no-lead package with exposed electroplated side lead surfaces
US10079198B1 (en) * 2017-05-31 2018-09-18 Stmicroelectronics, Inc. QFN pre-molded leadframe having a solder wettable sidewall on each lead
KR20210137143A (ko) * 2019-03-08 2021-11-17 실리코닉스 인코포레이티드 측벽 도금을 갖는 반도체 패키지
CN115662915B (zh) * 2022-12-07 2023-06-02 四川富美达微电子有限公司 一种引线框架矫形检测组件及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751068A (en) * 1994-09-01 1998-05-12 Intel Corporation Tape with solder forms for semiconductor devices
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
CN1387244A (zh) * 2001-03-30 2002-12-25 琳得科株式会社 带导电体的粘接板、半导体装置的制造方法及半导体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3723963B2 (ja) * 2003-06-06 2005-12-07 三井金属鉱業株式会社 メッキ装置および電子部品実装用フィルムキャリアテープの製造方法
JP4164435B2 (ja) * 2003-11-05 2008-10-15 新光電気工業株式会社 電子部品用めっき治具及び電解めっき装置
JP4164443B2 (ja) * 2003-11-26 2008-10-15 新光電気工業株式会社 電子部品用めっき治具及び電解めっき装置
TWI270905B (en) 2004-07-14 2007-01-11 Sanyo Electric Co Solid electrolytic condenser and manufacturing method of the same
US7955953B2 (en) * 2007-12-17 2011-06-07 Freescale Semiconductor, Inc. Method of forming stacked die package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751068A (en) * 1994-09-01 1998-05-12 Intel Corporation Tape with solder forms for semiconductor devices
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
CN1387244A (zh) * 2001-03-30 2002-12-25 琳得科株式会社 带导电体的粘接板、半导体装置的制造方法及半导体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110544636A (zh) * 2019-08-13 2019-12-06 广东芯华微电子技术有限公司 一种提高foplp芯片线路良率的封装方法
CN113035722A (zh) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
US11876003B2 (en) 2019-12-24 2024-01-16 Vishay General Semiconductor, Llc Semiconductor package and packaging process for side-wall plating with a conductive film

Also Published As

Publication number Publication date
US8642461B2 (en) 2014-02-04
CN102376588B (zh) 2016-12-28
CN105097563B (zh) 2019-10-18
US20120032352A1 (en) 2012-02-09
US9318462B1 (en) 2016-04-19
CN102376588A (zh) 2012-03-14

Similar Documents

Publication Publication Date Title
CN102376588B (zh) 用于半导体芯片封装的侧可润湿电镀
EP0181032B1 (en) Solid electrolytic capacitor for surface mounting
KR20060050290A (ko) 반도체장치
US7604727B2 (en) Electroplating method for a semiconductor device
US9184116B2 (en) Method of manufacturing resin-encapsulated semiconductor device, and lead frame
EP0160222B1 (en) Novel nickel/indium alloy for use in the manufacture of a hermetically sealed container for semiconductor and other electronic devices
CN106449440B (zh) 一种具有电磁屏蔽功能的封装结构的制造方法
TW201108363A (en) Semiconductor device and method of manufacturing the same
JP2023126980A (ja) 電気めっきされたダイ取り付けを備える半導体デバイス
US11348806B2 (en) Making a flat no-lead package with exposed electroplated side lead surfaces
CN106298743A (zh) 具有屏蔽效果的封装结构及其制作方法
EP0823719A1 (en) Molded electronic component having pre-plated lead terminals and manufacturing process thereof
TW200908833A (en) Metal plugged substrates with no adhesive between metal and polyimide
US3948736A (en) Method of selective electroplating and products produced thereby
CN108074901A (zh) 具有可湿拐角引线的半导体器件及半导体器件组装方法
EP3835461A1 (en) Substrate carrier for metallic electroplating of substrates
CN208848897U (zh) 电子部件封装
US6791182B2 (en) Semiconductor device
KR101252137B1 (ko) 전해정련을 이용하여 저알파 방사선을 방출하는 주석 제조방법
CN1318651C (zh) 镀敷装置、镀敷方法及半导体装置的制造方法
KR102346708B1 (ko) 리드 프레임, 리드 프레임의 제조 방법, 및 반도체 장치의 제조 방법
JP2023132232A (ja) リードフレームおよびリードフレームの製造方法
DE102011109295A1 (de) Seitenbenetzbare Plattierung für Halbleiterchip-Packages
JP2008190005A (ja) 半導体装置の製造方法
JP2011052258A (ja) 置換めっき層の剥離方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant