TWI594422B - 位於半導體基底中含有有源晶胞區和端接區的半導體功率元件及其製備方法 - Google Patents

位於半導體基底中含有有源晶胞區和端接區的半導體功率元件及其製備方法 Download PDF

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TWI594422B
TWI594422B TW105102024A TW105102024A TWI594422B TW I594422 B TWI594422 B TW I594422B TW 105102024 A TW105102024 A TW 105102024A TW 105102024 A TW105102024 A TW 105102024A TW I594422 B TWI594422 B TW I594422B
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TW201639160A (zh
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李文軍
托魯普 保羅
虹 常
李亦衡
向泱
覺為 鄧
宏勇 薛
一鳴 顧
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萬國半導體股份有限公司
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Description

位於半導體基底中含有有源晶胞區和端接區的半導體功率元 件及其製備方法
本發明涉及關於半導體功率元件的製程及結構，尤其涉及帶有臨界尺寸改良後的深接觸溝槽的製程和結構配置，在深溝槽接頭之間具有縮小的距離。
製備半導體功率元件的傳統方法，仍然面臨在高縱橫比以及溝槽間微小間距的溝槽中，製備電接觸的技術局限。這種技術局限經常成為阻礙進一步減小電子元件尺寸和維度的瓶頸。基於這些原因，目前已採用多種技術，以試圖克服這些局限。
採用光刻製程的傳統技術，用於限定打開接觸溝槽的圖案。通常來說，利用掩膜選擇性地曝光光致抗蝕劑層、沉積光致抗蝕劑層並形成圖案，以限定打開接觸溝槽的位置。然而，由於難以準確對齊，這些製程往往受到限制。另外，光刻曝光的焦點深度以及解析度還會引起需要製造公差的偏差和不準確，並且阻礙製程的能力，以製備帶有次微米間距的接觸溝槽的元件。
在發明人為Xu等人的美國專利公開號US20040058481中，提出了一種用於功率MOSFET的自對準接頭的製備方法。該方法包含藉由沉積在氧化層上的氮化矽掩膜、在基底中蝕刻溝槽、在溝槽壁上製備一柵極氧化層。然後，藉由用多晶矽層填充柵極溝槽，利用溝槽側壁上的柵極氧化層，以自對準柵極匯流排。與之類似，用於源極和本體區的接觸視窗，也限定在氮化矽中，以便在氧化層上方蝕刻氮化矽；接觸視窗覆蓋在源極和本體區上方。在這些接觸視窗的側壁上生長墊片，並自對準沉積在這些接觸視窗中的接觸金屬；接觸視窗作為氮化矽層中的溝槽，在其側壁上具有墊片。在本專利中Xu等人提出的方法，仍然受到首次使用掩膜的局限，限定覆蓋在元件頂面上方的氮化矽層上的位置。由於要允許微小程度的誤差需要公差，以便在平整表面上放置掩膜，因此仍然受到局限，阻礙減小溝槽接頭之間的間距。即使Xu等人提出的不同的接觸金屬，以自對準方式形成在接觸溝槽中，但是接觸溝槽本身沒有利用自對準製程製成。
因此，對於所屬技術領域中具有通常知識者而言，有必要改善功率元件的製備方法，尤其是精確形成在功率元件的整個頂面區域上方不同位置的溝槽接頭，以解決上述技術局限。
本發明的目的在於提出結構特點和元件配置的進步性地改良的製備方法，以便藉由自對準製程精確放置接觸溝槽，從而克服先前技術中的困難與局限。
本發明的一方面在於，提出了一種位於半導體基底中含有有源晶胞區和端接區的半導體功率元件的製備方法，其利用選擇性蝕刻製程，以製備自對準結構可選件；在柵極溝槽之間的檯面結構區域帶有凹槽；凹槽的側壁限定溝槽接頭位置的外邊緣。從而解決了傳統製程中遇到的，相對於柵極溝槽來說不準確放置掩膜所需公差的難題。
本發明的另一方面在於提出一種位於半導體基底中含有有源晶胞區和端接區的半導體功率元件的製備方法，其藉由在外延層的凹陷側壁上進一步進行氧化物墊片，從而進一步縮小和限定凹陷中心處溝槽接頭的位置。因此，藉由精確限定的位置，無需使用傳統方法的掩膜，就可以進行高縱橫比的接觸溝槽蝕刻製程。以完全自對準的方式，精確限定接觸溝槽的位置在檯面結構區域中的源極和本體區正中央。
因此，利用本發明的製程，還可以精確地限定溝槽之間的距離，並且無需傳統方法中要求的不確定性和公差，以便減小功率元件的晶胞間距。
在一較佳實施例中，本發明提出了一種位於半導體基底中含有有源晶胞區和端接區的半導體功率元件，其包含複數個柵極溝槽。複數個柵極溝槽形成在有源晶胞區中半導體基底的頂部，其中每個柵極溝槽都用導電柵極材料部分填充；溝槽的頂部用高密度等離子(HDP)氧化層填充。該半導體功率元件更包含位於柵極溝槽之間的半導體基底的檯面結構區，其中檯面結構區凹陷下去，頂部檯面結構表面垂直位於HDP氧化層的頂面以下，其中覆蓋在導電柵極材料上方的HDP氧化層構 成一凸起邊界限定層，以包圍著柵極溝槽之間有源晶胞區中的凹陷檯面結構區。
在一較佳實施例中，本發明更提出了一種位於半導體基底中含有有源晶胞區和端接區的半導體功率元件的方法，其包含以下步驟：a)在有源晶胞區中半導體基底的頂部，打開複數個柵極溝槽，並用導電柵極材料填充每個柵極溝槽，然後從溝槽頂部蝕刻掉導電柵極材料；b)沉積高密度等離子(HDP)氧化層，並且在頂面上方製備硼磷矽玻璃(BPSG)絕緣層，然後利用自對準接觸(SAC)光致抗蝕劑掩膜，進行自對準接觸蝕刻，以便從未覆蓋區域中半導體基底的頂面，除去BPSG絕緣層和HDP氧化層；以及c)進行檯面結構凹陷蝕刻，以蝕刻半導體基底，形成檯面結構凹陷，頂部檯面結構表面垂直在HDP氧化層的頂面下方，並覆蓋在導電柵極材料上方，以構成一凸起邊界限定層，其包圍著柵極溝槽之間有源晶胞區中的凹陷檯面結構區。
閱讀以下詳細說明並參照圖式之後，本發明的這些和其他的特點和優勢，對於所屬技術領域中具有通常知識者而言，無疑將顯而易見。
110‧‧‧外延層
112、112’‧‧‧硬掩膜
113‧‧‧光致抗蝕劑掩膜
115、115’‧‧‧溝槽
120‧‧‧柵極氧化層
130‧‧‧柵極溝槽
130’‧‧‧多晶矽拾取柵極
130”‧‧‧晶矽層
132‧‧‧光致抗蝕劑掩膜
140‧‧‧本體箝位層(BCL)
145‧‧‧高密度等離子體(HDP)氧化層、低溫氧化(LTO)層
148‧‧‧硼磷矽玻璃(BPSG)絕緣層
149‧‧‧自對準接觸(SAC)光致抗蝕劑掩膜
150‧‧‧本體區
155‧‧‧凹陷
160‧‧‧源極區
165、165’、165”‧‧‧墊片層
168、174‧‧‧開口
170‧‧‧接觸注入區
180、180’、180”‧‧‧接頭
190-G‧‧‧柵極襯墊金屬
190-S‧‧‧源極金屬
g‧‧‧縫隙
圖1A和1B表示利用本發明的方法和結構可選件，製備半導體功率元件的側剖面圖。
圖1C表示半導體功率元件的特殊結構可選件的側剖面圖，用於圖1A所示的元件。
圖2A至2T表示圖1和1A所示本發明的半導體功率元件的製程的一系列剖面圖。
圖1A表示利用本發明的製程步驟，以製備帶有深溝槽接觸結構的功率元件的側剖面圖。功率元件位於N-型外延層110中；N-型外延層110形成在N-型半導體基底(圖中沒有表示出)上方。半導體功率元件包含一有源晶胞區，其在頂部源極金屬190-S覆蓋的區域以及被柵極襯墊金屬190-G覆蓋的端接區上方延伸。
功率元件包含複數個柵極溝槽130，其形成在墊有柵極氧化層120的深溝槽115中；每個柵極溝槽130都被P-型本體區150包圍；本體區150包圍著N-型源極區160。功率元件更包含複數個源極/本體接頭180，其作為深溝槽115的接頭180。每個深溝槽115都穿過HDP氧化層145，在源極區160下方垂直延伸，然後穿過本體區150的頂部，觸及形成在本體區150中的接觸注入區170，並用金屬層填充，以構成源極/本體接頭180。每個源極/本體接頭180更直接接觸到源極金屬190-S；源極金屬190-S覆蓋在HDP氧化層145的頂部和墊片層165上方。源極/本體接頭180的中心與兩個鄰近的有源溝槽115之間的檯面結構中心對準。
然而，在最後一有源溝槽115和柵極拾取溝槽115’之間的檯面結構中，源極/本體接頭180”偏離檯面結構的中心，而更靠近最後一有源溝槽115。在本實施例中，半導體功率元件更包含一本體箝位層(BCL)140，其作為硼注入層，用於嵌制BVdss。多晶矽柵極拾取130’形成在深柵極拾取溝槽115’中；墊有柵極氧化層120藉由拾取接頭180’ 觸及柵極襯墊金屬190-G，穿過HDP氧化層145和BPSG層148，而垂直延伸穿過多晶矽柵極拾取130’的頂部；柵極拾取130’的寬度大於有源晶胞區中柵極溝槽130的寬度。分隔源極金屬190-S和柵極襯墊金屬190-G的縫隙g延伸穿過HDP氧化層145及BPSG層148的邊緣；縫隙g與更靠近有源溝槽115的柵極拾取溝槽115’的溝槽側壁對準。
圖1B表示本發明的一種可選功率元件的側剖面圖，該元件除了端接區不包含BCL層140之外，其他都與圖1A所示的功率元件類似。
圖1C表示圖1A所示元件的半導體功率元件的專用結構可選件。確切地說，源極/本體溝槽接頭180的寬度減至0.1至0.2微米，例如0.13微米；深接觸溝槽之間的間距減至0.2至0.3微米，例如0.25微米。
圖2A至2T表示依據本發明的結構和方法，為減小圖1A所示半導體功率元件的晶胞間距，製備深溝槽接觸結構的製程步驟的一系列側剖面圖。在圖2A中，熱氧化層為硬掩膜112生長在N-型外延層110上方。外延層110形成在N-型半導體基底(圖中沒有表示出)上方。熱氧化層112的厚度大約為2700埃。在圖2B中，對於有源溝槽來說，溝槽光致抗蝕劑掩膜113的臨界尺寸(CD)約為0.25微米；對於柵極拾取溝槽來說，其臨界尺寸約為0.9微米；溝槽光致抗蝕劑掩膜113用於使硬掩膜112形成圖案，以構成溝槽硬掩膜112’，然後除去光致抗蝕劑掩膜113，如圖2C所示。
在圖2D中，藉由蝕刻製程打開溝槽115、115’；有源溝槽115的溝槽深度約為1.45微米。打開的溝槽側壁與基底的頂面並不完全垂直，而是呈86.5度角。溝槽蝕刻製程之後，進行CARO清潔製程，但具 有1200埃左右層厚的一部分硬掩膜112’仍然存在。在圖2E中，利用帶有HF的標準的清潔1(SC1)製程，進行犧牲氧化物預清潔製程，以除去厚度50埃左右的氧化層，然後生長另一100埃左右的犧牲氧化層，並除去130埃的目標氧化層。然後呈現出厚度310埃左右的柵極氧化層120，其覆蓋在溝槽側壁上方。剩餘硬掩膜氧化層112’的厚度約為1000埃。在圖2F中，原位磷摻雜多晶矽層130”沉積在溝槽115、115’中以及硬掩膜112’的表面上方，藉由化學-機械平整(CMP)製程，使多晶矽層130”和硬掩膜112’的頂面平整，如圖2G所示。剩餘硬掩膜112’的厚度約為800埃。然後利用CARO進行預退火清潔製程、標準的清潔1(SC1)和標準的清潔2(SC2)清潔製程，然後在1150攝氏度左右的溫度下在多晶矽層130”上進行多退火製程。
在圖2H中，繼續利用BCL光致抗蝕劑掩膜132，進行BCL注入的複數個步驟。在一典型實施例中，注入包含：a)在2100Kev下，注入摻雜濃度為2E15cm-3的BF2摻雜物；b)在100Kev下，注入摻雜濃度為1E15cm-3的硼摻雜物；c)在460Kev下，注入摻雜濃度為2E12cm-3的硼摻雜物；以及d)在700Kev下，注入摻雜濃度為2E12cm-3的硼摻雜物，以構成BCL層140。在圖2I中，除去BCL注入光致抗蝕劑掩膜132(見圖2H)，首次進行氧化物突破蝕刻，以除去晶矽層130上方300埃的硬掩膜112’的頂部。然後，藉由多晶矽回刻製程，以將多晶矽層130”(見圖2G)蝕刻到矽基底110頂面下方約0.4微米的深處，以在溝槽115和115’中構成柵極溝槽130和多晶矽拾取柵極130’。剩餘的硬掩膜氧化層112’厚度約為200埃。
在圖2J中，製程繼續沉積層厚3000埃左右的HDP氧化層145，然後在HDP氧化層145上方製備層厚約為4300埃左右的BPSG層148。在圖2K中，利用自對準接觸(SAC)光致抗蝕劑掩膜149，進行自對準接觸氧化物蝕刻，以從未覆蓋的部分上除去HDP氧化層145和BPSG層148，並且在矽基底110的頂面停止；帶掩膜的蝕刻之後，HDP氧化層145和BPSG層148的邊緣對準到柵極拾取溝槽115’的溝槽側壁，更靠近有源溝槽115。在圖2L中，利用檯面結構凹陷蝕刻，以蝕刻矽基底，以形成凹陷深度0.3微米左右的檯面結構凹陷155。在圖2M中，除去光致抗蝕劑掩膜149(見圖2L)，然後在100Kev和600Kev之間的能量水準下，用硼離子進行全面本體注入，以構成本體區150。在圖2N中，繼續藉由全面注入，在80Kev下利用摻雜濃度約為4E15cm-3的砷摻雜物，以製備源極區160，然後在950攝氏度下進行30秒退火製程。在圖2O中，利用低溫氧化物沉積，以在結構上方製備一800埃左右的薄的低溫氧化(LTO)層145，並藉由全面氧化物蝕刻製程(例如等離子體幹蝕刻)，以在低溫氧化層145的每個側面形成一氧化物墊片。然後，在圖2P中，進行接觸蝕刻(例如等離子體幹蝕刻)打開接觸開口168，以在檯面結構表面下方接觸溝槽(見圖2O)的深度為0.25微米。如圖2O所示，兩個有源溝槽115之間的檯面結構上方；一對墊片層165是藉由檯面結構的中心對稱的，以致於接觸開口168(見圖2P)的中心與檯面結構的中心基本對準。然而，在最後一有源溝槽115和柵極拾取溝槽115’之間的檯面結構中，連接到低溫氧化層145和BPSG層148邊緣的墊片層165”，比連接到最後一有源溝槽115上方低溫氧化層145側面上的墊片層165和墊片層165’更厚且更高，以致 於墊片層165’和165”形成的接觸開口的中心，偏離最後一有源溝槽115和柵極拾取溝槽115’之間的檯面結構的中心，而是更靠近最後一有源溝槽115。墊片層165’的尺寸與墊片層165的尺寸基本相同。在圖2Q中，在接觸開口168的底部製備接觸注入區170，例如在20Kev下摻雜濃度1E14cm-3的BF2摻雜物。在圖2R中，利用多晶矽拾取接觸掩膜，以打開多晶矽拾取接觸開口174。
在圖2S中，除去掩膜後，藉由快速熱退火(RTA)，以在開口168和174(圖中沒有表示出)的側面沉積勢壘層，例如Ti/TiN勢壘層，然後用鎢填充接觸溝槽168(圖2Q)和174(見圖2R)並回刻，以形成鎢接頭(W-接頭)180、180’和180”，源極/本體接頭180的中心與兩個鄰近有源溝槽115之間的檯面結構的中心基本對準，但源極/本體接頭180”偏離對應檯面結構的中心，更靠近最後一有源溝槽115。在圖2T中，藉由製備源極金屬190-S和柵極襯墊金屬190-G並形成圖案，以及標準的鈍化製備和形成圖案(沒有明確表示出)，完成製程。如上所述，隔開源極金屬190-S和柵極襯墊金屬190-G的縫隙g，穿過HDP氧化層145和BPSG層148的邊緣延伸，與更靠近有源溝槽115的柵極拾取溝槽115’的溝槽側壁基本對準。
儘管本發明的內容已經藉由上述較佳實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在所屬技術領域中具有通常知識者閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由發明申請專利範圍來限定。
110‧‧‧外延層
115、115’‧‧‧溝槽
120‧‧‧柵極氧化層
130‧‧‧柵極溝槽
130’‧‧‧多晶矽拾取柵極
140‧‧‧本體箝位層(BCL)
145‧‧‧高密度等離子體(HDP)氧化層、低溫氧化(LTO)層
148‧‧‧硼磷矽玻璃(BPSG)絕緣層
150‧‧‧本體區
160‧‧‧源極區
165‧‧‧墊片層
170‧‧‧接觸注入區
180、180’、180”‧‧‧接頭
190-G‧‧‧柵極襯墊金屬
190-S‧‧‧源極金屬
g‧‧‧縫隙

Claims (22)

  1. 一種位於半導體基底中含有有源晶胞區和端接區的半導體功率元件，其包含：複數個柵極溝槽和一柵極拾取溝槽，形成在該半導體基底的頂部，其中各該柵極溝槽都用一導電柵極材料部分填充，各該柵極溝槽頂部由一高密度等離子體(HDP)氧化層填充，該柵極拾取溝槽用一導電柵極材料部分填充，頂部由一高密度等離子體(HDP)氧化層和一硼磷矽玻璃(BPSG)絕緣層填充，該導電柵極材料電連接一頂部柵極襯墊金屬；以及一檯面結構區，其位於各該柵極溝槽之間的該半導體基底，其中該檯面結構區相對於該HDP氧化層的頂面凹陷，頂部檯面結構表面位於該HDP氧化層的頂面下方，其中該HDP氧化層覆蓋在該導電柵極材料上方，構成凸起邊緣限定層，包圍著該複數個柵極溝槽之間的該有源晶胞區中的一凹陷檯面結構區，一源極金屬層，其位於該HDP氧化層上方，分隔該源極金屬層和該頂部柵極襯墊金屬的一縫隙穿過該HDP氧化層和該硼磷矽玻璃(BPSG)絕緣層的邊緣延伸，該縫隙與更靠近該柵極溝槽的該柵極拾取溝槽的溝槽側壁對準。
  2. 如申請專利範圍第1項所述的半導體功率元件，更包含：一低溫氧化(LTO)層，連接到該HDP氧化層的側壁，該LTO層限定一檯面結構中心區位於該凹陷檯面結構區的中心部分，以蝕刻該檯面結構中心區的一接觸溝槽。
  3. 如申請專利範圍第2項所述的半導體功率元件，其中該接觸溝槽限定在該檯面結構中心區的該半導體基底中向下垂直打開。
  4. 如申請專利範圍第3項所述的半導體功率元件，更包含：一接觸注入區，其位於該接觸溝槽的底面下的該半導體基底中。
  5. 如申請專利範圍第3項所述的半導體功率元件，更包含：一導電接觸材料，其填充該接觸溝槽。
  6. 如申請專利範圍第4項所述的半導體功率元件，更包含：一導電接觸材料，其填充該接觸溝槽並且連接在該接觸溝槽的底面以下的該接觸注入區。
  7. 如申請專利範圍第1項所述的半導體功率元件，更包含：一本體區以及一源極區，該本體區位於該凹陷檯面結構區下方的該半導體基底中，該源極區包圍著該本體區頂部，該源極區導電類型與該本體區相反。
  8. 如申請專利範圍第6項所述的半導體功率元件，更包含：一本體區以及一源極區，該本體區位於該凹陷檯面結構區下方的該半導體基底中，該源極區包圍著該本體區頂部，該源極區導電類型與該本體區相反，其中該接觸溝槽穿過該源極區，並連接位於該接觸溝槽底面下方的該接觸注入區，該接觸溝槽位於該本體區中。
  9. 如申請專利範圍第8項所述的半導體功率元件，更包含： 一源極金屬層，其位於該HDP氧化層和該接觸溝槽上方，並與填充該接觸溝槽的導電材料相接觸，以便電連接到該源極區和該本體區。
  10. 如申請專利範圍第8項所述的半導體功率元件，更包含：一本體箝位層(BCL)，其導電類型與該本體區相同，在該有源晶胞區週邊區域中該柵極溝槽的底面下方垂直延伸。
  11. 如申請專利範圍第3項所述的半導體功率元件，其中：該接觸溝槽的寬度約為0.1至0.15微米。
  12. 如申請專利範圍第1項所述的半導體功率元件，其中：該柵極溝槽的寬度約為0.25微米，鄰近該柵極溝槽之間的距離約為0.5微米。
  13. 一種在半導體基底中製備含有有源晶胞區和、端接區的半導體功率元件的方法，其包含：在該半導體基底的頂部，打開複數個柵極溝槽和一柵極拾取溝槽，並用一導電柵極材料填充各該柵極溝槽，然後從該柵極溝槽頂部蝕刻掉該導電柵極材料；沉積一高密度等離子體(HDP)氧化層，並在頂面上方製備一硼磷矽玻璃(BPSG)絕緣層，然後利用一自對準接觸(SAC)光致抗蝕劑掩膜，進行自對準接觸蝕刻，以便從未覆蓋區域中該半導體基底的頂面，除去該BPSG絕緣層和該HDP氧化層，待掩膜的蝕刻之後，該高密度等離子體(HDP)氧化層和該硼磷矽玻璃(BPSG)絕緣層的邊緣對準到該柵極拾取溝槽的溝槽側壁，更靠近該柵極溝槽；以及 進行檯面結構凹陷蝕刻，以蝕刻該半導體基底，形成檯面結構凹陷，頂部檯面結構表面垂直在該HDP氧化層的頂面下方，覆蓋在該導電柵極材料上方，構成凸起邊界限定層，包圍著該柵極溝槽之間該有源晶胞區中的一凹陷檯面結構區，製備一源極金屬和一柵極襯墊金屬，分隔該源極金屬和該柵極襯墊金屬的一縫隙穿過該等離子體(HDP)氧化層和該硼磷矽玻璃(BPSG)絕緣層的邊緣延伸，該縫隙與更靠近該柵極溝槽的該柵極拾取溝槽的溝槽側壁對準。
  14. 如申請專利範圍第13項所述的方法，更包含：在該HDP氧化層的側壁上沉積一低溫氧化(LTO)層，以限定該凹陷檯面結構區中心部分中的檯面結構中心區。
  15. 如申請專利範圍第14項所述的方法，更包含：藉由檯面結構蝕刻以蝕刻該半導體基底，以打開一接觸溝槽。
  16. 如申請專利範圍第15項所述的方法，更包含：在該接觸溝槽底面下方的該半導體基底中，製備一接觸注入區。
  17. 如申請專利範圍第16項所述的方法，更包含：用一導電接觸材料填充該接觸溝槽。
  18. 如申請專利範圍第13項所述的方法，更包含：在該凹陷檯面結構區下方的該半導體基底中注入一本體區，然後在該本體區的頂部注入導電類型相反的一源極區。
  19. 如申請專利範圍第18項所述的方法，更包含： 在該HDP氧化層的側壁上沉積該LTO層，以限定該凹陷檯面結構區中心部分中的檯面結構中心區；藉由檯面結構蝕刻，以蝕刻該半導體基底，以打開一接觸溝槽，穿過該源極區，該接觸溝槽位於該本體區中，在該接觸溝槽底面下方的該半導體基底中，製備一接觸注入區；以及用一導電接觸材料填充該接觸溝槽。
  20. 如申請專利範圍第15項所述的方法，其中：打開該接觸溝槽的製程包含打開寬度在0.1至0.15微米左右的該接觸溝槽。
  21. 如申請專利範圍第13項所述的方法，其中：打開該柵極溝槽的製程包含打開寬度約為0.25微米的該柵極溝槽，鄰近該柵極溝槽之間的距離約為0.5微米。
  22. 如申請專利範圍第18項所述的方法，更包含：製備導電類型與該本體區相同的一本體箝位層(BCL)，該BCL在該有源晶胞區週邊區域中的該柵極溝槽的底面下方垂直延伸。
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