TWI649836B - 用於放置在具有高ｋ介電閘極覆蓋體之半導體主動區內之閘極接觸的方法及設備 - Google Patents

用於放置在具有高ｋ介電閘極覆蓋體之半導體主動區內之閘極接觸的方法及設備 Download PDF

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TWI649836B
TWI649836B TW106106416A TW106106416A TWI649836B TW I649836 B TWI649836 B TW I649836B TW 106106416 A TW106106416 A TW 106106416A TW 106106416 A TW106106416 A TW 106106416A TW I649836 B TWI649836 B TW I649836B
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恩德 拉伯特
瑞龍 謝
張洵淵
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格羅方德半導體公司
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Abstract

一種方法，提供在Rx區中具有FinFET之結構，該FinFET包括通道、源極/汲極(S/D)區及閘極，該閘極包括閘極金屬。在具有高k介電性襯墊與核心之閘極上方形成覆蓋體。該閘極之諸側上布置溝槽矽化物(TS)。使該TS凹陷至高於該閘極之層階且低於該覆蓋體之層階的層階。在該結構上方布置氧化物層。在該Rx區裡的氧化物層內圖型化CB溝槽，以在該CB溝槽之中間部分處使核心與襯墊曝露。相對於襯墊而選擇性蝕刻核心，以將CB溝槽延展至閘極金屬處之底端。金屬化CB溝槽以形成CB接觸部。

Description

用於放置在具有高K介電閘極覆蓋體之半導體主動區內之閘極接觸的方法及設備
本發明係關於半導體裝置及其製作方法。更具體地說，本發明係關於一種在半導體結構之主動區內置放閘極接觸部之方法及設備。
先前技術半導體技術(例如：40奈米(nm)、14nm及更先進的技術節點)目前在閘極結構之一部分上布置有大部分閘極(CB)接觸部，該部分位於任何主動(Rx)區外側及隔離區上方，諸如淺溝槽隔離(STI)區、深溝槽隔離區或類似者上方。目的在於防止電氣短路至源極/汲極(CA)接觸部或下層溝槽矽化物(TS)層的高風險。
CB接觸部短路至TS層的可能性特別會造成問題。原因在於，TS層縱向跨佈整個Rx區延展，為的是要確保即使在最壞情況的錯準條件下，與鰭片陣列中之FinFET之源極/汲極(S/D)有適當的電接觸。因此，即使源極/汲極接觸部可位於Rx區之局部化區域中離CB接觸部 夠遠處以防短路，但TS層無法如此。
在先前技術10nm技術及更先進的技術中，閘極電極金屬上方的自對準接觸(SAC)氮化物覆蓋體用於防止CA接觸部與閘極金屬之間出現短路。SAC覆蓋體是由單一材料所組成，典型為氮化矽(SiN)，其大體上與上方布置有SAC覆蓋體之閘極間隔物具有相同或類似的材料組成。於閘極間隔物與SAC覆蓋體之間，閘極金屬與TS區完全隔離。在有此類覆蓋體的情況下，有可能在閘極金屬之層階下面做出深TS凹口，以企圖避免短路至潛在布置於Rx區中之CB接觸部。
不過，還是有問題，關於TS層可凹陷到多深而不會不可接受地使穿過TS層的電阻增加，這方面仍有所限制。因此，即是有了此一深TS層凹口，布置於閘極上方之CB接觸部仍與凹陷之TS變得太過接近而無法可靠製造。
在Rx區外側置放CB接觸部不利於擴縮，對於10nm技術節點及更先進節點尤其如此。另外，布置於隔離區上方之CB接觸部有另外的設計要求，對於比例縮小又造成更多問題。舉例而言，隔離區上方之CB接觸部必須總是位於兩個Rx區之間，必須在CB接觸部與鰭片與TS區之間具有最小間隔，諸如此類等等。
因此，需要有一種能夠在半導體結構之Rx區內置放CB接觸部之方法及設備。此外，此類方法及設備需要具備能可靠製造性。
本發明藉由提供一種在半導體結構之Rx區內置放CB接觸部之方法與設備，提供優於先前技術之優點與替代方案。此外，該等方法與設備不僅改良半導體結構之尺寸調整能力，而且還具備可輕易製造性。
一種根據本發明之一或多項態樣在半導體結構之Rx區中置放CB接觸部之方法，包括：提供在Rx區中布置有FinFET之結構。該FinFET包括布置於一對源極/汲極區之間的通道、及布置於該通道上方之閘極(CB)。該閘極包括布置於閘極間隔物之間的閘極金屬。該閘極上方形成覆蓋體，該覆蓋體具有圍繞內核布置之高k介電性外襯墊。在該源極/汲極區上方該閘極之相對側上形成溝槽矽化物(TS)層。使該TS層凹陷至高於該閘極之層階且低於該覆蓋體之層階的層階。在該結構上方布置氧化物層。在氧化物層內圖型化CB溝槽，以在該CB溝槽之中間部分處使核心曝露。CB溝槽位於Rx區內。相對於該襯墊而選擇性蝕刻該核心，以使該CB溝槽進一步延展至溝槽底端，並且使該閘極金屬曝露。金屬化該CB溝槽以形成電連接至該閘極金屬之CB接觸部。
在本發明之另一態樣中，一種半導體結構，包括布置於Rx區中之FinFET。該FinFET包括布置於一對源極/汲極區之間的通道、及布置於該通道上方之閘極。該閘極包括布置於閘極間隔物之間的閘極金屬。布置於該閘極上方之覆蓋體，其包括圍繞內核布置之高k介電性外襯墊。該覆蓋體與核心自該閘極向上 延展至實質相同第一覆蓋體層階。在該源極/汲極區上方該閘極之相對側上布置溝槽矽化物(TS)層。該TS層具有高於該閘極之層階且低於該覆蓋體層階的層階。在該結構上方布置氧化物層。在氧化物層內及Rx區上方布置CB溝槽。該CB溝槽向下延展至實質位於該覆蓋體層階處之溝槽中間部分，並且自該中間部分進一步延展至溝槽底端。該溝槽底端包括該閘極金屬。CB接觸部布置於該CB溝槽內並且電連接至該閘極金屬。
100‧‧‧半導體結構
102‧‧‧基材
104‧‧‧鰭片
106‧‧‧主動區
108‧‧‧虛設閘極
110‧‧‧源極/汲極區
112‧‧‧主動閘極
114‧‧‧隔離區
116‧‧‧FinFET
118‧‧‧通道
120‧‧‧閘極金屬
122‧‧‧閘極間隔物
124‧‧‧層間介電質、ILD
126‧‧‧第一層階
128‧‧‧第二層階
130‧‧‧襯墊層
131‧‧‧保護層
132‧‧‧覆蓋體
134‧‧‧襯墊
136‧‧‧內核
138‧‧‧TS層
140‧‧‧第三層階
142‧‧‧氧化物填充層
144‧‧‧CA溝槽
146‧‧‧CB溝槽
148‧‧‧距離
150‧‧‧有機平坦化層
152‧‧‧中間部分
154‧‧‧距離
156‧‧‧溝槽底端
160‧‧‧CA接觸部
162‧‧‧CB接觸部
搭配附圖經由以下詳細說明將會更完全理解本發明，其中：第1A圖根據本發明，是半導體結構在中間製造階段的簡化俯視平面圖；第1B圖根據本發明，是第1A圖沿著線條1B-1B取看的簡化截面圖；第2圖根據本發明，是第1B圖有閘極凹陷之後的截面圖；第3圖根據本發明，是第2圖具有保護層及布置於其上之襯墊層的截面圖；第4圖根據本發明，是第3圖有保護層及襯墊層受非等向性蝕刻而使閘極之閘極金屬曝露的截面圖；第5圖根據本發明，是第4圖有覆蓋體形成於其上的截面圖；第6圖根據本發明，是第5圖有TS層布置於其上的截面圖； 第7圖根據本發明，是第6圖有TS層凹陷的截面圖；第8圖根據本發明，是第7圖有氧化物層布置於其上的截面圖；第9A圖根據本發明，是第8圖展示半導體結構100之特徵的俯視平面圖，該特徵下鋪於氧化物層(以假想線邊界表示)，其中氧化物層中布置一對CA溝槽，而虛線周界表示氧化物層中尚待形成CB溝槽的目標位置。
第9B圖根據本發明，是第9A圖沿著線條9B-9B取看的簡化截面圖；第9C圖根據本發明，是第9A圖沿著線條9C-9C取看的簡化截面圖；第10A圖根據本發明，是第9B圖具有布置於其上之有機平坦化層(OPL)、及布置於該OPL內之CB溝槽的截面圖；第10B圖根據本發明，是第9C圖具有OPL布置於其上的截面圖；第11A圖根據本發明，是第10A圖具有蝕刻於氧化物層內之CB溝槽的截面圖；第11B圖根據本發明，是第10B圖的截面圖；第12A圖根據本發明，是第11A圖具有向下蝕刻至閘極之閘極金屬之CB溝槽的截面圖；第12B圖根據本發明，是第11B圖的截面圖；第13A圖根據本發明，是第12A圖具有經金 屬化用以形成CB接觸部之CB溝槽的截面圖；以及第13B圖根據本發明，是第12B圖具有經金屬化用以形成CA接觸部之CA溝槽的截面圖。
現將說明某些例示性具體實施例以便整體理解本文所揭示方法、系統及裝置其結構、功能、製造及使用之原理。附圖中繪示這些具體實施例之一或多項實施例。所屬技術領域中具有通常知識者將會理解本文中具體所述、及附圖中所示之方法、系統及裝置為非限制性例示性具體實施例，而且本發明之範疇僅由申請專利範圍來界定。搭配一項例示性具體實施例所示或所述之特徵可與其它具體實施例之特徵組合。此類修改及變動用意是要包括於本發明之範疇內。
第1A至13B圖根據本發明，繪示用於在半導體結構之主動(Rx)區內置放閘極(CB)接觸部之一種方法與設備的各項例示性具體實施例。
請參閱第1A及1B圖，介紹根據本發明之半導體結構100在中間製造階段沿著線條1B-1B取看的簡化俯視平面圖及簡化截面圖之例示性具體實施例。在程序流程之這個階段，半導體結構100包括具有鰭片104之基材102，該鰭片自基材102起向上垂直延展，並且跨佈該基材水平延展，用以界定基材102之主動區106。鰭片104布置於跨佈基材102之主動區106延展之平行鰭片陣列中(看第1A圖最清楚)。鰭片104在虛設閘極108終止，其位在 主動區106之邊緣處跨佈鰭片104之遠端而側向延展。虛設閘極108用於誘使源極/汲極區110在鰭片104位於虛設閘極108與相鄰主動閘極112之間的部分上對稱磊晶生長。
所示雖然僅一個主動閘極112，但主動閘極112仍可以是沿著主動區106內之鰭片104布置的複數個主動閘極112(例如：從數個到數千個及更大數量)。主動閘極112大體上垂直於主動區106內之鰭片104延展，並且亦可實質延展到隔離區114內。另外，所示雖然僅兩個源極/汲極區110，典型仍有源極/汲極區110磊晶生長到介於主動區106內許多主動閘極112的各者之間、及介於主動區106之邊界處之主動閘極112與虛設閘極108之間的鰭片104內。
與主動區106毗連旳是隔離區114，諸如淺溝槽隔離(STI)區、深溝槽隔離區或類似者，其用於使主動區106與半導體結構100上各種其它主動區(圖未示)分開。隔離區114典型為由非晶介電材料所組成，諸如可流動氧化物(FOX)或類似者。
鰭式場效電晶體(FinFET)116布置於主動區106之鰭片104內。FinFET 116包括一對源極/汲極區110及布置於其之間的通道118。主動閘極112布置於通道118上方，並且可操作成用以控制穿過通道118及介於源極/汲極區110之間的電氣連續性。主動閘極112包括布置於一對閘極間隔物122之間的閘極金屬(或閘極金屬堆疊)120。要注意的是，虛設閘極108具有如主動閘極112般確 切的結構，差別在於虛設閘極未布置於主動通道118上方並且部分延展到隔離區114內沒有主動裝置處。
閘極間隔物122是由介電材料所組成，諸如SiN、SiBCN或類似者。對於本特定例示性具體實施例，閘極間隔物122是SiBCN。
閘極金屬120典型為閘極金屬堆疊，其大體上包括三個主要結構群組(圖未示)。那三個主要結構為：閘極介電層(典型為高k介電材料)、功函數金屬結構(典型為TiN、TaN、TiCAl、其它金屬氮化物或類似材料)及閘極電極金屬(典型為Al、W、Cu或類似金屬)。閘極介電層用於使功函數金屬結構及閘極電極與基材電氣絕緣。功函數金屬結構大體上是金屬氮化物，其提供適當FinFET操作所需要的功函數，但電阻率典型比閘極電極大10到100倍。閘極電極是具有很低電阻率之金屬。
布置於源極/汲極區110上方且介於主動閘極112與虛設閘極108之間的是層間介電質(ILD)124，其典型為由諸如SiO2之氧化物所組成。ILD 124自鰭片104向上延展至鰭片104頂端上面之第一層階(即高度)126。該第一層階在程序流程之這個階段，實質等於主動閘極112及ILD 124之高度。
請參閱第2圖，虛設閘極108和主動閘極112接著向下凹陷至第二層階128。第二層階128是經完全處理之半導體結構100中之鰭片104上面的虛設閘極108和主動閘極112之最後層階(高度)。可使閘極間隔物122及閘 極金屬120在兩個不同的非等向性蝕刻程序中凹陷，諸如反應性離子蝕刻(RIE)程序或類似者。
請參閱第3圖，在半導體結構100上方布置襯墊層130。大體上，可透過諸如原子層沉積(ALD)程序或類似程序，在ILD 124及虛設閘極108和主動閘極112之曝露表面上方保形塗佈襯墊層。該襯墊層大體上是一種高k介電質，具有第一材料組成，諸如二氧化鉿(HfO2)、氮化物矽酸鉿(HfSiON)或類似者。對於本特定例示性具體實施例，襯墊層是HfO2。襯墊層大體上非常薄，而且典型為在3nm至6nm厚的範圍內。
由於襯墊層如此之薄，所以接著在襯墊層130上方布置保護層131以在後續蝕刻程序期間保護襯墊層。保護層可以是氮化物，諸如氮化矽(SiN)或類似者。保護層可透過諸如ALD或類似程序來塗敷。對於本特定例示性具體實施例，襯墊層是SiN。
請參閱第4圖，接著舉例如藉由RIE或類似者來非等向性蝕刻高k介電性襯墊層130及相關聯之保護層131。該非等向性蝕刻程序使閘極金屬120在虛設閘極108和主動閘極112之頂端處曝露。保護層131防止襯墊層130在此程序期間遭受破壞或腐蝕。襯墊層130之其餘部分形成用於覆蓋體132之外襯墊134(看第5圖最清楚)，其將完全在後續步驟中形成。
請參閱第5圖，接著藉由諸如化學氣相沉積(CVD)、物理氣相沉積(PVD)、ALD或類似手段在襯墊層130 上方布置核心層。該核心層大體上亦為一種介電質，具有與襯墊層130之第一材料組成不同的第二材料組成。核心層典型為由氮化物所組成，諸如SiN、SiBCN或類似者。
對於本特定例示性具體實施例，核心層是SiN，其是與保護層131相同的材料。如此，在這項具體實施例中，沉積核心層之前，不需要先移除保護層。
接著，將核心層與襯墊層130向下平坦化(諸如藉由化學機械平坦化(CMP)來達成)，以使ILD 124之頂端表面曝露，並且完成在虛設閘極108和主動閘極112上方形成覆蓋體132。覆蓋體132包括圍繞內核136布置之高k介電性外襯墊134。如前述，外襯墊134是自襯墊層130經平坦化之後留下的部分所形成。內核136是自核心層經平坦化之後留下的部分所形成。
請參閱第6圖，TS溝槽(圖未示)是藉由眾所周知的程序，諸如藉由非等向性乾蝕刻程序，將ILD層124從半導體結構100之主動區106中的虛設閘極108和主動閘極112之間移除所形成。舉例而言，可利用TS遮罩藉由習知的微影程序，接著進行電漿乾蝕刻，來圖型化TS溝槽。電漿蝕刻本質上屬於自對準，其中此蝕刻程序僅移除氧化物ILD層124，並且對氮化物閘極蓋體132及間隔物122具有選擇性。接著，在TS溝槽內形成TS層138。
TS層138取代ILD層124布置於虛設閘極108和主動閘極112之相對側上及源極/汲極區110上方。TS層138可藉由TS金屬化程序來布置。TS金屬化程序可包 括在源極/汲極區110上方形成底端矽化物層，接著沉積頂端傳導金屬層。底端矽化物層可由Ni、Ti、NiPt矽化物或類似者所組成。傳導金屬層可由TiN、TaN及諸如W、Co或Ru之主體傳導材料所組成。
將TS層138之任何過量填充向下平坦化至第一層階126，其現為鰭片104之頂端表面上面的覆蓋體132之頂端的層階(或高度)(內核136及/或高k襯墊134)。TS層138跨佈整個主動區106縱向延展，以便確保即使是在最壞情況的錯準條件下，仍與鰭片104之陣列中之源極/汲極區110有適當電接觸。
請參閱第7圖，接著使TS層138凹陷至高於虛設閘極108和主動閘極112之第二層階128且低於內核136之第一層階126的第三層階140。此凹陷可藉由TS層138之定時非等向性蝕刻來達成，諸如藉由反應性離子蝕刻(RIE)或類似者來達成。
要注意的重點是，相較於在Rx區中形成CB接觸部之先前技術方法，TS層138之此種凹陷屬於淺式。在那些先前技術方法中，TS層妥適地凹陷至低於虛設閘極108和主動閘極112之第二層階128。在本具體實施例中，TS層138的凹陷範圍典型為15nm至30nm，其典型為原始TS層高度的約百分之25至50。然而，在Rx區中形成CB接觸部之先前技術方法是使TS層凹陷到盡可能合理的程度，不會過度增加TS層的整體電阻。因此，先前技術方法使TS層妥適凹陷至低於TS層原始高度的百分之50， 且低於虛設閘極108和主動閘極112之第二層階128。
請參閱第8圖，氧化物填充層142布置於半導體結構100上方。氧化物填充層142將用於後續圖型化CB溝槽(看第12A圖最清楚)及CA溝槽(看第9C圖最清楚)。
請參閱第9A、9B及9C圖，在氧化物填充層142內圖型化一對CA溝槽144(看第9C圖最清楚)，用以在其底下曝露TS層138。在此程序流程之後面，可金屬化CA溝槽以形成電連接至TS層138之一對CA接觸部160(看第13B圖最清楚)。CA溝槽144可如藉由RIE程序或類似者來非等向性蝕刻。截面圖9B展示同樣將對尚待形成CB溝槽146進行圖型化並金屬化以形成CB接觸部162處的位置(看第13A圖最清楚)。
為求清楚，第9A圖之俯視平面圖展示半導體結構100下鋪於氧化物填充層142的特徵，其中氧化物填充層142是以假想線邊界來表示。另外，俯視平面圖9A中展示CB溝槽146之虛線周界，而且其表示將在後續程序步驟中布置於氧化物填充層142內之CB溝槽146的目標位置。
要注意的重點是，CA溝槽144與CB溝槽146必須順著平行於主動閘極112之方向相隔充分距離148而置，用以實質防止CB接觸部162與CA接觸部160之間出現電氣短路(看第13B圖最清楚)。距離148必須顧及因無法避免之製造變異所致的最壞情況錯準允差，並且仍然能 夠防止出現此短路。距離148典型為在15nm至30nm或更大的範圍內，端視Rx區的整體寬度而定。
請參閱第10A及10B圖，接著在半導體結構100上方布置有機平坦化層150。接著藉由諸如RIE蝕刻或類似程序，將CB溝槽146圖型化並蝕刻到有機平坦化層150內。雖然本具體實施例之程序流程展示CA溝槽之後才形成CB溝槽146，但所屬技術領域中具有通常知識者仍將認知的是，該程序流程中可先形成CB溝槽。
請參閱第11A及11B圖，在氧化物填充層142內進一步圖型化並蝕刻CB溝槽146，以在CB溝槽146之中間部分152處使覆蓋體132之頂端表面曝露。此蝕刻程序再次地，可以是RIE程序。
中間部分152的目標是要著落於該覆蓋體之內核136直接位在閘極金屬120上面的至少一部分上。如後續步驟中將更詳細論述者，這是因為將會自中間部分152起，進一步將CB溝槽146向下蝕刻至溝槽底端156(看第12A圖最清楚)以使閘極金屬120曝露。
然而，由於微影及其它製造允差的關係，CB溝槽146之中間部分152可著落於覆蓋體132之其它部分上，包括內核136未直接安放於閘極金屬120或閘極高k介電性襯墊134上方的部分。在最壞情況的製造允差下，中間部分152甚至可部分延展到氧化物填充層142內約覆蓋體132之第一層階126處，如這項特定具體實施例中所示。此外，使中間部分152在覆蓋體132之頂端表面上著 落，甚至可將頂端表面向下蝕刻到稍微低於第一層階126約二至五nm處。
要注意的是，覆蓋體132向上延展至第一層階126，此為高於TS層138之第三層階140的距離154，亦實質為中間部分152高於TS層138的距離。此距離154預定為中間部分152離任何TS層138之充分垂直距離，用以實質防止該中間部分上所布置之任何金屬與主動區106內之任何TS層之間出現電氣短路。
距離154必須顧及因無法避免之製造變異所致的最壞情況錯準及其它允差，並且仍然能夠防止出現此短路。距離154典型為在10nm至30nm的範圍內。
請參閱第12A及12B圖，接著在本具體實施例中，相對於襯墊134選擇性非等向性蝕刻內核136，以使CB溝槽146進一步延展至溝槽底端156，並且使閘極金屬120曝露。該非等向性蝕刻可藉由RIE程序或類似者來完成。
高k介電性襯墊134之第一材料組成、內核136之第二材料組成與氧化物填充層142之第三材料組成之間的差異使第一核心材料在非等向性蝕刻程序(諸如RIE)中相對於襯墊及氧化物填充層之第二及第三材料非常具有選擇性。因此，可將內核136向下蝕刻以使閘極金屬120曝露而不會蝕刻高k介電性襯墊134或氧化物填充層142。
這很重要，因為在此實施例中，要防止布置 於CB溝槽146之任何CB接觸部162(看第13A圖最清楚)與TS層138之間出現短路，需要高k介電性襯墊134。即使襯墊134典型只有3nm至6nm厚，但其高k材料組成仍提供足以防止CB接觸部162與TS層138之間出現短路的電氣絕緣。另外，未遭受蝕刻之襯墊134作用在於使CB接觸部162與閘極金屬120自對準。
請參閱第13A及13B圖，有機平坦化層150舉例如藉由濕蝕刻程序或類似者來剥除。接著，舉例如藉由CVD、PVD、無電式金屬鍍覆或類似者將CA溝槽144及CB溝槽146金屬化，以形成位在CA溝槽144中的CA接觸部160、及位在CB溝槽146中的CB接觸部162。CB接觸部162電連接至閘極金屬120，而CA接觸部160電連接至TS層138。
在本程序流程之最後階段，完成之半導體結構100此時包括布置於主動區106中之FinFET 116。FinFET 116包括布置於一對源極/汲極區110之間的通道118、及布置於通道118上方之主動閘極112。主動閘極112包括布置於閘極間隔物122之間的閘極金屬120。覆蓋體132布置於主動閘極112上方。該覆蓋體包括圍繞覆蓋體內核136布置之高k介電性外襯墊134。在源極/汲極區110上方主動閘極112之相對側上布置溝槽矽化物(TS)層138。TS層138具有高於主動閘極112之第二層階128且低於覆蓋體132之第一層階126的第三層階140。在半導體結構100上方布置氧化物填充層142。氧化物填充層142內及主動 區106上方布置CB溝槽146。CB溝槽146向下延展至實質位於覆蓋體132之第一層階126處之溝槽中間部分152，並且自中間部分152進一步延展至溝槽底端156。該溝槽底端包括閘極金屬120。CB接觸部162布置於CB溝槽146內並且電連接至該閘極金屬120。
另外，半導體結構100此時包括用於FinFET 116之該對源極/汲極(CA)接觸部160，其亦布置於氧化物填充層142內。該等CA接觸部電連接至TS層138，其套疊FinFET 116之源極/汲極區110。CA接觸部160順著平行於主動閘極112之方向位於離CB接觸部162充分距離148處(看第9A圖最清楚)，用以實質防止CB接觸部162與CA接觸部160之間出現電氣短路。
此外，半導體結構100之主動區106更包括垂直於主動閘極112延展之複數個鰭片104(看第1A圖最清楚)。複數個FinFET 116布置於鰭片104中。各FinFET 116包括布置於一對源極/汲極區110之間的通道118，其中主動閘極112布置於各FinFET 116之通道118上方，而TS層138布置於各FinFET 116之源極/汲極區110上方的主動閘極112之相對側上。
有助益的是，CA接觸部160與CB接觸部162都布置於半導體結構100之主動區106內，並且離任何TS層138充分距離且彼此相離，用以實質防止出現電氣短路。CA接觸部160與CB接觸部162之形式及間隔顧及因無法避免之製造變異所致的最壞情況錯準及其它允差，用 以防止出現此短路。因此，半導體結構100可輕易製造，並且可比例縮小至10nm技術節點及更先進的技術節點。
雖然已參照特定具體實施例說明本發明，應了解的是，仍可在所述發明概念之精神與範疇內施作許多變更。因此，本發明之用意不在於限制所述具體實施例，而是要具有以下申請專利範圍內容所界定的完全範疇。

Claims (20)

  1. 一種製造半導體裝置之方法，該方法包含：提供在主動區中布置有FinFET之結構，該FinFET包括布置於一對源極/汲極區之間的通道、及布置於該通道上方之閘極，該閘極包括布置於閘極間隔物之間的閘極金屬；在該閘極上方形成覆蓋體，該覆蓋體具有圍繞內核布置之高k介電性外襯墊；在該源極/汲極區上方的該閘極之相對側上形成溝槽矽化物層；使該溝槽矽化物層凹陷至高於該閘極之層階且低於該覆蓋體之層階的層階；在該結構上方布置氧化物層；在該氧化物層內圖型化閘極溝槽，以使該核心與襯墊在該閘極溝槽之中間部分處曝露，該閘極溝槽位於該主動區內；相對於該襯墊選擇性蝕刻該核心，以使該閘極溝槽進一步延展至溝槽底端，並且使該閘極金屬曝露；以及金屬化該閘極溝槽以形成電連接至該閘極金屬之閘極接觸部。
  2. 如申請專利範圍第1項所述之方法，其中，該覆蓋體外襯墊具有高k介電性的第一材料組成，並且該覆蓋體內核具有與該第一材料組成不同的第二材料組成。
  3. 如申請專利範圍第2項所述之方法，其中，該第一材料 是HfO2。
  4. 如申請專利範圍第2項所述之方法，其中，該第二材料是SiN、SiBCN及SiCO的其中一者。
  5. 如申請專利範圍第1項所述之方法，其中，該閘極溝槽之該中間部分位於離任何溝槽矽化物層充分距離處，用以實質防止該主動區內該閘極接觸部與該溝槽矽化物層之間出現電氣短路。
  6. 如申請專利範圍第1項所述之方法，包含使該溝槽矽化物層凹陷至該核心之該層階之25%至50%之範圍內的層階。
  7. 如申請專利範圍第1項所述之方法，包含使該溝槽矽化物層凹陷至該核心之該層階下面15nm至30nm之範圍內。
  8. 如申請專利範圍第1項所述之方法，包含在氧化物層內就該FinFET布置一對源極/汲極接觸部，該源極/汲極接觸部電連接至將該FinFET之該源極/汲極區套疊之該溝槽矽化物層，該源極/汲極接觸部順著平行於該閘極之方向位於離該閘極接觸部充分距離處，用以實質防止該閘極接觸部與該源極/汲極接觸部之間出現電氣短路。
  9. 如申請專利範圍第8項所述之方法，包含：在該氧化物層內圖型化一對源極/汲極溝槽，以使該溝槽矽化物層在該FinFET之該源極/汲極區上方曝露；以及 金屬化該源極/汲極溝槽，以形成電連接至該溝槽矽化物層之該源極/汲極接觸部。
  10. 如申請專利範圍第1項所述之方法，包含：形成該覆蓋體前先在該閘極之間布置介電層；使該介電層之層階下面之該閘極凹陷至該閘極層階；在該結構上方布置襯墊層，該襯墊層具有高k介電性的第一材料組成；在該襯墊層上方布置核心層，該核心層具有與該第一材料組成不同的第二材料組成；將該核心層與襯墊層向下研磨至該介電層之該層階，以形成該覆蓋體之該襯墊與核心；移除該介電層，以形成溝槽矽化物溝槽；以及在該溝槽矽化物溝槽內形成該溝槽矽化物層。
  11. 一種半導體結構，包含：FinFET，布置於主動區中，該FinFET包括布置於一對源極/汲極區之間的通道、及布置於該通道上方之閘極，該閘極包括布置於閘極間隔物之間的閘極金屬；覆蓋體，包括圍繞內核布置之高k介電性外襯墊，該覆蓋體布置於該閘極上方，該覆蓋體襯墊與核心自該閘極向上延展至實質相同第一覆蓋體層階；布置於該等源極/汲極區上方該閘極之對置側上的溝槽矽化物層，該等溝槽矽化物層具有高於該閘極之層階且低於該覆蓋體層階的層階； 布置於該結構上方之氧化物層；布置於該氧化物層內及該主動區上方之閘極溝槽，該閘極溝槽向下延展至實質位於該覆蓋體層階處之溝槽中間部分，並且自該中間部分進一步延展至溝槽底端，該溝槽底端包括該閘極金屬；以及布置於該閘極溝槽內並且電連接至該閘極金屬之閘極接觸部。
  12. 如申請專利範圍第11項所述之半導體結構，其中，該覆蓋體外襯墊具有高k介電性的第一材料組成，並且該覆蓋體內核具有與該第一材料組成不同的第二材料組成。
  13. 如申請專利範圍第12項所述之半導體結構，其中，該第一材料是HfO2。
  14. 如申請專利範圍第12項所述之半導體結構，其中，該第二材料是SiN、SiBCN及SiCO的其中一者。
  15. 如申請專利範圍第11項所述之半導體結構，其中，該閘極溝槽之該中間部分位於離任何溝槽矽化物層充分距離處，用以實質防止該主動區內該閘極接觸部與該溝槽矽化物層之間出現電氣短路。
  16. 如申請專利範圍第11項所述之半導體結構，包含該溝槽矽化物層，所具層階在該覆蓋體層階之25%至50%之範圍內。
  17. 如申請專利範圍第11項所述之半導體結構，包含該溝槽矽化物層，所具層階在該覆蓋體層階下面15nm至 30nm之範圍內。
  18. 如申請專利範圍第11項所述之半導體結構，包含供該FinFET布置於氧化物層內之一對源極/汲極接觸部，該源極/汲極接觸部電連接至將該FinFET之該源極/汲極區套疊之該溝槽矽化物層，該源極/汲極接觸部順著平行於該閘極之方向位於離該閘極接觸部充分距離處，用以實質防止該閘極接觸部與該源極/汲極接觸部之間出現電氣短路。
  19. 如申請專利範圍第11項所述之半導體結構，其中，該閘極溝槽自該閘極溝槽之該中間部分向下延展至該溝槽底端之區段具有面積與該核心之橫向截面實質相等的截面。
  20. 如申請專利範圍第11項所述之半導體結構，更包含：該主動區，包括垂直於該閘極而延展之複數個鰭片；複數個FinFET，布置於該鰭片中，各FinFET包括布置於一對源極/汲極區之間的通道，其中，該閘極布置於各FinFET之該通道上方；以及該溝槽矽化物層，布置於各FinFET之該源極/汲極區上方的該閘極之相對側上。
TW106106416A 2016-07-06 2017-02-24 用於放置在具有高ｋ介電閘極覆蓋體之半導體主動區內之閘極接觸的方法及設備 TWI649836B (zh)

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