TW201818475A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW201818475A
TW201818475A TW105137190A TW105137190A TW201818475A TW 201818475 A TW201818475 A TW 201818475A TW 105137190 A TW105137190 A TW 105137190A TW 105137190 A TW105137190 A TW 105137190A TW 201818475 A TW201818475 A TW 201818475A
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fin
semiconductor
dopant source
layer
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TW105137190A
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TWI704622B (zh
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劉恩銓
童宇誠
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聯華電子股份有限公司
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Priority to TW105137190A priority Critical patent/TWI704622B/zh
Priority to US15/378,050 priority patent/US9837417B1/en
Priority to US15/802,472 priority patent/US10121790B2/en
Publication of TW201818475A publication Critical patent/TW201818475A/zh
Priority to US16/149,125 priority patent/US10777556B2/en
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Publication of TWI704622B publication Critical patent/TWI704622B/zh

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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Abstract

一種半導體元件，包括一半導體基底，具有一第一區域及一第二區域；複數個第一半導體鰭狀結構，位於該第一區域；複數個第二半導體鰭狀結構，位於該第二區域；一第一固態摻質來源層，設於該半導體基底的該第一區域；一第一絕緣緩衝層設於該第一固態摻質來源層上；一第二固態摻質來源層，設於該半導體基底的該第二區域；一第二絕緣緩衝層設於該第二固態摻質來源層上及該第一絕緣緩衝層上；一第一鰭凸塊，設於該第一區域；以及一第二鰭凸塊，設於該第二區域。

Description

半導體元件及其製作方法
本發明揭露一種半導體元件及其製作方法，尤指一種利用固態摻質(solid state doping, SSD)技術於鰭狀結構下半部形成摻雜層的半導體元件及其製作方法。
近年來，隨著關鍵元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。
由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。
再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行的鰭狀場效電晶體元件製程中，鰭狀結構的設計仍存在許多瓶頸，進而影響整個元件的漏電流及整體電性表現。因此如何改良現有鰭狀場效電晶體製程即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先提供一半導體基底，具有一第一區域及一第二區域。再分別於該第一區域及該第二區域內形成複數個第一半導體鰭狀結構及複數個第二半導體鰭狀結構。再於該半導體基底上的該第一區域內形成一第一固態摻質來源層。於該第一固態摻質來源層上形成一第一絕緣緩衝層。
接著，於該半導體基底上的該第二區域內形成一第二固態摻質來源層。再於該第一固態摻質來源層及該第二固態摻質來源層上形成一第二絕緣緩衝層。然後，於該第一區域內的該複數個第一半導體鰭狀結構之間形成一第一鰭凸塊，並於該第二區域內的該複數個第二半導體鰭狀結構之間形成一第二鰭凸塊。
該第一鰭凸塊包含一第一側壁子，該第二鰭凸塊包含一第二側壁子，該第二側壁子與該第一側壁子的結構不同。
其中該第一側壁子不覆蓋該第一鰭凸塊的一上表面，且該第二側壁子不覆蓋該第二鰭凸塊的一上表面。
本發明另一實施例揭露一種半導體元件，包括一半導體基底，具有一第一區域及一第二區域；複數個第一半導體鰭狀結構，位於該第一區域；複數個第二半導體鰭狀結構，位於該第二區域；一第一固態摻質來源層，設於該半導體基底的該第一區域；一第一絕緣緩衝層設於該第一固態摻質來源層上；一第二固態摻質來源層，設於該半導體基底的該第二區域；一第二絕緣緩衝層設於該第二固態摻質來源層上及該第一絕緣緩衝層上；一第一鰭凸塊，設於該第一區域；以及一第二鰭凸塊，設於該第二區域。
該第一鰭凸塊包含一第一側壁子，該第二鰭凸塊包含一第二側壁子，該第二側壁子與該第一側壁子的結構不同。
其中該第一側壁子不覆蓋該第一鰭凸塊的一上表面，且該第二側壁子不覆蓋該第二鰭凸塊的一上表面。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在本發明的以下詳細描述中，所參考的圖式亦構成說明書的一部分，其例示出可具體實踐本發明的實施例。這些實施例已描述足夠的細節以使本領域的技術人員能夠實踐本發明。其它實施例可以被利用，並且可以做出結構，邏輯和電性上的變化而不脫離本發明的範圍。下面的詳細說明，因此，不被視為具有限制意義，並且本發明的範圍是由所附申請專利範圍而定。
在進一步的描述優選實施例之前，以下先針對全文中使用的特定用語進行說明。
用語“蝕刻”在本文中通常用來描述圖案化材料的製程，使得在蝕刻完成後的材料的至少一部分能被留下。例如，應該理解的是，蝕刻矽的方法通常包括在矽上面圖案化一光阻層，然後從不被光阻層保護的區域去除矽。因此，在蝕刻過程完成，由光阻保護的區域的矽會留下。然而，在另一實例中，刻蝕也可以指不使用光阻的方法，但在蝕刻過程完成後仍留下至少一部分的材料。
上面的說明用來從區分“刻蝕”及“去除”。當“蝕刻”一材料，該材料的至少一部分在處理結束後被保留。與此相反，“去除”材料時，基本上未被保護或遮蓋的所有材料層是在過程中除去。然而，在一些實施例中，“去除”被認為是一個廣義的用語，可以包括刻蝕。
全文中所描述的“基底”、“半導體基底”或“晶圓”，最常見的應該是矽基底或矽晶圓。然而，“基底”或“晶圓”也可以是指任何半導體材料，例如鍺、砷化鎵、磷化銦等。在其它實施例的，“基底”或“晶圓”可以是不導電的，例如玻璃或藍寶石晶圓。
請參閱第1圖至第9圖，其為依據本發明一實施例所繪示的一種製造半導體元件的方法剖面示意圖。如第1圖所示，首先提供一半導體基底10，具有一第一區域101及一第二區域102。例如，第一區域101可以是NMOS區域，而第二區域102可以是PMOS區域。第一區域101及第二區域102彼此不重疊。接著，分別於第一區域101及第二區域102內形成複數個第一半導體鰭狀結構11及複數個第二半導體鰭狀結構12。
在半導體基底10上定義形成半導體鰭狀結構的做法乃週知技藝，可以包括微影及蝕刻等步驟，其細節不另贅述。
根據本發明一實施例，各第一半導體鰭狀結構11頂部可以具有一遮罩層112，各第一半導體鰭狀結構12頂部可以具有一遮罩層122，其中遮罩層112、122可以包含氮化矽或氧化矽，但不限於此。此外，在各第一半導體鰭狀結構11及各第一半導體鰭狀結構12上分別可以選擇形成有一氧化層114及一氧化層124。氧化層114、124可以包含氧化矽，例如，臨場蒸氣產生(in-situ steam generation，ISSG)氧化層，但不限於此。
如第2圖所示，接著於半導體基底10上形成一第一固態摻質來源層21，例如，以化學氣相沉積法形成。第一固態摻質來源層21係順形的沉積在半導體基底10上。根據本發明一實施例，第一固態摻質來源層21可以包含一硼矽玻璃(BSG)層，但不限於此。再於第一固態摻質來源層21上形成一第一絕緣緩衝層22，其中第一絕緣緩衝層22可以包含氮化矽，但不限於此。第一絕緣緩衝層22可以化學氣相沉積法形成。
如第3圖所示，接著以一蝕刻遮罩30，例如光阻，遮蓋住第一區域101，顯露出第二區域102。然後，進行一蝕刻製程，將未被蝕刻遮罩30遮蔽的第一固態摻質來源層21及第一絕緣緩衝層22從第二區域102去除，以顯露出第二區域102內的複數個第二半導體鰭狀結構12。隨後，去除蝕刻遮罩30。
如第4圖所示，接著於半導體基底10上的第一區域101及第二區域102上全面沉積第二固態摻質來源層41，例如，以化學氣相沉積法形成。第二固態摻質來源層41係順形的沉積在半導體基底10上。根據本發明一實施例，第二固態摻質來源層41可以包含一磷矽玻璃(PSG)層或一砷矽玻璃(AsSG)層，但不限於此。
如第5圖所示，接著，以另一蝕刻遮罩50，例如光阻，遮蓋住第二區域102，顯露出第一區域101。然後，進行一蝕刻製程，將未被蝕刻遮罩50遮蔽的第二固態摻質來源層41從第一區域102去除，以顯露出第一區域101內的第一絕緣緩衝層22。隨後，去除蝕刻遮罩50。
如第6圖所示，於第一區域101內的第一絕緣緩衝層22及第二區域102內的第二固態摻質來源層41上形成一第二絕緣緩衝層42，其中第二絕緣緩衝層42可以包含氮化矽，但不限於此。第二絕緣緩衝層42可以化學氣相沉積法形成。
接著，如第7圖所示，於半導體基底10上形成一蝕刻遮罩60，例如光阻，遮蓋住第一區域101及第二區域102。蝕刻遮罩60具有開口60a及60b，其中開口60a僅顯露出第一區域101內的部分第一半導體鰭狀結構11，開口60b僅顯露出第二區域102內的部分第二半導體鰭狀結構12。
接著，進行一非等向性乾蝕刻製程，經由開口60a及60b蝕刻顯露出來的第一半導體鰭狀結構11及第二半導體鰭狀結構12，如此於第一區域101內的複數個第一半導體鰭狀結構11之間形成一第一鰭凸塊201，並於第二區域102內的複數個第二半導體鰭狀結構12之間形成一第二鰭凸塊202，其中第一鰭凸塊201包含一第一側壁子201a，第二鰭凸塊202包含一第二側壁子202a，第二側壁子202a與第一側壁子201a的結構不同。
根據本發明一實施例，第一側壁子201a包含部分的氧化層114、部分的第一固態摻質來源層21、部分的第一絕緣緩衝層22及部分的第二絕緣緩衝層42。第二側壁子202a包含部分的氧化層124、部分的第二固態摻質來源層41及部分的第二絕緣緩衝層42。
其中，第一側壁子201a不覆蓋第一鰭凸塊201的一上表面，且第二側壁子202a不覆蓋第二鰭凸塊202的一上表面。從第7圖中可看出，此時所述第一鰭凸塊201的上表面是一裸露的矽表面，其與第一側壁子201a之間形成一下凹區域201b，所述第二鰭凸塊202的上表面是一裸露的矽表面，其與第一側壁子202a之間形成一下凹區域202b。之後，去除蝕刻遮罩60。
根據本發明一實施例，在形成第一鰭凸塊201與第二鰭凸塊202時，會另在第一鰭凸塊201與第二鰭凸塊202旁邊的半導體基底10上，分別形成下凹區域211及下凹區域212。
如第8圖所示，接著於第二絕緣緩衝層42、第一鰭凸塊201及第二鰭凸塊202上形成一介電層70，例如，矽氧層。根據本發明一實施例，介電層70可以利用化學氣相沉積形成，但不限於此。根據本發明一實施例，介電層70亦填入第一鰭凸塊201的下凹區域201b、第二鰭凸塊202的下凹區域202b、第一鰭凸塊201旁的下凹區域211，及第二鰭凸塊202旁的下凹區域212。接著，可以選擇進行一平坦化製程。
然後，蝕刻介電層70、第二絕緣緩衝層42、第一絕緣緩衝層22、第一固態摻質來源層21及第二固態摻質來源層41、氧化層114、氧化層124，至一低於第一半導體鰭狀結構11及第二半導體鰭狀結構12上表面的水平，以顯露各第一半導體鰭狀結構11及各第二半導體鰭狀結構112高於其下鰭區域11b及12b的突出部分11a及12a。
根據本發明一實施例，遮罩層112、114也可以選擇在此蝕刻步驟中被去除，但不限於此。
之後，可以進行一熱趨入製程，將摻質從剩餘的第一固態摻質來源層21及第二固態摻質來源層41分別趨入各第一半導體鰭狀結構11及各第二半導體鰭狀結構12的下鰭區域11b及12b，如此分別在各第一半導體鰭狀結構11及各第二半導體鰭狀結構12的下鰭區域11b及12b形成摻雜區311及312。
如第9圖所示，接著於介電層70上形成一閘極80，跨越各第一半導體鰭狀結構11及各第二半導體鰭狀結構12的突出部分11a及12a。根據本發明一實施例，閘極80可以包含金屬閘極。再於閘極80各側的各第一半導體鰭狀結構11及各第二半導體鰭狀結構12的突出部分11a及12a中形成源極及汲極摻雜區(圖未示)，隨後，可選擇進行磊晶製程，於源極及汲極摻雜區形成SiGe或SiP磊晶。
根據本發明一實施例，另包含將閘極80切斷成閘極區段80a、80b、80c、80d的步驟。其中各閘極區段80a、80b、80c、80d包含一閘極邊緣801、802、803、804，當從上往下看時，閘極邊緣801、802、803、804與第一鰭凸塊201或第二鰭凸塊202部分重疊。當從上往下看時，閘極邊緣801、802、803、804不會完全重疊第一鰭凸塊201或第二鰭凸塊202。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體基底
11‧‧‧第一半導體鰭狀結構
11a‧‧‧突出部分
11b‧‧‧下鰭區域
12‧‧‧第二半導體鰭狀結構
12a‧‧‧突出部分
12b‧‧‧下鰭區域
21‧‧‧第一固態摻質來源層
22‧‧‧第一絕緣緩衝層
30‧‧‧蝕刻遮罩
41‧‧‧第二固態摻質來源層
42‧‧‧第二絕緣緩衝層
50‧‧‧蝕刻遮罩
60‧‧‧蝕刻遮罩
60a‧‧‧開口
60b‧‧‧開口
70‧‧‧介電層
80‧‧‧閘極
80a~80d‧‧‧閘極區段
101‧‧‧第一區域
102‧‧‧第二區域
112‧‧‧遮罩層
114‧‧‧氧化層
122‧‧‧遮罩層
124‧‧‧氧化層
201‧‧‧第一鰭凸塊
201a‧‧‧第一側壁子
201b‧‧‧下凹區域
202‧‧‧第二鰭凸塊
202a‧‧‧第二側壁子
202b‧‧‧下凹區域
211‧‧‧下凹區域
212‧‧‧下凹區域
311‧‧‧摻雜區
312‧‧‧摻雜區
801~804‧‧‧閘極邊緣
第1圖至第9圖為依據本發明一實施例所繪示的一種製造半導體元件的方法剖面示意圖。

Claims (20)

  1. 一種製造半導體元件的方法，包含： 提供一半導體基底，具有一第一區域及一第二區域； 分別於該第一區域及該第二區域內形成複數個第一半導體鰭狀結構及複數個第二半導體鰭狀結構； 於該半導體基底上的該第一區域內形成一第一固態摻質來源層； 於該第一固態摻質來源層上形成一第一絕緣緩衝層； 於該半導體基底上的該第二區域內形成一第二固態摻質來源層； 於該第一固態摻質來源層及該第二固態摻質來源層上形成一第二絕緣緩衝層；以及 於該第一區域內的該複數個第一半導體鰭狀結構之間形成一第一鰭凸塊，並於該第二區域內的該複數個第二半導體鰭狀結構之間形成一第二鰭凸塊，其中該第一鰭凸塊包含一第一側壁子，該第二鰭凸塊包含一第二側壁子，該第二側壁子與該第一側壁子的結構不同，其中該第一側壁子不覆蓋該第一鰭凸塊的一上表面，且該第二側壁子不覆蓋該第二鰭凸塊的一上表面。
  2. 如申請專利範圍第1項所述的製造半導體元件的方法，其中於該半導體基底上的該第二區域內形成該第二固態摻質來源層之前，另包含： 遮蓋住該第一區域；以及 從該第二區域去除該第一固態摻質來源層及該第一絕緣緩衝層，以顯露出該第二區域內的該複數個第二半導體鰭狀結構。
  3. 如申請專利範圍第1項所述的製造半導體元件的方法，其中所述於該半導體基底上的該第二區域內形成一第二固態摻質來源層包含： 於該半導體基底上的該第一區域及該第二區域上全面沉積該第二固態摻質來源層； 遮蓋住該第二區域；以及 從該第一區域去除該第二固態摻質來源層，以顯露出該第一區域內的該第一絕緣緩衝層。
  4. 如申請專利範圍第1項所述的製造半導體元件的方法，其中另包含： 於該第二絕緣緩衝層、該第一鰭凸塊及該第二鰭凸塊上形成一介電層； 蝕刻該介電層、該第二絕緣緩衝層、該第一固態摻質來源層及該第二固態摻質來源層，至一低於該複數個第一半導體鰭狀結構及該複數個第二半導體鰭狀結構上表面的水平，以顯露各該複數個第一半導體鰭狀結構及各該複數個第二半導體鰭狀結構高於其下鰭區域的突出部分；以及 將摻質從該第一固態摻質來源層及該第二固態摻質來源層趨入各該複數個第一半導體鰭狀結構及各該複數個第二半導體鰭狀結構的該下鰭區域。
  5. 如申請專利範圍第4項所述的製造半導體元件的方法，其中另包含： 形成一閘極，跨越各該複數個第一半導體鰭狀結構及各該複數個第二半導體鰭狀結構的該突出部分； 於該閘極各側的各該複數個第一半導體鰭狀結構及各該複數個第二半導體鰭狀結構的該突出部分中形成源極及汲極摻雜區；以及 將該閘極切斷成閘極區段。
  6. 如申請專利範圍第5項所述的製造半導體元件的方法，其中各該閘極區段包含一閘極邊緣，當從上往下看時，該閘極邊緣與該第一鰭凸塊或該第二鰭凸塊部分重疊。
  7. 如申請專利範圍第6項所述的製造半導體元件的方法，其中當從上往下看時，該閘極邊緣不會完全重疊該第一鰭凸塊或該第二鰭凸塊。
  8. 如申請專利範圍第1項所述的製造半導體元件的方法，其中該第一固態摻質來源層包含一硼矽玻璃(BSG)層。
  9. 如申請專利範圍第1項所述的製造半導體元件的方法，其中該第二固態摻質來源層包含一磷矽玻璃(PSG)層或一砷矽玻璃(AsSG)層。
  10. 如申請專利範圍第1項所述的製造半導體元件的方法，其中該第一絕緣緩衝層包含氮化矽。
  11. 如申請專利範圍第1項所述的製造半導體元件的方法，其中該第二絕緣緩衝層包含氮化矽。
  12. 如申請專利範圍第1項所述的製造半導體元件的方法，其中該第一側壁子包含部分的該第一固態摻質來源層、部分的該第一絕緣緩衝層及部分的該第二絕緣緩衝層。
  13. 如申請專利範圍第1項所述的製造半導體元件的方法，其中該第二側壁子包含部分的該第二固態摻質來源層及部分的該第二絕緣緩衝層。
  14. 一種半導體元件，包含： 一半導體基底，具有一第一區域及一第二區域； 複數個第一半導體鰭狀結構，位於該第一區域； 複數個第二半導體鰭狀結構，位於該第二區域； 一第一固態摻質來源層，設於該半導體基底的該第一區域； 一第一絕緣緩衝層設於該第一固態摻質來源層上； 一第二固態摻質來源層，設於該半導體基底的該第二區域； 一第二絕緣緩衝層設於該第二固態摻質來源層上及該第一絕緣緩衝層上； 一第一鰭凸塊，設於該第一區域；以及 一第二鰭凸塊，設於該第二區域，該第一鰭凸塊包含一第一側壁子，該第二鰭凸塊包含一第二側壁子，該第二側壁子與該第一側壁子的結構不同，其中該第一側壁子不覆蓋該第一鰭凸塊的一上表面，且該第二側壁子不覆蓋該第二鰭凸塊的一上表面。
  15. 如申請專利範圍第14項所述的半導體元件，其中該第一固態摻質來源層包含一硼矽玻璃(BSG)層。
  16. 如申請專利範圍第14項所述的半導體元件，其中該第二固態摻質來源層包含一磷矽玻璃(PSG)層或一砷矽玻璃(AsSG)層。
  17. 如申請專利範圍第14項所述的半導體元件，其中該第一絕緣緩衝層包含氮化矽。
  18. 如申請專利範圍第14項所述的半導體元件，其中該第二絕緣緩衝層包含氮化矽。
  19. 如申請專利範圍第14項所述的半導體元件，其中該第一側壁子包含部分的該第一固態摻質來源層、部分的該第一絕緣緩衝層及部分的該第二絕緣緩衝層。
  20. 如申請專利範圍第14項所述的半導體元件，其中該第二側壁子包含部分的該第二固態摻質來源層及部分的該第二絕緣緩衝層。
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