TW201828478A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
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- 238000005530 etching Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
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- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 239000007772 electrode material Substances 0.000 description 1
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Abstract
本發明提供一種減小尺寸且不損失有效通道區域的半導體裝置及其製造方法。所述半導體裝置包括:基板;汲極區域,設置於基板的背面側;基底層,自汲極區域起設置於基板表面間;溝槽,自基板表面起到達汲極區域;閘極絕緣膜,覆蓋自溝槽的底面起至第一高度為止的溝槽內側;閘極電極,介隔閘極絕緣膜埋入至溝槽內直至與閘極絕緣膜高度相同;絕緣膜,埋入至溝槽內直至比第一高度高的第二高度;源極電極,埋入至溝槽內的剩餘的部分;基底接觸區域,以自基板的表面起低於第二高度而設置且單側面與源極電極相接;源極區域,上表面與基底接觸區域的底面的一部分相接,單側面與溝槽的側面相接且一部分與源極電極相接;以及基板的背面上的汲極電極。
Description
本發明是有關於一種半導體裝置及其製造方法,尤其是有關於一種具有具備溝槽閘極的縱型金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)的半導體裝置及其製造方法。
作為先前的縱型MOSFET之一,例如如專利文獻1所示般提出了如下構成者:僅在形成於基板上的溝槽內的下部設置閘極電極,將使源極電極與閘極電極絕緣的層間絕緣膜埋入至溝槽內上部,且以其上表面與基板表面幾乎成為同一平面的方式形成,於所述平面上形成源極電極。藉此,不需要如下情況下所需要的、用以將形成於層間絕緣膜上的源極電極與基板表面的源極區域及基底接觸區域連接的接觸開口,可實現裝置於橫方向上的尺寸縮小,所述情況是將閘極電極埋入至溝槽上部,且於基板表面上形成層間絕緣膜。
進而,於專利文獻1(尤其參照圖4、圖5)中揭示了藉由沿著條紋狀的溝槽於基板表面交替配置源極區域與基底接觸區域,可縮小鄰接的溝槽的間隔,且亦進一步減小裝置的尺寸。 [現有技術文獻] [專利文獻]
[專利文獻1]日本專利第5118270號說明書
[發明所欲解決之課題]然而,於專利文獻1等的先前的縱型MOSFET中,為了連接源極電極與源極區域及基底接觸區域,需要於基板表面在橫方向上並排設置源極區域與基底接觸區域。因此,源極區域與基底接觸區域鑒於步驟偏差的影響而需要於橫方向上具有某種程度的餘裕而進行配置。因此,進一步的裝置尺寸的縮小困難。
另外,進而於專利文獻1中揭示的沿著條紋狀的溝槽而於基板表面交替配置源極區域與基底接觸區域的結構中,需要犧牲通道形成所需要的源極區域而於基板表面形成基底接觸區域,於形成基底接觸區域的區域中未形成通道,因此通道密度變低。
因此,本發明的目的在於提供一種具有減小尺寸且抑制通道密度的下降的縱型MOSFET的半導體裝置及其製造方法。 [解決課題之手段]
本發明的半導體裝置的特徵在於包括:基板;第一導電型的汲極區域,自所述基板的背面起具有規定的厚度且設置於所述基板上;溝槽,自所述基板的表面起到達所述汲極區域的上表面;第二導電型的基底層,與所述溝槽鄰接且設置於所述汲極區域上;閘極絕緣膜,覆蓋所述溝槽的內側的底面及側面,且上端部自所述溝槽的底面起位於第一高度;閘極電極,介隔所述閘極絕緣膜埋入至所述溝槽內直至所述第一高度;第一絕緣膜,埋入至所述溝槽內的所述閘極絕緣膜及所述閘極電極上直至比所述第一高度高的第二高度;源極電極,埋入至所述溝槽內的所述第一絕緣膜上的剩餘部分;第二導電型的基底接觸區域,具有自所述基板的表面起直至高於所述第二高度且低於所述溝槽的上部的第三高度為止的深度,其中一個側面與所述源極電極相接而設置,且所述第二導電型的基底接觸區域的濃度高於所述基底層;第二導電型的源極區域,其是以如下方式設置,即上表面與所述基底接觸區域的底面的一部分相接,其中一個側面與所述溝槽的外側面相接且所述其中一個側面的至少一部分與所述源極電極相接,沿著自底面起至所述汲極區域為止的所述溝槽的外側面的所述基底層成為通道區域;以及汲極電極,於所述基板的背面上與所述汲極區域相接而設置。
另外,本發明的半導體裝置的製造方法的特徵在於包括:自第一導電型的基板表面起以少於基板的厚度的深度來形成第二導電型的基底層,並使所述基板的剩餘區域作為第一導電型的汲極區域而殘存的步驟;以自所述基板表面起到達所述汲極區域的方式形成溝槽的步驟;於所述溝槽的內側的底面及側面形成閘極絕緣膜的步驟;於所述溝槽內介隔所述閘極絕緣膜而埋入閘極電極的步驟;對所述閘極電極進行蝕刻直至所述閘極電極的上表面的位置自所述溝槽的底面變為第一高度的步驟;自所述溝槽的內側注入雜質,而形成與溝槽的外側面的一部分相接且至少具備自所述基板表面起至所述第一高度為止的深度的源極區域的步驟;對所述閘極絕緣膜的上部進行蝕刻直至所述閘極絕緣膜的上端部成為所述第一高度的步驟;於所述溝槽內的所述閘極絕緣膜及所述閘極電極上形成第一絕緣膜直至比所述第一高度高的第二高度的步驟;形成第二導電型的基底接觸區域的步驟,所述第二導電型的基底接觸區域具有自所述基板的表面起直至高於所述第二高度且低於所述溝槽的上部的第三高度為止的深度,且所述溝槽的所述外側面的另一部分與所述基底層及所述源極區域的上部相接,並且所述第二導電型的基底接觸區域的濃度高於所述基底層;以及於所述溝槽內的所述第一絕緣膜上的剩餘部分,埋入與所述源極區域及所述基底接觸區域相接的源極電極的步驟。
再者,所述「基底層」、「基底接觸區域」有時亦分別被稱為「主體(body)區域」、「主體接觸區域」等,但於本說明書中稱為「基底層」、「基底接觸區域」。 [發明的效果]
根據本發明,設為如下構成,因此不需要如先前般於基板表面在橫方向上並排設置源極區域與基底接觸區域,相應地可減小橫方向(水平方向)的裝置的尺寸,所述構成是於溝槽的側面中在縱方向上並排設置源極區域與基底接觸區域,並使埋入至溝槽中的源極電極與源極區域及基底接觸區域接觸。另外,不需要為了形成基底接觸區域而犧牲通道形成所需要的源極區域,而不會損失有效通道區域,因此可防止通道密度的下降。
以下,參照圖式來對本發明的實施形態進行詳細說明。
圖1是用以對本發明的第一實施形態的縱型MOSFET的半導體裝置100進行說明的剖面圖。
第一實施形態的半導體裝置100如圖1所示包括高濃度地注入了N型雜質的高濃度半導體基板10、以及設置於高濃度半導體基板10上的磊晶層15。再者,以下,亦將高濃度半導體基板10與磊晶層15合併稱為基板16。
於基板16內設置有汲極區域17、P型的基底層12以及溝槽20,所述汲極區域17包含N型高濃度半導體基板10與設置於N型高濃度半導體基板10上的N型半導體層11,所述P型的基底層12設置於汲極區域17上,所述溝槽20自基板16(磊晶層15)的表面貫穿基底層12並到達汲極區域17的上表面。
於溝槽20的內部形成有閘極絕緣膜21、閘極電極22、層間絕緣膜23及源極電極33,所述閘極絕緣膜21覆蓋溝槽20的底面及自底面起至第一高度H1為止的側面,所述閘極電極22介隔閘極絕緣膜21而埋入至第一高度H1,所述層間絕緣膜23位於閘極絕緣膜21及閘極電極22的上部,埋入至高於第一高度H1的第二高度H2,所述源極電極33填充溝槽20的剩餘部分。如此,閘極電極22與源極電極33藉由層間絕緣膜23在溝槽20內部絕緣。
於基板16的表面的除了溝槽20以外的區域設置有基底接觸區域14,所述基底接觸區域14具有直至高於第二高度H2且低於基板16表面的第三高度H3為止的深度且高濃度地注入了P型的雜質。
於基底接觸區域14的下面設置有源極區域13,所述源極區域13與溝槽20的側面相接,沿著溝槽20側面具有自第三高度H3起至至少第一高度H1為止的深度,且高濃度地注入了N型雜質。藉此,沿著自源極區域13的底面起至汲極區域17上表面為止的溝槽20的外側面的基底層12成為通道區域。
如此,根據第一實施形態,藉由設為使源極區域13與基底接觸區域14沿著溝槽20的外側面在縱方向上排列的構成,可於溝槽20側面處使源極區域13及基底接觸區域14與源極電極33接觸。因此,無須於基板16的上表面中使源極區域13及基底接觸區域14與源極電極33接觸,因此可實現半導體裝置100的橫方向(水平方向)的尺寸的縮小。
再者,源極電極33如上所述埋入至溝槽20的剩餘部分且亦設置於基板16表面的整個面。另外,於基板16的背面整個面、即汲極區域17的底面整個面設置有汲極電極32。
此處,圖2中示出了第一實施形態的半導體裝置100的平面結構的例子。圖2(a)表示第一例的平面結構100a,圖2(b)表示第二例的平面結構100b。再者,於圖2(a)、圖2(b)的任一者中源極電極33均被省略。
關於第一例的平面結構100a,如圖2(a)所示,溝槽20形成為條紋狀,沿著溝槽20的各側面源極區域13亦形成為條紋狀。另外,基底接觸區域14亦於源極區域13上沿著溝槽20的各側面,於除了溝槽20以外的基板16的整個表面形成為條紋狀。
關於第二例的平面結構100b,如圖2(b)所示,溝槽20形成為格子狀。而且,於由溝槽20包圍的各區域中,沿著溝槽20的側面源極區域13形成為四方環狀。另外,基底接觸區域14於由溝槽20包圍的各區域中於環狀的源極區域13上沿著溝槽20的側面且形成於除了溝槽20以外的基板16的整個表面上。
如此,溝槽20的平面結構可為條紋狀、格子狀中的任一種。於任一種的情況下,均可在橫方向(水平方向)上縮小半導體裝置100的尺寸,源極區域13形成於沿著溝槽20的側面的整個區域,因此通道區域不會減少,可提高通道密度。
其次,使用圖3至圖11所示的步驟剖面圖來對圖1所示的第一實施形態的半導體裝置100的製造方法進行說明。
如圖3所示,於高濃度地摻雜有N型雜質的高濃度半導體基板10上藉由磊晶成長而形成摻雜了N型雜質的磊晶層15。藉此,形成有基板16。
而且,藉由自磊晶層15(基板16)的表面摻雜P型的雜質,如圖4所示,形成P型的基底層12,並且於基底層12的下面殘存N型磊晶層15而形成N型半導體層11,藉此形成包含N型高濃度半導體基板10與N型半導體基板11的N型的汲極區域17。
其次,如圖5所示,於利用化學氣相沈積(Chemical Vapor Deposition,CVD)法等於基板16表面形成絕緣膜24後,利用光微影術形成使作為溝槽20(參照圖1)的部分開口的光阻劑的圖案(未圖示)。繼而,將所述抗蝕劑圖案作為遮罩而對絕緣膜24進行圖案化,於作為溝槽20的部分形成開口。
其次,藉由將絕緣膜24作為遮罩而對基底層12進行蝕刻,如圖6所示,於形成貫穿基底層12而到達汲極區域17的溝槽20後,將絕緣膜24去除。
其後,如圖7所示,於包含溝槽20的底面及側面的整個面形成閘極絕緣膜21。所述閘極絕緣膜21除了對基底層12及汲極區域17的上表面進行熱氧化而形成以外,亦可藉由CVD法等形成介電體。
繼而,於利用閘極電極材料將溝槽20填埋至上部後,如圖8所示,藉由進行蝕刻至第一高度H1,而形成閘極電極22。
其次,如圖8所示,形成在溝槽20的上部具有開口的光阻劑40的圖案,將該圖案作為遮罩並向溝槽20的內側面對N型的雜質進行傾斜離子注入,藉此沿著溝槽20的側面形成源極區域13。此時,源極區域13的下部與作為閘極電極22的上表面的第一高度H1同等或稍靠下地形成,因此源極區域13與閘極電極22的重疊亦以自動對準的方式得到保證。
於光阻劑40去除後,如圖9所示,將閘極絕緣膜21的形成於閘極電極22上方的部分去除後,利用絕緣膜對溝槽20內進行填埋,進行蝕刻直至低於基板16表面且高於第一高度H1的第三高度H3,藉此形成層間絕緣膜23。
其後,如圖10所示,將層間絕緣膜23作為源極區域13的遮罩,對P型的雜質全面地進行離子注入,藉此形成具有自基板16表面起至第三高度H3為止的深度的基底接觸區域14。再者,此時的離子注入的傾斜度並不限定於特定的角度。
其後,如圖11所示,再次對層間絕緣膜23進行蝕刻直至高於第一高度H1且低於第三高度H3的第二高度H2為止的深度。層間絕緣膜23具有為了使閘極電極22與源極電極33(參照圖1)絕緣而所需的厚度。
最後,藉由於溝槽20內及基板16的整個表面形成源極電極33,並使源極電極33與源極區域13及基底接觸區域14接觸,進而於基板16的整個背面形成汲極電極32,可獲得圖1所示的第一實施形態的半導體裝置100。
圖12為用以對本發明的第二實施形態的具有縱型MOSFET的半導體裝置200進行說明的剖面圖。再者,對於與圖1所示的第一實施形態的半導體裝置100相同的構成要素標注同一符號並適當省略重覆的說明。
第二實施形態的半導體裝置200在設置有基底接觸區域142
來代替基底接觸區域14的方面、以及於除了溝槽20以外的基板16的表面上設置有絕緣膜242
的方面和第一實施形態的半導體裝置100不同。
即,相對於半導體裝置100中的基底接觸區域14沿著溝槽20的各側面而設置於除了溝槽20以外的基板16(基底層)的整個表面,半導體裝置200中的基底接觸區域142
設置於除了溝槽20以外的基板16的表面中沿著溝槽20的側面的源極區域13的上部,於基板16的剩餘的表面上基底層12露出。因此,基底接觸區域142
成為如下結構:其中一個側面在溝槽20的側面處與源極電極33相接,另一個側面與基底層12相接。
根據本實施形態,由於基底接觸區域142
與基底層12在側面相接,因此即便於鄰接的溝槽20間的間隔變窄的情況下,亦可確實地使基底層12與源極電極33接觸。
此處,圖13(a)、圖13(b)中示出了第二實施形態的半導體裝置200的平面結構的例子。圖13(a)表示第一例的平面結構200a,圖13(b)表示第二例的平面結構200b。再者,於圖13(a)、圖13(b)中的任一者中源極電極33及絕緣膜242
均被省略。
關於該些平面結構,亦與第一實施形態的半導體裝置100大致相同,因此以不同的方面為中心進行說明。
關於第一例的平面結構200a,如圖13(a)所示,沿著形成為條紋狀的溝槽20的各側面源極區域13亦形成為條紋狀。進而,基底接觸區域142
亦於源極區域13上具有與源極區域13大致相同的寬度且沿著溝槽20的各側面形成為條紋狀。因此,成為如下構成:於鄰接的溝槽20間的基底接觸區域142
間的基板16表面基底層12露出。
關於第二例的平面結構200b,如圖13(b)所示,於由形成為格子狀的溝槽20包圍的各區域中,沿著溝槽20的側面源極區域13形成為四方環狀。進而,基底接觸區域142
亦於源極區域13上具有與源極區域13大致相同的寬度且沿著溝槽20的各側面形成為四方環狀。因此,成為如下構成:於由溝槽20包圍的各區域的中央部的基板16表面基底層12露出。
如此,於第二實施形態的半導體裝置200中,溝槽20的平面結構亦可為條紋狀、格子狀中的任一種。於任一種的情況下,均可獲得與所述第一實施形態的半導體裝置100相同的效果。
其次,使用圖14至圖17所示的步驟剖面圖來對圖12所示的第二實施形態的半導體裝置200的製造方法進行說明。
與第一實施形態同樣地,於經過圖3至圖5的步驟後,如圖14般在使絕緣膜24作為絕緣膜242
殘存的狀態下於溝槽的底面及側面形成閘極絕緣膜21。
其後,如圖15般藉由利用導電性材料、例如多晶矽將溝槽20填埋至第一高度H1而形成閘極電極22,將絕緣膜242
作為遮罩,並向溝槽20的內側面對雜質進行傾斜離子注入,而形成具有沿著溝槽側面至少直至第一高度H1為止的深度的源極區域13。如此,絕緣膜242
成為離子注入的遮罩,因此相對於第一實施形態而言,可去掉利用光微影術而形成遮罩圖案的步驟。
繼而,如圖16般利用絕緣膜對溝槽20內進行填埋,並進行蝕刻直至比第一高度H1高的第二高度H2,藉此形成層間絕緣膜23。
其次,如圖17般藉由於殘留絕緣膜242
的狀態下向溝槽側面對雜質進行傾斜離子注入,而形成基底接觸區域142
,所述基底接觸區域142
具有直至低於基板16表面且高於第二高度H2的第三高度H3為止的深度,且其中一側面與溝槽20側面相接,另一側面與基底層12相接。此時,藉由存在絕緣膜242
,可防止雜質被注入至源極區域13中。即,絕緣膜242
作為源極區域13的遮罩發揮功能。如此,藉由形成基底接觸區域142
,根據本實施形態,無須如第一實施形態般對層間絕緣膜23進行兩次蝕刻,且亦不存在將絕緣膜242
去除的步驟,因此與第一實施形態相比,可減少步驟。
以上,對本發明的實施形態進行了說明,但本發明並不限定於所述實施形態,當然可在不脫離本發明的主旨的範圍內進行各種變更。
例如,於在所述實施形態中說明的半導體裝置的構成中,亦可使P型與N型的構成要素的導電型完全相反。
另外,於圖2(b)及圖13(b)中,作為本發明的實施形態的半導體裝置的平面結構,示出了由溝槽20包圍的各區域為四邊形的例子,但所述區域並不限於四邊形,亦可為將四邊形的角切除所得的八邊形或圓形等。
10‧‧‧高濃度半導體基板
11‧‧‧半導體層/半導體基板
12‧‧‧基底層
13‧‧‧源極區域
14、142‧‧‧基底接觸區域
15‧‧‧磊晶層
16‧‧‧基板
17‧‧‧汲極區域
20‧‧‧溝槽
21‧‧‧閘極氧化膜
22‧‧‧閘極電極
23‧‧‧層間絕緣膜
24、242‧‧‧絕緣膜
32‧‧‧汲極電極
33‧‧‧源極電極
40‧‧‧光阻劑
100、200‧‧‧半導體裝置
100a、100b、200a、200b‧‧‧平面結構
H1‧‧‧第一高度
H2‧‧‧第二高度
H3‧‧‧第三高度
圖1為表示本發明的第一實施形態的半導體裝置的結構的剖面圖。 圖2(a)、圖2(b)為表示本發明的第一實施形態的半導體裝置的平面結構的圖,圖2(a)表示第一例的平面結構,圖2(b)表示第二例的平面結構。 圖3為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖4為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖5為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖6為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖7為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖8為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖9為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖10為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖11為表示本發明的第一實施形態的半導體裝置的製造步驟的剖面圖。 圖12為表示本發明的第二實施形態的半導體裝置的結構的剖面圖。 圖13(a)、圖13(b)為表示本發明的第二實施形態的半導體裝置的平面結構的圖,圖13(a)表示第一例的平面結構,圖13(b)表示第二例的平面結構。 圖14為表示本發明的第二實施形態的半導體裝置的製造步驟的剖面圖。 圖15為表示本發明的第二實施形態的半導體裝置的製造步驟的剖面圖。 圖16為表示本發明的第二實施形態的半導體裝置的製造步驟的剖面圖。 圖17為表示本發明的第二實施形態的半導體裝置的製造步驟的剖面圖。
Claims (10)
- 一種半導體裝置,其特徵在於包括: 基板; 第一導電型的汲極區域,自所述基板的背面起具有規定的厚度且設置於所述基板上; 溝槽,自所述基板的表面起到達所述汲極區域的上表面; 第二導電型的基底層,與所述溝槽鄰接且設置於所述汲極區域上; 閘極絕緣膜,覆蓋所述溝槽的內側的底面及側面,且上端部自所述溝槽的底面起位於第一高度; 閘極電極,介隔所述閘極絕緣膜埋入至所述溝槽內直至所述第一高度; 第一絕緣膜,埋入至所述溝槽內的所述閘極絕緣膜及所述閘極電極上直至比所述第一高度高的第二高度; 源極電極,埋入至所述溝槽內的所述第一絕緣膜上的剩餘部分; 第二導電型的基底接觸區域,具有自所述基板的表面起直至高於所述第二高度且低於所述溝槽的上部的第三高度為止的深度,其中一個側面與所述源極電極相接而設置,且所述第二導電型的基底接觸區域的濃度高於所述基底層; 第二導電型的源極區域,其是以如下方式設置,即上表面與所述基底接觸區域的底面的一部分相接,其中一個側面與所述溝槽的外側面相接且所述其中一個側面的至少一部分與所述源極電極相接,沿著自底面起至所述汲極區域為止的所述溝槽的外側面的所述基底層成為通道區域;以及 汲極電極,於所述基板的背面上與所述汲極區域相接而設置。
- 如申請專利範圍第1項所述的半導體裝置,其中所述基底接觸區域的底面的一部分與所述基底層相接。
- 如申請專利範圍第1項所述的半導體裝置,其中所述基底接觸區域的另一個側面與所述基底層相接。
- 如申請專利範圍第1項至第3項中任一項所述的半導體裝置,其進而包括第二絕緣膜,所述第二絕緣膜設置於所述基底接觸區域上且具有與所述溝槽的上部連接的開口,所述源極電極亦埋入至所述開口內。
- 如申請專利範圍第1項所述的半導體裝置,其中所述溝槽於規定的方向上延伸。
- 如申請專利範圍第1項所述的半導體裝置,其中所述溝槽包圍所述基底層的周圍。
- 一種半導體裝置的製造方法,其特徵在於包括: 自第一導電型的基板表面起以少於基板的厚度的深度來形成第二導電型的基底層,並使所述基板的剩餘區域作為第一導電型的汲極區域而殘存的步驟; 以自所述基板表面起到達所述汲極區域的方式形成溝槽的步驟; 於所述溝槽的內側的底面及側面形成閘極絕緣膜的步驟; 於所述溝槽內介隔所述閘極絕緣膜而埋入閘極電極的步驟; 對所述閘極電極進行蝕刻直至所述閘極電極的上表面的位置自所述溝槽的底面變為第一高度的步驟; 自所述溝槽的內側注入雜質,而形成與溝槽的外側面的一部分相接且至少具備自所述基板表面起至所述第一高度為止的深度的源極區域的步驟; 對所述閘極絕緣膜的上部進行蝕刻直至所述閘極絕緣膜的上端部成為所述第一高度的步驟; 於所述溝槽內的所述閘極絕緣膜及所述閘極電極上形成第一絕緣膜直至比所述第一高度高的第二高度的步驟; 形成第二導電型的基底接觸區域的步驟,所述第二導電型的基底接觸區域具有自所述基板的表面起直至高於所述第二高度且低於所述溝槽的上部的第三高度為止的深度,且所述溝槽的所述外側面的另一部分與所述基底層及所述源極區域的上部相接,並且所述第二導電型的基底接觸區域的濃度高於所述基底層;以及 於所述溝槽內的所述第一絕緣膜上的剩餘部分,埋入與所述源極區域及所述基底接觸區域相接的源極電極的步驟。
- 如申請專利範圍第7項所述的半導體裝置的製造方法,其中所述形成源極區域的步驟是藉由向所述溝槽內側面對雜質進行傾斜離子注入而進行。
- 如申請專利範圍第7項或第8項所述的半導體裝置的製造方法,其中所述形成第一絕緣膜的步驟與形成基底接觸區域的步驟包括:將所述第一絕緣膜形成至所述第三高度為止的步驟;將所述第一絕緣膜作為遮罩並進行離子注入而形成所述基底接觸區域的步驟;以及其後將所述第一絕緣膜蝕刻至所述第二高度為止的步驟。
- 如申請專利範圍第7項所述的半導體裝置的製造方法,其中所述形成溝槽的步驟包括形成第二絕緣膜的步驟,所述第二絕緣膜於在所述基板表面上形成有所述溝槽的部分具有開口, 所述形成基底接觸區域的步驟包括將所述第二絕緣膜作為遮罩而向溝槽內側面對雜質進行傾斜離子注入的步驟。
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US10770396B2 (en) | 2018-12-28 | 2020-09-08 | Vanguard International Semiconductor Corporation | Semiconductor structure and method for fabricating the same |
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