CN108987362B - 内连线结构、其制造方法与半导体结构 - Google Patents
内连线结构、其制造方法与半导体结构 Download PDFInfo
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Abstract
本发明提供一种内连线结构、其制造方法与半导体结构,其中内连线结构包括导体层、间隙壁、介电层与接触窗。导体层设置在基底上。间隙壁设置在导体层的侧壁上。介电层覆盖导体层与间隙壁。接触窗设置在介电层中且位于导体层上。上述内连线结构、其制造方法与半导体结构可在不增加元件尺寸的情况下,有效地提升重叠裕度。
Description
技术领域
本发明涉及一种内连线结构、其制造方法与半导体结构,尤其涉及一种具有较佳制程裕度的内连线结构、其制造方法与半导体结构。
背景技术
在目前存储器元件的制程中,会通过增加存储单元区中的电容结构的高度来增加电容值。然而,在电容结构的高度变高的情况下,将使得周边电路区中的接触窗的制程面临相当大的挑战。
详细而言,由于电容结构的高度变高,接触窗开口的深度也随着变深。为了确保接触窗开口能够充分暴露出下方的导体层,因此会增加蚀刻时间,来对介电层进行过蚀刻。
如此一来,在形成接触窗开口的蚀刻制程中,当接触窗开口与导体层发生重叠偏差(overlay shift)时,接触窗开口的位置会超出导体层的范围,因此上述过蚀刻制程会蚀刻到邻近于导体层的介电层,而对接触窗开口下方的电路元件造成伤害,进而使得半导体元件的可靠度降低。
目前业界用来解决上述重叠偏差的方法主要是加大导体层的尺寸或是在电路设计上禁止(forbidden)在邻近于导电层的位置下方设置电路元件。然而,不论是采用上述何种方法,均会使得晶片尺寸变大。
发明内容
本发明提供一种内连线结构、其制造方法与半导体结构,其可在不增加元件尺寸的情况下,有效地提升重叠裕度(overlay window)。
本发明提出一种内连线结构,包括导体层、间隙壁、介电层与接触窗。导体层设置在基底上。间隙壁设置在导体层的侧壁上。介电层覆盖导体层与间隙壁。接触窗设置在介电层中且位于导体层上。
本发明提出一种半导体结构,包括半导体元件与上述内连线结构。内连线结构与半导体元件电性连接。
本发明提出一种内连线结构的制造方法,包括以下步骤。提供基底。在基底上形成导体层。在导体层的侧壁上形成间隙壁。形成覆盖导体层与间隙壁的介电层。在介电层中形成接触窗。接触窗位于导体层上。
基于上述,在本发明所提出的内连线结构及其制造方法中,由于间隙壁位于导体层的侧壁上,因此可在不增加元件尺寸的情况下,有效地提升重叠裕度。如此一来,在形成接触窗开口的蚀刻制程中,即使接触窗开口与导体层发生重叠偏差,接触窗开口的位置仍会落在间隙壁与导体层的范围内,因此不会对接触窗开口下方的电路元件造成伤害,进而可提升半导体元件的可靠度。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1A至图1E为本发明一实施例的内连线结构的制造流程剖面图。
图2为本发明另一实施例的内连线结构的剖面图。
图3A至图3B为本发明另一实施例的内连线结构的制造流程剖面图。
图4为本发明另一实施例的内连线结构的剖面图。
附图标记说明
100:基底
102、112:介电层
104、114:接触窗
106:导体层
108:间隙壁材料层
108a:间隙壁
110:金属硅化物层
116:接触窗开口
118、118a、218、218a:内连线结构
120:凹陷
200:半导体元件
202:栅极
204:栅介电层
206:间隙壁
208a、208b:掺杂区
210:轻掺杂区
W1:宽度
具体实施方式
图1A至图1E为本发明一实施例的内连线结构的制造流程剖面图。
请参照图1A,提供基底100。在基底100上可形成有半导体元件200、介电层102与接触窗104。在此实施例中,半导体元件200是以金氧半晶体管(MOS transistor)为例来进行说明,但本发明并不以此为限。
半导体元件200包括栅极202、栅介电层204、间隙壁206、掺杂区208a、掺杂区208b与轻掺杂区210。栅极202设置于基底100上。栅介电层204设置于栅极202与基底100之间。间隙壁206设置于栅极202的侧壁上。掺杂区208a与掺杂区208b设置于栅极202两侧的基底100中。掺杂区208a与掺杂区208b分别可用以作为源极或漏极。轻掺杂区210设置于间隙壁206下方的基底100中。
介电层102覆盖半导体元件200。介电层102的材料例如是氧化硅。介电层102的形成方法例如是化学气相沉积法。
接触窗104设置于介电层102中且位于掺杂区208a上,藉此接触窗104可电性连接至掺杂区208a。接触窗104的材料例如是钨。接触窗104的形成方法例如是金属镶嵌法。
请参照图1B,在基底100上形成导体层106。在此实施例中,导体层106是以形成在基底100上方的介电层102上为例来进行说明,但本发明并不以此为限。此外,导体层106可电性连接至接触窗104。藉此,导体层106可经由接触窗104而电性连接至半导体元件200的电极(掺杂区208a),如金氧半晶体管的源极或漏极。
导体层106的材料例如是钨。导体层106的形成方法例如是先在介电层102上形成导体材料层(未示出),再对导体材料层进行图案化制程。
在导体层106上形成共形的间隙壁材料层108。间隙壁材料层108的材料例如是氮化硅或多晶硅。多晶硅例如是掺杂多晶硅或未掺杂多晶硅。间隙壁材料层108的形成方法例如是化学气相沉积法或原子层沉积法(atomic layer deposition,ALD)。
请参照图1C,对间隙壁材料层108进行回蚀刻制程,而在导体层106的侧壁上形成间隙壁108a。间隙壁108a的宽度W1例如是5nm至15nm。回蚀刻制程例如是干蚀刻制程,如反应性离子蚀刻(Reactive Ion Etching,RIE)制程。
间隙壁108a可有效地提升导体层106与后续形成于导体层106上的接触窗114(图1E)之间的重叠裕度。此外,当导体层106与接触窗114产生重叠偏差时,部分接触窗114会位于间隙壁108a上。在间隙壁108a的材料为多晶硅(特别是阻值较低的掺杂多晶硅)的情况下,间隙壁108a与接触窗114的接触部分可提供额外的导电面积,因此可降低接触窗114的底部接触电阻。
请参照图1D,在间隙壁108a的材料为多晶硅的情况下,可选择性地在间隙壁108a上形成金属硅化物层110。由于金属硅化物层110具有较低的阻值,因此可更进一步地降低接触窗114(图1E)的底部接触电阻。金属硅化物层110的材料例如是硅化钛、硅化钴或硅化镍。金属硅化物层110的形成方法例如是进行自对准金属硅化物制程。
请参照图1E,形成覆盖导体层106与间隙壁108a的介电层112。介电层112的材料例如是氧化硅。介电层112的形成方法例如是化学气相沉积法。
在介电层112中形成接触窗114。接触窗114位于导体层106上,藉此接触窗114可电性连接至导体层106。接触窗114的材料例如是钨。接触窗114的形成方法例如是金属镶嵌法。详细来说,接触窗114的形成方法可先于介电层112中形成接触窗开口116,接着形成填满接触窗开口116的接触窗材料层(未示出),再移除接触窗开口116以外的接触窗材料层。接触窗材料层的形成方法例如是物理气相沉积法。接触窗开口116以外的接触窗材料层的移除方法例如是化学机械研磨法。
以下,通过图1E来说明上述实施例的内连线结构118。
请参照图1E,内连线结构118包括导体层106、间隙壁108a、介电层112与接触窗114。导体层106设置在基底100上。间隙壁108a设置在导体层106的侧壁上。介电层112覆盖导体层106与间隙壁108a。接触窗114设置在介电层112中且位于导体层106上。此外,在间隙壁108a的材料为多晶硅的情况下,内连线结构118还可包括金属硅化物层110。金属硅化物层110设置在间隙壁108a上。此外,内连线结构118的各构件的材料、特性、形成方法与配置方式已于上述实施例中进行详尽地说明,于此不再重复说明。
在此实施例中,内连线结构118是以包括金属硅化物层110为例来进行说明。然而,在其他实施例中,内连线结构118也可不包括金属硅化物层110。
此外,内连线结构118可应用半导体结构中。举例来说,半导体结构可包括半导体元件200与内连线结构118,内连线结构118与半导体元件200电性连接。详细来说,内连线结构118中的导体层106可经由接触窗104而电性连接至半导体元件200的电极(掺杂区208a),如金氧半晶体管的源极或漏极。
图2为本发明另一实施例的内连线结构的剖面图。
请同时参照图1E与图2,图2的内连线结构118a与图1E的内连线结构118的差异如下。图2的内连线结构118a可不包括图1E的内连线结构118中的金属硅化物层110。也即,在形成图2的内连线结构118a的制程中,可不在间隙壁108a上形成金属硅化物层110。此外,图2的内连线结构118a与图1E的内连线结构118中相似的构件使用相同符号表示,于此不再重复说明。
基于上述实施例可知,在上述内连线结构118、118a及其制造方法中,由于间隙壁108a位于导体层106的侧壁上,因此可在不增加元件尺寸的情况下,有效地提升重叠裕度。如此一来,在形成接触窗开口116的蚀刻制程中,即使接触窗开口116与导体层106发生重叠偏差,接触窗开口116的位置仍会落在间隙壁108a与导体层106的范围内,因此不会对接触窗开口116下方的电路元件造成伤害,进而可提升半导体元件的可靠度。
图3A至图3B为本发明另一实施例的内连线结构的制造流程剖面图。图3A为接续图1C的内连线结构的制造流程剖面图。
请参照图3A,在对间隙壁材料层108进行回蚀刻制程,而在导体层106的侧壁上形成间隙壁108a之后,对间隙壁108a进行过蚀刻制程,使得间隙壁108a的顶面低于导体层106的顶面,而在间隙壁108a与导体层106之间形成凹陷120。过蚀刻制程例如是干蚀刻制程,如反应性离子蚀刻制程。
请参照图3B,在间隙壁108a的材料为多晶硅的情况下,可选择性地在间隙壁108a上形成金属硅化物层110。形成覆盖导体层106与间隙壁108a的介电层112。在介电层112中形成接触窗114。接触窗114位于导体层106上,藉此接触窗114可电性连接至导体层106。金属硅化物层110、介电层112与接触窗114的形成方法可参考图1D至图1E中的说明,于此不再重复说明。
以下,通过图3B来说明上述实施例的内连线结构218。
请同时参照图1E与图3B,图1E的内连线结构118与图3B的内连线结构218的差异如下。在图3B的内连线结构218中,间隙壁108a的顶面低于导体层106的顶面,而在间隙壁108a与导体层106之间形成凹陷120。此外,图3B的内连线结构218与图1E的内连线结构118中的相似构件以相同符号表示并省略其说明。
在此实施例中,内连线结构218是以包括金属硅化物层110为例来进行说明。然而,在其他实施例中,内连线结构218也可不包括金属硅化物层110。
图4为本发明另一实施例的内连线结构的剖面图。
请同时参照图3B与图4,图4的内连线结构218a与图3B的内连线结构218的差异如下。图4的内连线结构218a可不包括图3B的内连线结构218中的金属硅化物层110。也即,在形成图4的内连线结构218a的制程中,可不在间隙壁108a上形成金属硅化物层110。此外,图4的内连线结构218a与图3B的内连线结构218中相似的构件使用相同符号表示,于此不再重复说明。
基于上述实施例可知,在内连线结构218、218a中,由于凹陷120可暴露出部分导体层106的侧壁,因此当导体层106与接触窗114产生重叠偏差时,接触窗114会与导体层106的侧壁接触,藉此可增加导体层106与接触窗114的接触面积,而可进一步性降低接触窗114的底部接触电阻。
综上所述,在上述实施例所提出的内连线结构及其制造方法中,由于间隙壁位于导体层的侧壁上,因此可在不增加元件尺寸的情况下,有效地提升重叠裕度。如此一来,在形成接触窗开口的蚀刻制程中,即使接触窗开口与导体层发生重叠偏差,接触窗开口的位置仍会落在间隙壁与导体层的范围内,因此不会对接触窗开口下方的电路元件造成伤害,进而可提升半导体元件的可靠度。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视权利要求所界定者为准。
Claims (12)
1.一种内连线结构,其特征在于,包括:
第一介电层,设置在基底上;
第一接触窗,垂直贯穿所述第一介电层;
导体层,设置在所述基底上,其中所述第一接触窗连接至所述导体层的底面;
间隙壁,横向环绕所述导体层,且所述间隙壁沿着所述导体 层的侧壁从所述第一介电层的顶面朝所述导体 层的顶面垂直延伸,其中所述间隙壁直接接触所述第一介电层的所述顶面;
第二介电层,覆盖所述导体层与所述间隙壁,且所述第二介电层直接接触所述导体 层的所述顶面;以及
第二接触窗,设置在所述第二介电层中且位于所述导体层上,其中所述第二接触窗的底部连接至所述导体层的所述顶面,所述第一接触窗与所述第二接触窗彼此分离,且所述第二接触窗的部分所述底部重叠于所述间隙壁。
2.根据权利要求1所述的内连线结构,其特征在于,所述第一接触窗与所述第二接触窗电性连接至所述导体层。
3.根据权利要求1所述的内连线结构,其特征在于,所述间隙壁的宽度为5nm至15nm。
4.根据权利要求1所述的内连线结构,其特征在于,所述间隙壁的顶面低于所述导体层的顶面,而在所述间隙壁与所述导体层之间形成凹陷。
5.根据权利要求1所述的内连线结构,其特征在于,所述间隙壁的材料包括氮化硅或多晶硅,且所述多晶硅包括掺杂多晶硅或未掺杂多晶硅。
6.根据权利要求5所述的内连线结构,其特征在于,在所述间隙壁的材料为所述多晶硅的情况下,所述内连线结构还包括:
金属硅化物层,设置在所述间隙壁上。
7.一种半导体结构,其特征在于,包括半导体元件与根据权利要求1所述的内连线结构,其中所述内连线结构与所述半导体元件电性连接。
8.根据权利要求7所述的半导体结构,其特征在于,所述内连线结构的所述导体层电性连接至半导体元件的电极,且所述电极包括金氧半晶体管的源极或漏极。
9.一种内连线结构的制造方法,其特征在于,包括:
提供基底;
在所述基底上形成第一介电层;
在所述第一介电层中形成第一接触窗;
在所述基底上形成导体层,其中所述第一接触窗连接至所述导体层的底面;
在所述导体层的侧壁上形成间隙壁,其中所述间隙壁横向环绕所述导体层,所述间隙壁沿着所述导体 层的所述侧壁从所述第一介电层的顶面朝所述导体 层的顶面垂直延伸,且所述间隙壁直接接触所述第一介电层的所述顶面;
形成覆盖所述导体层与所述间隙壁的第二介电层,其中所述第二介电层直接接触所述导体 层的所述顶面;以及
在所述第二介电层中形成第二接触窗,其中所述第二接触窗位于所述导体层上,所述第二接触窗的底部连接至所述导体层的所述顶面,所述第一接触窗与所述第二接触窗彼此分离,且所述第二接触窗的部分所述底部重叠于所述间隙壁。
10.根据权利要求9所述的内连线结构的制造方法,其特征在于,所述间隙壁的形成方法包括:
在所述导体层上形成共形的间隙壁材料层;以及
对所述间隙壁材料层进行回蚀刻制程。
11.根据权利要求10所述的内连线结构的制造方法,其特征在于,还包括对所述间隙壁材料层进行所述回蚀刻制程之后,对所述间隙壁进行过蚀刻制程,使得所述间隙壁的顶面低于所述导体层的顶面,而在所述间隙壁与所述导体层之间形成凹陷。
12.根据权利要求9所述的内连线结构的制造方法,其特征在于,还包括在所述间隙壁的材料为多晶硅的情况下,在所述间隙壁上形成金属硅化物层。
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