JP2012253148A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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Abstract
【解決手段】本実施形態の半導体装置は、半導体基板10を覆う第1の層間絶縁膜上に設けられる配線60と、配線60の上面上に設けられるキャップ層68と、配線60と第2の層間絶縁膜との間に設けられるバリア膜62と、を含む。配線60は高融点導電層を含み、配線60の配線幅W1は、キャップ層68の幅W2よりも小さい。バリア膜62は、高融点導電層60が含む元素の化合物からなり、配線60を覆う層間絶縁膜69,70に起因する不純物が配線60内に拡散するのを抑制する。
【選択図】図1
Description
以下、図1乃至図30を参照しながら、本実施形態について詳細に説明する。以下の説明において、同一の機能及び構成を有する要素については、同一符号を付し、重複する説明は必要に応じて行う。
図1を参照して、本実施形態の半導体装置の構成について、説明する。図1は、本実施形態の半導装置の構成を模式的に示す断面図である。
第3の層間絶縁膜72が、配線60及び層間絶縁膜71上に、設けられている。
例えば、密着層67には、窒化チタン(TiN)が用いられる。但し、密着層67の材料は、配線60の材料に応じて、適宜変更されてもよい。例えば、配線がMoによって形成される場合には、窒化モリブデン(MoN)が、密着層67として用いられる。
バリア膜62は、導電層60を形成する材料(配線材)の酸化物又は窒化物である。例えば、配線60がMoを用いて形成された場合、バリア膜62は、二酸化モリブデン(MoO2)を含む。尚、バリア膜62は、酸窒化膜又は炭化膜でもよい。
これに対して、本実施形態の半導体装置の配線構造のように、配線60と層間絶縁膜との間に、バリア膜(拡散防止膜)62が設けられることによって、配線60を形成するための高融点導電層の酸化又は窒化が防止され、層間絶縁膜の形成に起因した配線60の抵抗の上昇が抑制される。
図2乃至図13を参照して、本実施形態の半導体装置が含む配線60の材料及び配線構造の形成条件について、説明する。
図1を用いて説明したように、本実施形態の半導体装置において、高融点導電体(高融点導電層)が、配線60を形成するための材料(配線材)として、用いられている。
図2乃至図5を用いて、本実施形態の半導体装置が含む配線の形成条件について、説明する。
図2は、配線としての高融点導電層の堆積時における基板の加熱温度(以下、成膜温度とよぶ)と高融点導電層の電気的特性との関係を示すグラフである。
図2に示される例において、W層の抵抗率は、400℃の成膜温度において、室温で形成されたW層に対して、30%程度、減少する。
また、図2に示される例において、150℃の成膜温度で形成されたMo層の抵抗率は、室温で形成されたMo層の抵抗率に比較して、20%程度低下し、成膜温度が高くなるにつれて、Mo層の抵抗率の減少率は大きくなる。500℃の成膜温度で形成されたMo層の抵抗率は、室温で形成されたMo層の抵抗率に比較して、60%から70%程度、減少する。
図3において、グラフの横軸は、ポストアニール処理の加熱温度を示している。加熱温度は、400℃から800℃程度に設定されている。図3において、グラフの縦軸は、ポストアニール処理を施した導電層の抵抗率の減少率(単位:[%])を示している。ここでは、室温(25℃〜30℃)の成膜温度で導電層が形成され、かつ、ポストアニール処理が施されていない導電層の抵抗率が、基準(参照値)とされている。
W層の抵抗率は、400℃から750℃の範囲内のポストアニール処理によって、ポストアニール処理なしのW層に比較して、4%から10%程度の範囲内で、減少する。例えば、400℃から750℃の範囲においてポストアニール処理されたW層の抵抗率は、11μΩ・cmから12μΩ・cm程度の大きさを示す。
図4は、高融点導電層の堆積時における封入ガスのガス圧と高融点導電層の抵抗率との関係を示すグラフである。図4において、グラフの横軸は、スパッタガスのガス圧が示されている。図4において、グラフの縦軸は、各ガス圧で形成された導電層(ここでは、W層)の抵抗率が示されている。図4では、アルゴン(Ar)が、スパッタガスに用いられている。図4に示されるArガスのガス圧は、0.08Paから0.8Pa程度の範囲内にそれぞれに設定されている。また、図4では、放電電圧を変化させて、ガス圧に対する配線の抵抗率の変化が、測定されている。尚、図4において、3つの放電電圧A,B,Cのうち、放電電圧Cが最も大きく、放電電圧Aが最も小さく、放電電圧Bが、放電電圧Aと放電電圧Cとの間の大きさに設定されている。
それゆえ、配線としての高融点導電層がスパッタ法によって堆積される場合、放電電圧が300V以上に設定されることが、その配線の抵抗率の低減に有効である。
図6及び図7を用いて、本実施形態の半導体装置における層間絶縁膜の形成条件について、説明する。
さらに、Mo層に対して400℃程度の加熱処理が施された場合、O2のガス圧にほとんど依存せずに、Moの酸化速度はほぼ0nm/sec程度となり、Mo層の表面上に、Mo酸化膜はほとんど形成されなくなる。
図8乃至図13を参照して、配線としての高融点導電層上に設けられるバリア膜及びその形成条件について、説明する。
図8の各サンプルにおいて、各形成時間によってバリア膜が形成された後に、高融点導電層上に、5nm程度の膜厚を有するシリコン窒化膜が形成される。図8において、高融点導電層には、50nm程度の膜厚を有するMo層が用いられている。
図9は、高融点導電体の気化速度を説明するためのグラフである。図9の(a)は、酸素雰囲気中におけるMoの気化速度(気化レート)の2次元マップが示されている。図9の(a)において、グラフの横軸はO2ガス圧(単位:[Pa])を示し、グラフの縦軸は加熱温度を示している。図9の(b)は、O2ガス圧が60Paに設定された場合における、Mo及びWの気化速度と加熱温度との関係を一例として示している。図9の(b)において、グラフの横軸は加熱温度を示し、グラフの縦軸は気化速度を示している。
これによって、バリア膜の形成が原因で配線の抵抗値が上昇するのを、防止できる。
このXRDによる解析結果は、二酸化モリブデン(MoO2)の回折ピークを示している。
高融点導電層60上のバリア膜62は、金属のセルフパッシベーション(自己不動態化)によって、形成されてもよい。この場合、配線材として高融点導電体に、配線材として選択された高融点金属以外の元素(例えば、金属元素)が添加される。以下では、高融点導電層に添加される元素(金属元素)のことを、添加元素又は添加金属とよぶ。
また、添加された金属の酸化物が、Mo酸化物又はW酸化物に比較して、化学的に安定な材料であることが好ましい。
本実施形態の半導体装置は、高融点導電体から構成される配線60を含む。
以下、図14乃至図16を用いて、本実施形態の半導体装置の変形例について説明する。
以下、図17乃至図20を用いて、本実施形態の半導体装置の応用例について、説明する。
本実施形態で述べた高融点導電体から構成される配線は、例えば、電界効果トランジスタ(FET:Field Effect Transistor)に用いることができる。
図18を用いて、本実施形態の半導体装置の応用例2について、説明する。
図19及び図20を用いて、本実施形態の半導体装置の応用例3について、説明する。
本実施形態で述べた高融点導電体から構成される配線は、例えば、抵抗変化型メモリに用いることができる。
図19に示されるように、抵抗変化型メモリは、クロスポイント型メモリセルアレイ1を有している。クロスポイント型メモリセルアレイ1は、例えば、半導体基板10上に積層された層間絶縁膜70,71,72上に設けられている。この場合、半導体基板10上の層間絶縁膜が、クロスポイント型メモリセルアレイ1を形成するための基板として、用いられる。
図21乃至図30を参照して、本実施形態の半導体装置の製造方法について、説明する。
図21乃至図24を用いて、本実施形態の半導体装置の製造方法1について、説明する。図21乃至図24は、本実施形態の半導体装置の製造方法1における各工程の断面工程図を模式的に示している。
図26乃至図30を用いて、本実施形態の半導体装置の製造方法2について、説明する。本製造方法2において、上述の製造方法1と共通の構成要素、工程及び効果に関する説明は、必要に応じて行う。図26乃至図30は、本実施形態の半導体装置の製造方法2における各工程の断面工程図を模式的に示している。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
Claims (10)
- 素子が形成された半導体基板を覆う第1の層間絶縁膜上に設けられた配線と、
前記配線の上面上に設けられるキャップ層と、
前記配線と前記配線を覆う第2の層間絶縁膜との間に設けられるバリア膜と、
を具備し、
前記配線は、高融点導電層を含み、前記配線の配線幅は、前記キャップ層の幅よりも小さく、
前記バリア膜は、前記高融点導電層が含む元素の化合物から構成され、前記第2の層間絶縁膜に起因する不純物が前記配線内に拡散するのを抑制する、
ことを特徴とする半導体装置。 - 前記高融点導電層の再結晶化温度は、1000℃以下である、ことを特徴とする請求項1に記載の半導体装置。
- 前記高融点導電層は、Mo、W、Ru、Ta、Co及びNiを含むグループから選択される少なくとも1つの材料を含む、ことを特徴とする請求項1又は2に記載の半導体装置。
- 前記高融点導電層がMo層を含む場合、前記バリア膜はMoO2膜を含む、ことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記高融点導電層は、前記高融点導電層を構成する高融点金属より化合物生成エネルギーが小さい添加元素をさらに含み、前記バリア膜は、前記添加元素の化合物を含む、ことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記高融点導電層内のバリア膜側における前記添加元素の濃度は、前記高融点導電層内の中央部における前記添加元素の濃度より高い、ことを特徴とする請求項5に記載の半導体装置。
- 半導体基板上に、第1の層間絶縁膜を形成する工程と、
前記第1の層間絶縁膜上に、配線としての高融点導電層を形成する工程と、
所定の配線パターンに加工された前記高融点導電層に対して、還元雰囲気中の第1の熱処理を施す工程と、
前記高融点導電層に対して反応ガス雰囲気中の第2の熱処理を施して、前記高融点導電層が含む金属の化合物から構成されるバリア膜を、前記高融点導電層の露出面上に形成する工程と、
前記高融点導電層を覆う第2の層間絶縁膜を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記高融点導電層は、Mo、W、Ru、Ta、Co及びNiを含むグループから選択される少なくとも1つの材料を含む、ことを特徴とする請求項7に記載の半導体装置の製造方法。
- 高融点金属と前記高融点金属より化合物生成エネルギーが小さい添加元素を含む前記高融点導電層に対して、前記第2の熱処理が施され、
前記添加元素のセルフパッシベーションによって、前記添加元素の化合物を含む前記バリア膜が形成される、ことを特徴とする請求項7又は8に記載の半導体装置の製造方法。 - 前記第1及び第2の熱処理の一方において、前記高融点導電層を結晶化させる、ことを特徴とする請求項7乃至9のいずれか1項に記載の半導体装置の製造方法。
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JP2020155471A (ja) * | 2019-03-18 | 2020-09-24 | 東京エレクトロン株式会社 | 半導体装置およびその製造方法 |
JP7304721B2 (ja) | 2019-03-18 | 2023-07-07 | 東京エレクトロン株式会社 | 半導体装置およびその製造方法 |
JP2023502095A (ja) * | 2019-11-21 | 2023-01-20 | アプライド マテリアルズ インコーポレイテッド | ダイナミックランダムアクセスメモリのビットラインメタルを平滑化する方法及び装置 |
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