JP2023502095A - ダイナミックランダムアクセスメモリのビットラインメタルを平滑化する方法及び装置 - Google Patents
ダイナミックランダムアクセスメモリのビットラインメタルを平滑化する方法及び装置 Download PDFInfo
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- -1 Ruthenium (Ru) Chemical class 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
Claims (20)
- メモリ構造のビットラインメタルの上面を平滑化する方法であって、
基板上のポリシリコン層に、約30オングストロームから約50オングストロームのチタン層を堆積させることと、
前記チタン層に、約15オングストロームから約40オングストロームの第1の窒化チタン層を堆積させることと、
約700℃から約850℃の温度で、前記基板をアニール処理することと、
アニール処理後の第1の窒化チタン層に、約15オングストロームから約40オングストロームの第2の窒化チタン層を堆積させることと、
前記第2の窒化チタン層に、ルテニウムのビットラインメタル層を堆積させることと
を含む方法。 - 前記ビットラインメタル層に、約350℃から約400℃の堆積温度でキャップ層を堆積させることと、
前記キャップ層に、約500℃を上回る堆積温度でハードマスク層を堆積させることと
を更に含む、請求項1に記載の方法。 - 前記キャップ層は、窒化ケイ素又は炭窒化ケイ素の1又は複数を含む、請求項2に記載の方法。
- 前記キャップ層は、約30オングストロームから約50オングストロームである、請求項2に記載の方法。
- 前記キャップ層は、化学気相堆積(CVD)又は原子層堆積(ALD)プロセスによって堆積される、請求項2に記載の方法。
- 前記ハードマスク層は窒化ケイ素を含む、請求項2に記載の方法。
- 前記ハードマスク層は、低圧化学気相堆積(LPCVD)プロセスを用いて堆積される、請求項2に記載の方法。
- 前記ビットラインメタル層に、約400℃を下回る堆積温度でハードマスク層を堆積させること
を更に含む、請求項1に記載の方法。 - 前記ハードマスク層は窒化ケイ素を含む、請求項8に記載の方法。
- 前記ハードマスク層は、低圧化学気相堆積(LPCVD)プロセスを用いて堆積される、請求項8に記載の方法。
- メモリ構造を形成する方法であって、
基板上のポリシリコン層にバリアメタル層を形成することと、
約700℃から約850℃の温度で、前記バリアメタル層をアニール処理することと、
前記バリアメタル層にバリア層を形成することと、
前記バリア層にビットラインメタル層を形成することと
を含む方法。 - 前記バリアメタル層は、前記ポリシリコン層に形成された約30オングストロームから約50オングストロームのチタン層と、前記チタン層に形成された約15オングストロームから約40オングストロームの窒化チタン層である、請求項11に記載の方法。
- 前記バリアメタル層をアニール処理することにより、前記ポリシリコン層にチタンシリサイド層を形成する、請求項12に記載の方法。
- 前記バリア層は、約15オングストロームから約40オングストロームの窒化チタン層である、請求項11に記載の方法。
- 前記ビットラインメタル層は粒成長金属層である、請求項11に記載の方法。
- 化学気相堆積(CVD)又は原子層堆積(ALD)プロセスを用いて、前記ビットラインメタル層に、約350℃から約400℃の堆積温度でキャップ層を形成することと、
低圧化学気相堆積(LPCVD)プロセスを用いて、前記キャップ層に、約500℃を上回る堆積温度でハードマスク層を形成することと
を更に含む、請求項11に記載の方法。 - 前記キャップ層は、約30オングストロームから約50オングストロームである、請求項16に記載の方法。
- 低圧化学気相堆積(LPCVD)プロセスを用いて、前記ビットラインメタル層に、約400℃を下回る堆積温度でハードマスク層を堆積させること
を更に含む、請求項11に記載の方法。 - メモリ構造のビットラインメタルの上面を平滑化する方法であって、
プラズマ気相堆積(PVD)チャンバを用いて、基板上のポリシリコン層に、約30オングストロームから約50オングストロームのチタン層を堆積させることと、
前記チタン層の堆積と前記基板のアニール処理との間で真空を中断することなく、約700℃から約850℃の温度で前記基板をアニール処理することと、
アニール処理後の前記チタン層に、約15オングストロームから約40オングストロームの窒化チタン層を堆積させることと、
前記窒化チタン層に、ルテニウムのビットラインメタル層を堆積させることと
を含む方法。 - 前記ビットラインメタル層に、約350℃から約400℃の堆積温度でキャップ層を堆積させ、前記キャップ層に、約500℃を上回る堆積温度でハードマスク層を堆積させること、又は、
前記ビットラインメタル層に、約400℃を下回る堆積温度でハードマスク層を堆積させることと
を更に含む、請求項19に記載の方法。
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JPH10223556A (ja) * | 1997-02-10 | 1998-08-21 | Toshiba Corp | 半導体装置の製造方法 |
JPH1174354A (ja) * | 1997-06-30 | 1999-03-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001177074A (ja) * | 1999-12-15 | 2001-06-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2007509836A (ja) * | 2003-10-31 | 2007-04-19 | アヴィザ テクノロジー インコーポレイテッド | 窒化シリコンの低温堆積 |
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