TWI593108B - 帶有保護遮罩氧化物的分裂柵溝槽功率金屬氧化物半導體場效應電晶體 - Google Patents

帶有保護遮罩氧化物的分裂柵溝槽功率金屬氧化物半導體場效應電晶體 Download PDF

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TWI593108B
TWI593108B TW104139119A TW104139119A TWI593108B TW I593108 B TWI593108 B TW I593108B TW 104139119 A TW104139119 A TW 104139119A TW 104139119 A TW104139119 A TW 104139119A TW I593108 B TWI593108 B TW I593108B
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trench
conductive material
region
gate
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李亦衡
管靈鵬
宏勇 薛
一鳴 顧
向泱
士彰 黃
拉瑪莫西 謝卡爾
李文軍
虹 常
博德 馬督兒
托魯普 保羅
依瑪茲 哈姆紥
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萬國半導體股份有限公司
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Description

帶有保護遮罩氧化物的分裂柵溝槽功率金屬氧化物半導體場 效應電晶體
本發明的各個方面主要是關於半導體功率裝置，更確切地說，是關於分裂柵電晶體裝置及其製備方法。
功率金屬氧化物半導體場效應電晶體(MOSFET)因其低柵極驅動功率、快速切換速度以及出色的並聯性能等特性，常被用於功率裝置。大多數的功率MOSFET都具有垂直結構的特點，源極和漏極區在柵極溝槽的對邊上，柵極溝槽用多晶矽填充，作為柵極電極。在這種結構中，MOS通道沿溝槽的垂直側壁形成。
分裂柵溝槽結構因其良好的高頻性能和低導通狀態電阻，近年來已超越傳統的溝槽MOSFET，在特定應用中受到普遍歡迎。分裂柵溝槽功率MOSFET包括在柵極溝槽中的兩個電極。第一電極作為柵極電極，控制MOSFET的通道形成，第二電極作為遮罩電極，降低漏極電極和柵極電極之間的電容Cgd。分裂柵溝槽MOSFET現有的製備技術通常複雜且昂貴，處理時通常需要8個或8個以上的掩膜。
正是在這樣的背景下，提出了本發明的實施例。
因此，本發明的一個方面在於提出一種新型改良的帶有多晶矽保護的遮罩氧化物的功率金屬氧化物半導體場效應電晶體。
簡單地說，本發明的各個方面包括具有多個柵極溝槽的半導體裝置，形成在有源晶胞區中的半導體基板中，以及一個或多個溝槽，形成在有源晶胞區之外的區域中的半導體基板中。每個柵極溝槽都有一個在柵極溝槽底部的第一導電材料，以及一個在柵極溝槽頂部的第二導電材料。柵極溝槽中第一導電材料與半導體基板被第一絕緣層隔開。柵極溝槽中第二導電材料與半導體基板被第二絕緣層隔開，與柵極溝槽中第一導電材料被第三絕緣層隔開。一個或多個其他溝槽都含有一部分第一導電材料，呈半U型，在其他溝槽底部，以及第二導電材料在其他溝槽頂部。一個或多個其他溝槽中的第一導電材料和第二導電材料，被第三絕緣層隔開。第一絕緣層比第三絕緣層更厚，第三絕緣層比第二絕緣層更厚。
在一些實施例中，半導體裝置包括一個或多個拾起溝槽，形成在拾起區中的半導體基板中。拾起溝槽包括至少一部分第一導電材料，第一絕緣層將一個或多個拾起溝槽中的一部分第一導電材料與半導體基板隔開。
在一些實施例中，一個或多個其他溝槽都具有一部分第一絕緣層，沿底部和溝槽的至少一個側壁上內襯。
在一些實施例中，形成在有源晶胞區之外區域中半導體基板中的一個或多個溝槽，包括在周邊區域的周邊溝槽，其中周邊區域在有源晶胞區和裝置的邊緣之間。在一些實施例中，周邊溝槽中的第二導電材料與半導體基板被第二絕緣材料隔開。在一些實施例中，每個周邊溝槽都有 不對稱的側壁絕緣物，其中第一絕緣層在裝置邊緣附近的一側，第二絕緣層在有源晶胞區附近的一側。
在一些實施例中，形成在有源晶胞區之外區域中半導體基板中的一個或多個其他溝槽，包括在拾起區中的過渡溝槽，其中過渡溝槽在多個柵極溝槽和拾起溝槽之間。在一些實施例中，在過渡溝槽底部的那部分第一導電材料呈U型。在一些實施例中，過渡溝槽中的那部分第三絕緣層呈U型。
本發明的另一個方面是關於一種半導體裝置的製備方法。該方法包括：a)利用第一掩膜，製備多個溝槽，多個溝槽包括位於有源晶胞區中的一個或多個柵極溝槽，以及一個或多個過渡溝槽，一個或多個位於拾起區的拾起溝槽；b)利用第二掩膜，在多個溝槽中製備帶有第一導電材料的第一導電區，其中柵極溝槽在其底部具有第一導電區，一個或多個過渡溝槽都有一個U-型第一導電區，一個或多個拾起溝槽都用第一導電材料填充；c)為多個溝槽中的至少一部分溝槽，製備一個中間電介質區，其中為一個或多個過渡溝槽製備的中間電介質區呈U型；d)在多個溝槽中的至少一部分溝槽中，製備一個帶有第二導電材料的第二導電區；e)在有源晶胞區中製備一個或多個本體區；f)利用第三掩膜，在有源晶胞區中製備源極區；g)利用第四掩膜，在一個或多個過渡溝槽中，形成到第二導電區的第一電接觸，在一個或多個拾起溝槽中，形成到第一導電區的第一電接觸；h)利用第五掩膜，在柵極溝槽中，形成到第二導電區的第二電接觸；i)沉積一個金屬層；以及j)利用第六掩膜，製成由金屬層構成的源極金屬區和柵極金屬區。
閱讀實施例的以下詳細說明並參照各種圖式，本發明的這些特點和優勢對於本領域的技術人員來說，無疑將顯而易見。
I、II、III‧‧‧剖面線
100‧‧‧分裂柵電晶體裝置
101‧‧‧有源晶胞區
102‧‧‧周邊區
103‧‧‧拾起區
104‧‧‧基板
105、107‧‧‧氧化層
106‧‧‧氮化層
110‧‧‧分裂柵溝槽
111‧‧‧台面結構區
112‧‧‧內襯絕緣物
113‧‧‧遮罩電極
114‧‧‧多晶矽電介質層
115‧‧‧柵極電極
116‧‧‧柵極氧化物
120‧‧‧周邊溝槽
130‧‧‧過渡溝槽
140‧‧‧拾起溝槽
150‧‧‧光致抗蝕劑層
154‧‧‧本體區
155G、155S‧‧‧接觸開口
156‧‧‧源極區
157‧‧‧氮化物墊片
158‧‧‧氮化物阻擋層
159‧‧‧LTO層
160‧‧‧接觸掩膜
162‧‧‧接觸溝槽
164‧‧‧導電插頭
166‧‧‧源極金屬區
168、170‧‧‧柵極金屬區
第1圖表示依據本發明的一個方面，一種分裂柵電晶體裝置的俯視示意圖。
第2圖表示沿第1圖所示的線I、II和III的剖面示意圖。
第3A圖至第3H圖表示依據本發明的一個方面，沿第1圖所示的線I、II和III的剖面示意圖，用於說明分裂柵電晶體裝置的製備過程。
第1圖表示依據本發明的一個方面，一部分分裂柵電晶體裝置的俯視圖。第1圖所示的分裂柵電晶體裝置100包括在有源晶胞區101中的多個陣列分佈的分裂柵溝槽110，在周邊區102的一個周邊溝槽，以及在拾起區103的一個過渡陣列溝槽以及一個拾起溝槽。第2圖表示沿第1圖所示的線I、II和III的剖面示意圖。確切地說，在有源晶胞區101中，每個分裂柵溝槽110都有一個底部電極113(即遮罩電極)以及一個頂部電極115(即柵極電極)。形成在溝槽底部的底部電極113，藉由一個內襯絕緣材料112(即內襯氧化物或遮罩氧化物)，例如氧化物或氮化物，與半導體基板電絕緣，內襯絕緣材料可以覆蓋分裂柵溝槽110的側壁，底部電極113就形成在分裂柵溝槽110中。頂部電極115形成在底部電極和基板104表面之間的分裂柵溝槽的頂部。頂部電極115藉由絕緣材料116(即柵極氧化物)，例如氧化物或氮化物，與半導體基板104隔開，並藉由中間多晶矽電介質層114，與底部電極113隔開。在一些實施例中，柵 極氧化物116的厚度小於中間多晶矽電介質層114的厚度，中間多晶矽電介質層114的厚度小於內襯絕緣材料112的厚度。
周邊溝槽120形成在周邊區102中。周邊溝槽在底部、裝置邊緣附近的側壁和柵極溝槽110附近的底部側壁上內襯氧化物112，沿柵極溝槽110附近的頂部側壁，內襯柵極氧化物116。周邊溝槽120中的柵極電極115位於靠近柵極溝槽110的頂角中，遮罩電極113在柵極電極115下方呈半U型，半U型的中間電介質層114將柵極電極115和遮罩電極113分開。
過渡溝槽130和拾起溝槽140形成在拾起區103中。過渡溝槽130沿溝槽的側壁和底部，具有內襯絕緣物112，例如氧化物。過渡溝槽130中的柵極電極115位於溝槽的中上部，遮罩電極113呈U型，柵極電極115嵌入在U型的開口中。U型的中間電介質層114將柵極電極115和遮罩電極113分開。拾起溝槽140包括一個遮罩電極113，內襯絕緣物112沿溝槽的側壁和底部設置。
第3A圖至第3H圖表示依據本發明的一個方面，沿第1圖所示的線I、II和III的剖面示意圖，用於說明柵極電晶體裝置的製備過程。採用一個N-型裝置用於解釋說明。要注意的是，使用導電類型相反的類似過程，可以製備P-型裝置。在第3A圖中，N-型基板104(例如生長著一個N-外延層的N+矽晶圓)用作裝置的漏極。在一些實施例中，基板104頂部的摻雜濃度約為1×1016/cm3至1×1017/cm3，厚度為2-4μm。在基板104上方使用一個硬掩膜層，例如藉由沉積或熱生長，在基板104上製備一個薄氧化層105，然後在薄氧化層105上方製備一個氮化層106。在一些實施例中，氧化層105在100Å至500Å範圍內，最好是200Å左右。在一些實施例中，氮化層106的厚度約為1500Å至4000Å，最好是3500 Å左右。在氮化層106上方可以沉積另一個氧化層107，形成帶有氧化物/氮化物/氧化物堆疊的硬掩膜。在一些實施例中，氧化層107的厚度約為1000Å至3000Å，最好是2000Å左右。然後，在氧化物/氮化物/氧化物堆疊上使用一個光致抗蝕劑層(圖中沒有表示出)，並利用溝槽掩膜，形成圖案。然後，藉由硬掩膜刻蝕，刻蝕掉氮化層106、氧化層107和105的裸露部分，在矽表面處停止刻蝕，保留將用於掩膜溝槽刻蝕的開口。在半導體基板104中刻蝕溝槽開口，在有源晶胞區101中形成柵極溝槽110，在周邊區102中形成一個周邊溝槽120，在拾起區103中形成一個過渡溝槽130和一個拾起溝槽140。在一些實施例中，這些溝槽的目標深度約為0.6-1.5μm，最好是1.0μm左右。柵極溝槽110之間或柵極溝槽110和周邊溝槽120之間的基板區域111，有時可稱為台面結構區。
在第3B圖中，藉由氧化，生長一個內襯氧化層112。根據裝置低Rds和高擊穿電壓的優化要求，在溝槽壁上生長一個厚內襯絕緣層112到一定厚度。在一些實施例中，內襯絕緣層的厚度約為400-800Å，最好是600Å左右。然後，在溝槽中和半導體基板104上方，沉積第一導電材料113，例如多晶矽，藉由化學機械拋光(CMP)除去氧化層107上方的多晶矽，僅保留柵極溝槽110、過渡溝槽130以及拾起溝槽140中的導電材料。回刻溝槽110、130和140中的第一導電材料層113，在基板104表面下方100-600Å(例如在基板104表面下方300Å左右的地方)處停止刻蝕。第一層導電材料113有時稱為源極多晶矽、遮罩多晶矽或多晶矽。
參見第3C圖，在氧化物/氮化物/氧化物堆疊的頂部，使用一個光致抗蝕劑層150(例如多晶矽掩膜)，覆蓋拾起溝槽140、過渡溝槽130的兩邊以及周邊溝槽120靠近裝置邊緣的一側。然後，如第3C圖所示，在柵極溝槽110、周邊溝槽120以及過渡溝槽130的頂部，回刻裸露的第一導電材料113。由於刻蝕保留了周邊溝槽120中的半U型導電材 料113以及過渡溝槽中的U型導電材料113，因此要以保護內襯絕緣物112以及周邊溝槽120、過渡溝槽130和拾起溝槽140中至少一部分第一導電材料113的一種方式，形成光致抗蝕劑層150的圖案。在一個示例中，利用定時的回刻製程，可以將第一導電材料層113刻蝕到目標深度。在一些實施例中，導電材料層113刻蝕到半導體基板104的表面下方0.55μm左右的深度。
參見第3D圖，沿柵極溝槽110刻蝕後的頂部以及周邊溝槽120，例如利用濕刻蝕，剝去裸露的內襯絕緣物112。製備薄絕緣層116(例如柵極氧化物)，覆蓋柵極溝槽110的溝槽側壁頂部。另外，靠近周邊溝槽120的柵極溝槽110的溝槽壁的頂部，也內襯柵極絕緣物116。然後，在分裂柵溝槽110的第一導電材料層113的底部上方，製備一個中間電介質層114。也沿周邊溝槽120和過渡溝槽130中的導電材料層113，製備(例如藉由氧化)中間電介質層114，使中間電介質層114在周邊溝槽120中呈半U型，在過渡溝槽130中呈U型。柵極氧化物116的厚度約為150至500Å，中間多晶矽電介質層114的厚度約為250至800Å。
第二層導電材料115(例如多晶矽)沉積在溝槽110、120和130的頂部以及基板104上方，藉由CMP，除去氧化層107和光致抗蝕劑層150上方的多晶矽。在多晶矽的具體情況下，第二導電層115的導電材料有時也稱為柵極多晶矽或多晶矽。然後，將第二導電層115(有時也稱為柵極導體)回刻至100Å-600Å，例如基板表面以下300Å左右，使溝槽110、120和130中第二導電材料的頂面凹向半導體基板104的頂面以下。除去光致抗蝕劑150之後，在溝槽110、120、130和140中進行另一個氧化製程，形成絕緣層152，然後藉由CMP，除去氮化層106上方的氧化物152以及氧化層107。
參見第3E圖，利用濕刻蝕，剝去氮化層106。然後，利用本體摻雜注入，形成多個本體區。本次注入，例如，藉由全面注入以及本體擴散，形成本體區154。本體驅動使摻雜物擴散到所需深度。然後，利用源極掩膜，進行源極摻雜注入，在有源晶胞區101中形成多個源極區156。在結構頂部以上，沉積一層氮化物。在一個示例中，氮化層的厚度約為600至1200Å，例如900Å左右。沿水準表面，各向異性地回刻氮化層，從而沿氧化物152附近的壁，形成氮化物墊片157。然後，在該結構上方沉積一個氮化物阻擋層158。在一個示例中，氮化物阻擋層158的厚度約為200Å至500Å，例如300Å左右。然後，如第3E圖所示，沉積一個低溫氧化物(LTO)層和一個含有硼酸的矽玻璃(BPSG)層159。
參見第3F圖，使用第一接觸掩膜。在拾起區103中，利用刻蝕製程，刻蝕ONO堆疊(LTO層159、氮化物阻擋層158、氧化物152)，以觸及頂部導電材料的表面(即過渡溝槽130中的導電材料115和拾起溝槽140中的導電材料113)，形成穿過LTO層159的接觸開口155S和155G，從而在區域II和III中分別接觸到遮罩導體113和柵極導體115。
在第3G圖中，使用另一個接觸掩膜160，藉由另一個刻蝕製程，在有源晶胞區101中柵極溝槽110之間的台面結構區111中，打開源極和本體接觸開口的陣列。確切地說，刻蝕製程從LTO層159開始，在氮化物阻擋層158處停止。隨著氮化物阻擋層158的擊穿，接觸溝槽162就形成了。
然後，在接觸開口155S和155G以及接觸溝槽162的側壁和底部，內襯勢壘金屬(圖中沒有表示出)，並在接觸開口和接觸溝槽中沉積導電材料(例如鎢)，形成導電插頭164。沉積一層金屬。利用金屬掩膜，藉由刻蝕製程，形成一個源極金屬區166和柵極金屬區168和170。 如圖3H所示，所形成的導電插頭164連接到金屬區。然後，根據標準溝槽MOSFET的剩餘步驟，處理晶圓，完成整個過程。
本發明所述的製備方法，利用一個更少的掩膜，保留厚內襯絕緣物112。無需P-掩膜，保護周邊溝槽120中的內襯氧化物112。這使得整個製備過程更加便宜。在絕緣物刻蝕過程中，構成遮罩電極的導電材料113保護內襯絕緣物112，為遮罩導體113和柵極導體115的接頭形成開口。
儘管本發明依據現有的較佳實施例進行了詳細說明，但應明確本說明並不用於局限。例如，雖然上述說明是指n-通道裝置，但是藉由轉換摻雜區的導電類型，就可將本發明用於p-通道裝置。閱讀上述說明後，本發明的各種可選和修正方案對於本領域的技術人員無疑將顯而易見。因此，應由所附的申請專利範圍及其全部等效內容決定本發明的真實意圖及範圍。
I、II、III‧‧‧剖面線
100‧‧‧分裂柵電晶體裝置
101‧‧‧有源晶胞區
102‧‧‧周邊區
103‧‧‧拾起區
110‧‧‧分裂柵溝槽
111‧‧‧台面結構區

Claims (19)

  1. 一種半導體裝置，其包括：複數個柵極溝槽，形成在一有源晶胞區中的一半導體基板中，每一該柵極溝槽都有一第一導電材料在該柵極溝槽的底部，以及一第二導電材料在該柵極溝槽頂部，其中該柵極溝槽中的該第一導電材料與該半導體基板被一第一絕緣層隔開，該複數個柵極溝槽中的該第二導電材料與該半導體基板被一第二絕緣層隔開，並且該複數個柵極溝槽中的該第二導電材料與該複數個柵極溝槽中的該第一導電材料被一第三絕緣層隔開；至少一其他溝槽，形成在有源區之外的區域中的該半導體基板中，其中該至少一其他溝槽至少包含在該至少一其他溝槽底部呈半U型的部分該第一導電材料，以及在該至少一其他溝槽頂部的部分該第二導電材料，其中該至少一其他溝槽中的該第一導電材料和該第二導電材料被該第三絕緣層隔開；以及至少一拾起溝槽，形成在拾起區中的該半導體基板中，該至少一拾起溝槽連接到至少一個該柵極溝槽，該至少一拾起溝槽至少包含部分該第一導電材料，該第一絕緣層將該至少一拾起溝槽中的部分該第一導電材料與該半導體基板隔開。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該半導體基板為N-型半導體基板。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該半導體基板為P-型半導體基板。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該至少一其他 溝槽都有一部分該第一絕緣層，沿溝槽底部和至少一溝槽側壁上內襯。
  5. 如申請專利範圍第1項所述之半導體裝置，其中形成在該有源晶胞區以外區域的該半導體基板中的該至少一其他溝槽，是一周邊區中的一周邊溝槽，該周邊區位於該有源晶胞區和裝置的邊緣之間。
  6. 如申請專利範圍第5項所述之半導體裝置，其中該周邊溝槽中的部分該第二導電材料與該半導體基板被一第二絕緣材料隔開。
  7. 如申請專利範圍第5項所述之半導體裝置，其中每一該周邊溝槽都有不對稱的側壁絕緣，該第一絕緣層在裝置邊緣附近的一側，該第二絕緣層在該有源晶胞區附近的一側。
  8. 一種半導體裝置，其包括：複數個柵極溝槽，形成在一有源晶胞區中的一半導體基板中，每一該柵極溝槽都有一第一導電材料在該柵極溝槽的底部，以及一第二導電材料在該柵極溝槽頂部，其中該柵極溝槽中的該第一導電材料與該半導體基板被一第一絕緣層隔開，該複數個柵極溝槽中的該第二導電材料與該半導體基板被一第二絕緣層隔開，並且該複數個柵極溝槽中的該第二導電材料與該複數個柵極溝槽中的該第一導電材料被一第三絕緣層隔開；以及至少一其他溝槽，形成在有源區之外的區域中的該半導體基板中，其中該至少一其他溝槽至少包含在該至少一其他溝槽底部呈半U型的部分該第一導電材料，以及在該至少一其他溝槽頂部的部分該第二導電材料，其中該至少一其他溝槽中的該第一 導電材料和該第二導電材料被該第三絕緣層隔開；至少一過渡溝槽，形成在該有源晶胞區以外的拾起區中，該至少一過渡溝槽位於該複數個柵極溝槽和一拾起溝槽之間。
  9. 如申請專利範圍第8項所述之半導體裝置，其中該過渡溝槽底部的部分該第一導電材料呈U型。
  10. 如申請專利範圍第9項所述之半導體裝置，其中在該過渡溝槽中的部分該第三絕緣層呈U型。
  11. 如申請專利範圍第1項所述之半導體裝置，其中該第一絕緣層的厚度大於該第三絕緣層的厚度，該第三絕緣層的厚度大於該第二絕緣層的厚度。
  12. 一種半導體裝置的製備方法，其包括：利用一第一掩膜，在一半導體基板中製備複數個溝槽，該複數個溝槽至少包括位於一有源晶胞區中的一柵極溝槽，以及位於拾起區中的至少一過渡溝槽和至少一拾起溝槽；利用一第二掩膜，在該複數個溝槽中製備帶有一第一導電材料的一第一導電區，該柵極溝槽在它們的底部具有該第一導電區，該至少一過渡溝槽具有U型該第一導電區，該至少一拾起溝槽用該第一導電材料填充；為該複數個溝槽中的至少部分溝槽製備一中間電介質區，該至少一過渡溝槽的該中間電介質區呈U型；在該複數個溝槽中的至少部分溝槽中，製備帶有一第二導電材料的一第二導電區；在該半導體基板中製備一本體區； 利用一第三掩膜，在該有源晶胞區中製備源極區；利用一第四掩膜，在該至少一過渡溝槽中，形成到該第二導電區的一第一電接觸，並且在該至少一拾起溝槽中，形成到該第一導電區的該第一電接觸；利用一第五掩膜，在該柵極溝槽中，形成到該第二導電區的一第二電接觸；沉積一金屬層；以及用一第六掩膜，製成由金屬層構成的源極金屬區和柵極金屬區。
  13. 如申請專利範圍第12項所述之製備方法，其中該複數個溝槽進一步包括至少一周邊溝槽，在該有源晶胞區和半導體裝置邊緣之間的周邊區中，該至少一周邊溝槽具有一個半U型的該第一導電區。
  14. 如申請專利範圍第12項所述之製備方法，其中該至少一拾起溝槽連接到至少一該柵極溝槽，該至少一拾起溝槽至少包括部分該第一導電材料，一第一絕緣層將該至少一拾起溝槽中的該第一導電材料與該半導體基板隔開。
  15. 如申請專利範圍第14項所述之製備方法，其中每一該溝槽都具有部分該第一絕緣層，內襯於溝槽底部以及至少一溝槽側壁。
  16. 如申請專利範圍第14項所述之製備方法，其中該至少一過渡溝槽包括位於該有源晶胞區和裝置邊緣之間的溝槽。
  17. 如申請專利範圍第13項所述之製備方法，其中該周邊溝槽中 的部分該第二導電材料與該半導體基板被一第二絕緣層隔開。
  18. 如申請專利範圍第13項所述之製備方法，其中每一該周邊溝槽都具有不對稱的側壁絕緣，一第一絕緣層在裝置邊緣附近的一側，一第二絕緣層在該有源晶胞區附近的一側。
  19. 如申請專利範圍第12項所述之製備方法，其中該過渡溝槽位於該複數個柵極溝槽和該拾起溝槽之間。
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